JP3229058B2 - Method of manufacturing semiconductor device having filling groove isolation region - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an isolation region formed by trench filling isolation (also referred to as trench isolation) in which a trench for isolation is formed in a substrate and the trench is filled with a dielectric to perform element isolation. And a method for producing the same.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, the most common method is to form an element isolation region by selective oxidation (LOCOS) in order to perform element isolation. But,
With the progress of miniaturization of elements, there is a problem that an oxide film called a bird's beak extends to an element formation region in an element isolation region of a LOCOS structure, and thus the element isolation region becomes large. Therefore, as one method of miniaturizing the element isolation region, a trench is dug in the substrate, and the side wall of the trench is insulated, and then the trench is filled with polycrystalline silicon, or another insulator is filled in the trench. Various methods of filling and separating grooves have been studied. In the groove filling and separating method, grooves are formed deeply in a direction substantially perpendicular to the substrate surface by anisotropic etching.

[0003]

SUMMARY OF THE INVENTION The present invention relates to an improvement in an element isolation region by a groove filling method, and more particularly, to a semiconductor device having an isolation region with a higher breakdown voltage than that proposed.
It is an object of the present invention to provide a method for manufacturing a device .

[0004]

In a semiconductor device to which the present invention is directed, a groove having an upwardly open shape is formed in an element isolation region, and the groove is filled with a dielectric material. The dielectric is composed of at least two layers, and the dielectric layer filled in the deep portion of the groove has a higher dielectric constant than the dielectric layer filled in the shallow portion. The preferred shape of the groove formed in the substrate is such that the side wall is nearly perpendicular to the substrate surface in a deep portion, and the side wall is gentler in a shallow portion.

In order to form such an isolation region, the manufacturing method of the present invention includes the following steps (A) to (E). (A) a step of forming a resist pattern having an opening in an isolation region on a silicon substrate; and (B) etching to a depth equal to or less than a half of a predetermined depth of the isolation region by an isotropic etching method using the resist pattern as a mask. (C) a step of forming a groove by etching to a predetermined depth of an isolation region by an anisotropic etching method using the resist pattern as a mask, and (D) forming a high dielectric constant dielectric in a deep portion of the groove. And (E) filling the remaining portion of the groove with a dielectric having a lower dielectric constant than the dielectric. There is a high dielectric constant of silicon nitride as a dielectric (dielectric constant .epsilon.s about 7.4) or Ta 3 _O 5 _(.epsilon.s about 25), the low dielectric constant of silicon oxide as a dielectric (.epsilon.s about 3.9) and organic silicone resins.

[0006]

The lines of electric force from one element region are curved upward at the shallow portion of the groove, and the lines of electric force are more strongly curved upward by the low dielectric constant dielectric filled in the shallow portion, and are separated. The influence from one element region opposed to the other region is less likely to reach the other element region.

[0007]

DETAILED DESCRIPTION FIG. 1 is a representation of the cross-sectional shape of the element isolation region to be more formed to an embodiment. The silicon substrate 2 has a groove 4 formed of a deep portion 4a whose side wall is substantially perpendicular to the substrate surface and a shallow portion 4b whose side wall has a gentle inclination. The deep portion 4a of the groove 4 is filled with a dielectric 6a having a high dielectric constant, and the shallow portion 4b is filled with a dielectric 6b having a lower dielectric constant. For example, silicon nitride is used as the high dielectric constant dielectric 6a, and silicon oxide is used as the low dielectric constant dielectric 6b, for example.

[0008] The angle between the side walls of the shallow portion 4b of the groove 4 and the substrate surface and theta _1, when the angle between the sidewall and the substrate surface of the deep portion 4a and theta _2, a θ _1> θ _2. Lines of electric force acting from the substrate across the element isolation region enter the direction perpendicular to the side wall of the isolation groove 4. Since the groove 4 has a gentle inclination near the surface of the substrate as shown in FIG. 1, the lines of electric force from one element region enter the side wall perpendicularly at the shallow portion 4b and then curve upward. Due to the effect of the inclination of the side wall of the groove 4, lines of electric force from one element region hardly affect the other element region opposed to the element isolation region.

Further, the effect of filling the groove 4 with the high dielectric constant dielectric 6a in the deep portion 4a and filling the low dielectric constant dielectric 6b in the shallow portion 4b is superimposed, and the electric current from one element region is overlapped. After the field lines enter the separation region, they are strongly curved upward, and in the separation region of the deep portion 4a, the electric field lines are strongly curved again when they extend to the upper shallow portion having a lower dielectric constant. The influence from one element region opposed to the other element region is further reduced to the other element region.

As described above, the withstand voltage of the element region opposed to the element isolation region is increased by the shape of the groove 4 in the element isolation region and the effect of the filler. This element isolation region is referred to as CMO
When applied to the S circuit, the lateral NPN transistor of the parasitic thyristor is prevented from turning on, and as a result, the latch-up resistance is improved.

Next, an embodiment for manufacturing the element isolation region of FIG. 1 will be described with reference to FIG. (A) A layer to be a mask for etching the substrate 2 is formed on the surface of the P-type silicon substrate 2. The layer is, for example, a silicon oxide film 10 and a resist layer 12 formed thereon. (B) The resist layer 12 is patterned by photolithography so as to have an opening 14 in an element isolation region.

(C) Using the resist layer 12 as a mask, the silicon oxide film 10 is subjected to isotropic etching by wet etching or isotropic dry etching, and subsequently, the substrate 2 is also subjected to isotropic etching. The etching depth is １ ／ or less of a predetermined depth of a groove to be formed. In the isotropic etching, side etching also occurs, and the region to be etched advances to the lower side of the resist layer 12 and the etched region (shallow portion 4).
The side wall of b) has a gentler slope than the direction perpendicular to the substrate surface.

(D) Next, using the resist layer 12 as a mask, the substrate 2 is etched to a predetermined depth by anisotropic dry etching to form a deep portion 4a of a groove. The depth of the groove 4 composed of the deep part 4a and the shallow part 4b is about the same as the well, for example, 1 to 3.5 μm.

Thereafter, the resist 12 is removed, and the groove 4 is filled with a dielectric. A silicon nitride film is deposited on the entire surface to fill a high dielectric constant dielectric in a deep portion of the groove, and is etched back to be left in the deep portion of the groove. Next, for example, a silicon oxide film is deposited as a low dielectric constant dielectric material, and is etched back to leave the silicon resin only in the trench. Thereby, the deep portion of the trench is filled with silicon nitride, and the shallow portion is filled with silicon oxide, and the state shown in FIG. 1 is obtained.

In the present invention, the shape of the separating groove is not limited to the shape shown in FIG. 1 , and for example, the sectional shape of the groove may be V-shaped. The V-shaped groove can be formed by etching the silicon substrate with an alkaline etchant. The method of filling the groove with the filler is not limited to the method described in the embodiment. Further, in the state where the filler is filled, the material is not limited to the one divided into an upper layer and a lower layer as shown in FIG. The groove may be filled with a dielectric so as to be made of a body.

[0016]

According to the present invention , in the groove filling isolation region formed by the present invention, the groove is formed in an upwardly open shape, and the dielectric layer filled in the deep part of the groove is filled in the shallow part. Since the dielectric constant is higher than that of the formed dielectric layer, the lines of electric force from one element region are curved upward at the shallow part of the groove, and the low dielectric constant dielectric is filled in the shallow part. The lines of electric force are more strongly bent upward by the body, and the influence from one element region opposed to the separation region is less likely to reach the other element region. As a result, the withstand voltage between the element regions facing each other across the isolation region is improved, and the latch-up withstand voltage of the parasitic thyristor is also improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an element isolation region formed according to one embodiment.

FIG. 2 is a process sectional view showing one embodiment .

[Explanation of symbols]

 2 Silicon substrate 4 Separation groove 4a Deep groove portion 4b Shallow groove portion 6a High dielectric constant dielectric 6b Low dielectric constant dielectric 12 Resist pattern

Claims (1)

(57) [Claims] 1. A method for manufacturing a semiconductor device, comprising the steps of: (A) to (E); (A) a step of forming a resist pattern having an opening in a separation region on a silicon substrate; (B) etching using the resist pattern as a mask to a depth equal to or less than a half of a predetermined depth of the separation region by an isotropic etching method; (C) a step of forming a groove by etching to a predetermined depth of the isolation region by an anisotropic etching method using the resist pattern as a mask, and (D) forming a high dielectric constant dielectric in a deep portion of the groove. (E) filling the remaining portion of the groove with a dielectric having a lower dielectric constant than the dielectric.