WO1991006981A1 - Mos logic in bicmos circuits - Google Patents

Mos logic in bicmos circuits Download PDF

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Publication number
WO1991006981A1
WO1991006981A1 PCT/EP1990/001747 EP9001747W WO9106981A1 WO 1991006981 A1 WO1991006981 A1 WO 1991006981A1 EP 9001747 W EP9001747 W EP 9001747W WO 9106981 A1 WO9106981 A1 WO 9106981A1
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WIPO (PCT)
Prior art keywords
logic
mos
gates
gate
mos logic
Prior art date
Application number
PCT/EP1990/001747
Other languages
German (de)
French (fr)
Inventor
Rudolf Koblitz
Kuno Lenz
Philippe Larnicol
Original Assignee
Deutsche Thomson-Brandt Gmbh
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Publication of WO1991006981A1 publication Critical patent/WO1991006981A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology

Definitions

  • the invention relates to a MOS logic in integrated BICMOS circuits.
  • the BICMOS technology can be used to advantage.
  • On such a chip e.g. bipolar devices for analog circuits and CMOS logic for digital circuits.
  • BICMOS Bipolar and CMOS technology are used together on one chip.
  • CMOS means: Complementary Metal Oxide Semiconduc- tor.
  • I2L means: Integrated injection logic. Bipolar technology, CMOS and I2L are e.g. described in "Worksheet No. 110", from the 'Elektronik' magazine, issue 4/1978, pages 129-130 and issue 5/1978, pages 97-98.
  • a bipolar I2L gate consists of an NPN transistor that acts as a switch. works and its injector is operated with a pnp transistor as a current source. I2L gates require only a very small chip area, but the number of outputs per gate is very limited, for example to four. In addition, I2L logic is sensitive to voltage drops on ground and injector lines. Compared to I2L gates, CMOS gates have a higher immunity to interference, but more transistors are required for a conventional CMOS gate than for a corresponding I2L gate.
  • the invention is based on the object of specifying a circuit for an integrated circuit in which the advantages of the I2L circuit technology are connected to those of the CMOS circuit technology.
  • the solution is to build MOS gates in an I2L-like structure. This can e.g. well implemented in integrated circuits with BICMOS technology.
  • CWL I2L-like structure for MOS gates in BICMOS
  • - CWL logic is circuit compatible with I2L logic.
  • the slower logic behavior results in a lower strahlungt interference radiation for adjacent analog circuit structures on the chip.
  • an I2L control logic is required for the I2L gates with a corresponding number of parallel outputs. Because of the limitation of the number of outputs, for example to four, the control logic then has a tree structure with a corresponding time delay due to several logic gates connected in series and a corresponding space requirement on the chip.
  • CWL gates can, for example, provide more than twenty outputs. Such a control logic is correspondingly simplified. The number of parallel outputs is essentially only limited by the resulting capacitive load and the required speed.
  • a symbolic layout can be used very easily in the circuit design of CWL logic.
  • Fig. 1 shows a CWL gate structure
  • FIG. 2 layout of a CWL inverter with four outputs
  • FIG. 1 shows the structure of a CWL gate with one input (11) and several outputs (121, 122, 129). For example, there may be over twenty such parallel outputs.
  • the associated output N-MOS transistors (131, 132, 139) are on the one hand with their respective Source jointly connected to the ground line (16) and on the other hand with its respective gate to the input (11). With their respective drain, they form a multi-drain output (121, 122, 129).
  • the signals of the outputs (121, 122, 129) are formed in the form of a multiple-input NAND link by a plurality of signals, not shown, supplied from the outside, at the input (11), or in the form of an NOT link with one externally supplied signal at the input (11).
  • An injection current (18) into the gates of the N-MOS transistors (131, 132, 139) is supplied by the drain of a P-MOS transistor (17), which has its source connected to the supply voltage (14) and is connected with its gate to a reference current (15).
  • the reference current (15), hereinafter referred to as I-bias defines the size of the injection current (18), approximately in the range from 0.1 to 10 ⁇ A.
  • the reference current (15) can e.g. also initially feed a further PMOS transistor, which is connected as a current mirror and is connected to the I-bias connections (15, 25, 351, 352).
  • This PMOS transistor has the same structure as the PMOS transistor (17) from FIG. 1. This automatically compensates for manufacturing-related tolerances of the gate-source voltages of such transistors (17).
  • a CWL logic gate is therefore characterized by a current source (17, 18) at the input (11) and multi-open drain outputs (121, 122, 129).
  • the input (11) forms a 'CMOS-wired AND 1 logic with the signals supplied to it from the outside.
  • FIG. 2 shows the physical layout of a CWL gate with a gate structure according to FIG. 1, which is arranged between a metal connection for the supply voltage (24) and a metal connection (26) for ground. There are also the metal connection of the input (21) and four metal connections Inferences for the four outputs (221, 222, 223, 229) are shown. In addition, the I-bias line (25) made of polycrystalline silicon can be seen.
  • the fields (271 - 279) each show a type of marking for the different areas of the CWL gate:
  • FIG. 3 shows four adjacent CWL gates according to FIG. 2. It can be seen that the ground connections of two gates (361, 362) and the I-bias connections of two gates (351, 352) are connected.
  • the supply voltage connections (34) of all four gates are also combined.
  • the four inputs corresponding to the input (31) each correspond to the input (21) of the gate from FIG. 2,
  • the sixteen outputs corresponding to the four outputs (321, 322, 323, 329) each correspond to the four outputs (221, 222 , 223, 229) of the gate from FIG. 2.
  • the wiring of the CWL gates can advantageously be simplified by shifting the gate connections on the chip surface.
  • the input (21) of the 2 is to be connected to the output (37) of the quadruple gate from FIG. 3, the input (21) of the gate from FIG. 2 can advantageously be simply shifted at the location of the output (229).
  • the input (21) of the first gate is directly adjacent to the output (37) of the gate from FIG. 3 and a connection between the two is very short.
  • each gate is mirror-symmetrically connected in an H-shaped N + diffusion structure and only this common source surface of each gate or double gate is connected by a metal connection Ground (26, 361, 362) is connected.
  • a metal connection Ground 26, 361, 362
  • Tab. 1 shows the logical inputs (a, b, c, d) and output signals (A, B, C, D, E, F, G, H, I, J) of such a decoder ⁇ ben:
  • Fig. 4 shows a section of the wiring diagram for this decoder.
  • Eight logic gate inputs (a, b, c, d and a, b, c, d inverted) of eight logic gates (41) with corresponding metal contacts (43) are shown.
  • Four of these logic gate inputs (a, b, c, d) correspond to the logic input signals a, b, c, d in Table 1.
  • five (42) out of ten connecting lines for logic gate out ⁇ gears and five (F to J) of ten decoder outputs are shown, which correspond to the logical output signals (A to J) in Table 1.
  • the logical output signals (A to J) of the decoder are formed as follows (inv. Means logically inverted): + b (inv.) + c (inv. + d (inv.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

In BICMOS circuits, the complementary MOS logic requires more transistor functions than does a I2L logic in bipolar circuits. By means of an improved MOS gate structure similar to that of I2L (CWL logic), the space requirements of the MOS logic are considerably reduced, while maintaining the noise-voltage sensitivity at the same level as in prior art CMOS logics. Because of the slower logic behaviour, the analog circuit structures are exposed to lower levels of noise radiation.

Description

MOS-Logik in BICMOS-Schaltkreisen MOS logic in BICMOS circuits
Die Erfindung betrifft eine MOS-Logik in integrierten BICMOS-Schaltkreisen.The invention relates to a MOS logic in integrated BICMOS circuits.
Für die Herstellung von hochintegrierten Schaltkreisen, z.B. TV-Signalprozessoren, kann vorteilhaft die BICMOS-Technolo- gie verwendet werden. Auf einem solchen Chip verwendet man z.B. für analoge Schaltungen bipolare Bauelemente und für digitale Schaltungen CMOS-Logik.For the manufacture of highly integrated circuits, e.g. TV signal processors, the BICMOS technology can be used to advantage. On such a chip, e.g. bipolar devices for analog circuits and CMOS logic for digital circuits.
BICMOS bedeutet: Bipolar- und CMOS-Technologie werden gemein¬ sam auf einem Chip verwendet. CMOS bedeutet: Komplementäres Metall-Oxid Silizium (Complementary Metal Oxide Semiconduc- tor) . I2L bedeutet: Integrierte Injektionslogik. Bipolare Technologie, CMOS und I2L sind z.B. beschrieben i "Arbeits- blatt Nr. 110", aus der Zeitschrift 'Elektronik' , Heft 4/1978, Seiten 129-130 und Heft 5/1978, Seiten 97-98.BICMOS means: Bipolar and CMOS technology are used together on one chip. CMOS means: Complementary Metal Oxide Semiconduc- tor. I2L means: Integrated injection logic. Bipolar technology, CMOS and I2L are e.g. described in "Worksheet No. 110", from the 'Elektronik' magazine, issue 4/1978, pages 129-130 and issue 5/1978, pages 97-98.
Ein bipolares I2L-Gatter besteht aus einem npn-Transistor, der als Schalter. arbeitet und dessen Injektor mit einem pnp- Transistor als Stromquelle betrieben wird. I2L-Gatter benöti¬ gen nur eine sehr geringe Chip-Fläche, aber die Anzahl der Ausgänge pro Gatter ist stark begrenzt, z.B. auf vier. Außer¬ dem ist I2L-Logik empfindlich gegenüber Spannungsabfällen auf Masse- und Injektor-Leitungen. Gegenüber I2L-Gattern haben CMOS-Gatter eine höhere Störun- empfindlichkeit, allerdings benötigt man für ein konventio¬ nelles CMOS-Gatter mehr Transistoren als für ein entsprechen¬ des I2L-Gatter.A bipolar I2L gate consists of an NPN transistor that acts as a switch. works and its injector is operated with a pnp transistor as a current source. I2L gates require only a very small chip area, but the number of outputs per gate is very limited, for example to four. In addition, I2L logic is sensitive to voltage drops on ground and injector lines. Compared to I2L gates, CMOS gates have a higher immunity to interference, but more transistors are required for a conventional CMOS gate than for a corresponding I2L gate.
Der Erfindung liegt die Aufgabe zugrunde, eine Schaltung für einen integrierten Schaltkreis anzugeben, in der die Vortei¬ le der I2L-Schaltkreistechnologie mit denen der CMOS-Schalt- kreistech.nologie verbunden sind.The invention is based on the object of specifying a circuit for an integrated circuit in which the advantages of the I2L circuit technology are connected to those of the CMOS circuit technology.
Diese Aufgabe wird durch die im Patentanspruch 1 angegebenen Merkmale gelöst. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen beschrieben.This object is achieved by the features specified in claim 1. Advantageous developments of the invention are described in the subclaims.
Die Lösung besteht darin, daß MOS-Gatter in einer I2L-ähnli- chen Struktur aufgebaut werden. Dies läßt sich z.B. gut in integrierten Schaltkreisen mit BICMOS-Technologie verwirkli¬ chen.The solution is to build MOS gates in an I2L-like structure. This can e.g. well implemented in integrated circuits with BICMOS technology.
Durch die Verwendung einer I2L-ähnlichen Struktur für MOS- Gatter in BICMOS, im folgenden CWL bzw. CWL-Technologie ge¬ nannt, ergeben sich folgende Vorteile:The use of an I2L-like structure for MOS gates in BICMOS, hereinafter referred to as CWL or CWL technology, results in the following advantages:
- CWL-Logik ermöglicht eine Chipflächeneinsparung von ca. 50% gegenüber konventioneller CMOS-Logik.- CWL logic enables chip area savings of approx. 50% compared to conventional CMOS logic.
- CWL-Logik ist Schaltkreis-kompatibel mit I2L-Logik.- CWL logic is circuit compatible with I2L logic.
- CWL-Gatter sind unempfindlich gegenüber SpannungsSchwankun¬ gen auf Masse- und Injektorleitungen.- CWL gates are insensitive to voltage fluctuations on ground and injector lines.
- Durch langsameres Logikverhalten ergibt sich für auf dem Chip benachbarte Analog-Schaltungsstrukturen eine ge¬ ringere Ξtöreinstrahlung. Wenn z.B. gleichzeitig viele I2L-Gatter .angesteuert werden sollen, benötigt man eine I2L-Ansteuerlogik für die I2L- Gatter mit entsprechend vielen parallelen Ausgängen. Wegen der Begrenzung der Anzahl der Ausgänge, z.B. auf vier, hat die Ansteuerlogik dann eine Baumstruktur mit entsprechen¬ der zeitlicher Verzögerung durch mehrere hintereinander- geschaltete Logik-Gatter und einen entsprechenden Platzbe¬ darf auf dem Chip. CWL-Gatter können aber z.B. mehr als zwanzig Ausgänge bereitstellen. Entsprechend vereinfacht sich eine solche Ansteuerlogik. Die Anzahl der parallelen Ausgänge ist dabei im wesentlichen nur durch die dadurch bedingte kapazitive Last und die erforderliche Geschwindig¬ keit begrenzt.The slower logic behavior results in a lower strahlungt interference radiation for adjacent analog circuit structures on the chip. If, for example, many I2L gates are to be controlled simultaneously, an I2L control logic is required for the I2L gates with a corresponding number of parallel outputs. Because of the limitation of the number of outputs, for example to four, the control logic then has a tree structure with a corresponding time delay due to several logic gates connected in series and a corresponding space requirement on the chip. However, CWL gates can, for example, provide more than twenty outputs. Such a control logic is correspondingly simplified. The number of parallel outputs is essentially only limited by the resulting capacitive load and the required speed.
Beim Schaltungsdesign von CWL-Logik kann sehr einfach ein symbolisches Layout benutzt werden.A symbolic layout can be used very easily in the circuit design of CWL logic.
Nachstehend wird ein Ausführungsbeispiel der Erfindung an¬ hand der Zeichnungen erläutert. Diese zeigen in:An exemplary embodiment of the invention is explained below with reference to the drawings. These show in:
Fig. 1 eine CWL-GatterstrukturFig. 1 shows a CWL gate structure
Fig. 2 Layout eines CWL-Inverters mit vier AusgängenFig. 2 layout of a CWL inverter with four outputs
Fig. 3 Layout von vier zusammengef ßten CWL-InverternFig. 3 layout of four combined CWL inverters
Fig. 4 Verdrahtung für eine Decoderlogik nach Tab. 1Fig. 4 wiring for a decoder logic according to Tab. 1
In Fig. 1 ist die Struktur eines CWL-Gatters mit einem Ein¬ gang (11) und mehreren Ausgängen (121, 122, 129) darge¬ stellt. Es können z.B. über zwanzig solcher parallelen Aus¬ gänge vorhanden sein. Die zugehörigen Ausgangs-N-MOS-Transi- storen (131, 132, 139) sind einerseits mit ihrer jeweiligen Source gemeinsam an die Masse-Leitung (16) und andererseits mit ihrem jeweiligen Gate an den Eingang (11) angeschlossen. Mit ihrem jeweiligen Drain bilden sie einen Multi-Drain-Aus- gang (121, 122, 129).1 shows the structure of a CWL gate with one input (11) and several outputs (121, 122, 129). For example, there may be over twenty such parallel outputs. The associated output N-MOS transistors (131, 132, 139) are on the one hand with their respective Source jointly connected to the ground line (16) and on the other hand with its respective gate to the input (11). With their respective drain, they form a multi-drain output (121, 122, 129).
Die Signale der Ausgänge (121, 122, 129) werden in Form ei¬ ner Mehrfach-Eingangs-NAND-Verknüpfung durch mehrere von au¬ ßen zugeführte, nicht dargestellte Signale am Eingang (11) gebildet oder in Form einer NOT-Verknüpfung mit einem von außen zugeführten Signal am Eingang (11). Ein Injektions¬ strom (18) in die Gates der N-MOS-Transistören (131, 132, 139) wird von dem Drain eines P-MOS-Transistor (17) gelie¬ fert, der mit seiner Source an die Versorgungsspannung (14) und mit seinem Gate an einen Referenzstrom (15) angeschlos¬ sen ist. Der Referenzstrom (15), im folgenden I-Bias ge¬ nannt, legt die Größe des Injektionsstromes (18) fest, etwa im Bereich von 0,1 bis 10 μA.The signals of the outputs (121, 122, 129) are formed in the form of a multiple-input NAND link by a plurality of signals, not shown, supplied from the outside, at the input (11), or in the form of an NOT link with one externally supplied signal at the input (11). An injection current (18) into the gates of the N-MOS transistors (131, 132, 139) is supplied by the drain of a P-MOS transistor (17), which has its source connected to the supply voltage (14) and is connected with its gate to a reference current (15). The reference current (15), hereinafter referred to as I-bias, defines the size of the injection current (18), approximately in the range from 0.1 to 10 μA.
Der Referenzstrom (15) kann z.B. auch zunächst einen weite¬ ren PMOS-Transistor speisen, der als Stromspiegel geschaltet ist und an die I-Bias-Anschlüsse (15, 25, 351, 352) ange¬ schlossen wird. Dieser PMOS-Transistor hat den gleichen Auf¬ bau wie der PMOS-Transistor (17) aus Fig. 1 . Dadurch werden automatisch herstellungsbedingte Toleranzen der Gate-Source- Spannungen solcher Transistoren (17) ausgeglichen.The reference current (15) can e.g. also initially feed a further PMOS transistor, which is connected as a current mirror and is connected to the I-bias connections (15, 25, 351, 352). This PMOS transistor has the same structure as the PMOS transistor (17) from FIG. 1. This automatically compensates for manufacturing-related tolerances of the gate-source voltages of such transistors (17).
Ein CWL-Logikgatter ist also gekennzeichnet durch eine Strom¬ quelle (17, 18) am Eingang (11) und Multi-Open-Drain-Ausgän- ge (121, 122, 129). Der Eingang (11) bildet mit den ihm von außen zugeführten Signalen eine 'CMOS-wired AND1 -Logik.A CWL logic gate is therefore characterized by a current source (17, 18) at the input (11) and multi-open drain outputs (121, 122, 129). The input (11) forms a 'CMOS-wired AND 1 logic with the signals supplied to it from the outside.
Fig. 2 zeigt das physikalische Layout eines CWL-Gatters mit einer Gatterstruktur gemäß Fig. 1, das zwischen einem Me¬ tall-Anschluß für die VersorgungsSpannung (24) und einem Me¬ tall-Anschluß (26) für Masse angeordnet ist. Es sind weiter der Metall-Anschluß des Eingangs (21) und vier Metall-An- Schlüsse für die vier Ausgänge (221, 222, 223, 229) darge¬ stellt. Außerdem erkennt man die I-Bias-Leitung (25) aus po¬ lykristallinem Silizium.FIG. 2 shows the physical layout of a CWL gate with a gate structure according to FIG. 1, which is arranged between a metal connection for the supply voltage (24) and a metal connection (26) for ground. There are also the metal connection of the input (21) and four metal connections Inferences for the four outputs (221, 222, 223, 229) are shown. In addition, the I-bias line (25) made of polycrystalline silicon can be seen.
In den Feldern (271 - 279) ist jeweils eine Markierungsart für die verschiedenen Bereiche des CWL-Gatters dargestellt:The fields (271 - 279) each show a type of marking for the different areas of the CWL gate:
Markierung 271 vergrabene Diffusionsebene (buried layer) Markierung 272 Epitaxie-Bereich Markierung 273 aktiver Bereich Markierung 274 P+ Diffusion Markierung 275 N- Diffusion Markierung 276 N+ Diffusion Markierung 277 polykristallines Silizium Markierung 278 Kontakt zwischen Metall und polykristal¬ linem SiliziumMarking 271 buried layer (diffusion plane) Marking 272 Epitaxial area Marking 273 Active area Marking 274 P + diffusion marking 275 N- diffusion marking 276 N + diffusion marking 277 polycrystalline silicon marking 278 Contact between metal and polycrystalline silicon
Markierung 279 MetallisierungsebeneMarking 279 metallization level
Fig. 3 zeigt vier benachbarte CWL-Gatter gemäß Fig. 2. Man erkennt, daß jeweils die Masse-Anschlüsse zweier Gatter (361, 362) und die I-Bias-Anschlüsse zweier Gatter (351, 352) verbunden sind.FIG. 3 shows four adjacent CWL gates according to FIG. 2. It can be seen that the ground connections of two gates (361, 362) and the I-bias connections of two gates (351, 352) are connected.
Die Versorgungsspannungsanschlüsse (34) aller vier Gatter sind ebenfalls zusammengef ßt. Die vier Eingänge entspre¬ chend dem Eingang (31) entsprechen jeweils dem Eingang (21) des Gatters aus Fig. 2, die sechzehn Ausgänge entsprechend den vier Ausgängen (321, 322, 323, 329) entsprechen jeweils den vier Ausgängen (221, 222, 223, 229) des Gatters aus Fig. 2.The supply voltage connections (34) of all four gates are also combined. The four inputs corresponding to the input (31) each correspond to the input (21) of the gate from FIG. 2, the sixteen outputs corresponding to the four outputs (321, 322, 323, 329) each correspond to the four outputs (221, 222 , 223, 229) of the gate from FIG. 2.
Die Verdrahtung der CWL-Gatter läßt sich durch Verschiebung der Gatteranschlüsse auf der Chip-Fläche vorteilhaft verein¬ fachen.The wiring of the CWL gates can advantageously be simplified by shifting the gate connections on the chip surface.
Wenn beispielsweise die Gatter aus Fig. 2 und Fig. 3 benach¬ bart auf einem Chip angeordnet sind und der Eingang (21) des Gatters aus Fig. 2 an den Ausgang (37) des Vierfach-Gatters aus Fig. 3 angeschlossen werden soll, kann der Eingang (21) des Gatters aus Fig. 2 vorteilhaft einfach an dem Ort des Ausgangs (229) verschoben werden. Dadurch ist der Eingang (21) des ersten Gatters direkt dem Ausgang (37) des Gatters aus Fig. 3 benachbart und eine Verbindung zwischen beiden ist sehr kurz.If, for example, the gates from FIGS. 2 and 3 are arranged on a chip and the input (21) of the 2 is to be connected to the output (37) of the quadruple gate from FIG. 3, the input (21) of the gate from FIG. 2 can advantageously be simply shifted at the location of the output (229). As a result, the input (21) of the first gate is directly adjacent to the output (37) of the gate from FIG. 3 and a connection between the two is very short.
In Fig. 2 und Fig. 3 erkennt man, daß die Source-Anschlüsse jedes Gatters Spiegelsymmetrisch in einer H-förmigen N+ Dif¬ fusions-Struktur verbunden sind und nur diese gemeinsame Source-Fläche jedes Gatters bzw. Doppelgatters durch einen Metall-Anschluß an Masse (26, 361, 362) verbunden ist. Außer¬ dem gibt es nur gemeinsame Versorgungsspannungs-Metallan- schlüsse (an 34) für alle vier Gatter in Fig. 3 . Diese Ma߬ nahmen führen vorteilhaft zu einer weiteren Reduktion der benötigten Chip-Fläche und bieten eine größere Freiheit in der Verdrahtung der Gatter untereinander.2 and 3 that the source connections of each gate are mirror-symmetrically connected in an H-shaped N + diffusion structure and only this common source surface of each gate or double gate is connected by a metal connection Ground (26, 361, 362) is connected. In addition, there are only common supply voltage metal connections (at 34) for all four gates in FIG. 3. These measures advantageously lead to a further reduction in the chip area required and offer greater freedom in the wiring of the gates to one another.
Dadurch können auch komplexere Logikfunktionen, wie z.B. ein Binär-zu-Dezimal-Decoder, vorteilhaft mit geringem Verdraht¬ ungsaufwand aufgebaut werden. In der folgenden Tabelle (Tab. 1) sind die logischen Ein- (a, b, c, d) und Ausgangssignale (A, B, C, D, E, F, G, H, I, J) eines solchen Decoders angege¬ ben: As a result, even more complex logic functions, such as a binary-to-decimal decoder, can advantageously be set up with little wiring effort. The following table (Tab. 1) shows the logical inputs (a, b, c, d) and output signals (A, B, C, D, E, F, G, H, I, J) of such a decoder ¬ ben:
a b c d A B C D E F G H I Ja b c d A B C D E F G H I J
O O O O 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0OOOO 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
1 0 0 1 1 0 0 0 0 0 0 0 0 0 Tab.1 0 0 1 1 0 0 0 0 0 0 0 0 0 Tab.
Fig. 4 zeigt einen Ausschnitt aus dem Verdrahtungsschema für diesen Decoder. Es sind acht Logik-Gatter-Eingänge (a, b, c, d und a, b, c, d invertiert) von acht Logik-Gattern (41) mit entsprechenden Metall-Kontakten (43) dargestellt. Davon ent¬ sprechen vier Logik-Gatter-Eingänge (a, b, c, d) den logi¬ schen Eingangssignalen a, b, c, d in Tabelle 1. Weiter sind fünf (42) von zehn Verbindungsleitungen für Logik-Gatter-Aus¬ gänge und fünf (F bis J) von zehn Decoder-Ausgängen darge¬ stellt, die den logischen Ausgangssignalen (A bis J) in Ta¬ belle 1 entsprechen.Fig. 4 shows a section of the wiring diagram for this decoder. Eight logic gate inputs (a, b, c, d and a, b, c, d inverted) of eight logic gates (41) with corresponding metal contacts (43) are shown. Four of these logic gate inputs (a, b, c, d) correspond to the logic input signals a, b, c, d in Table 1. Furthermore, five (42) out of ten connecting lines for logic gate out ¬ gears and five (F to J) of ten decoder outputs are shown, which correspond to the logical output signals (A to J) in Table 1.
Auf diesen Verbindungsleitungen (42) befinden sich über den acht Logik-Gatter-Eingängen (a, b, c, d und a, b, c, d inver¬ tiert) weitere Metallkontakte von den Ausgängen der entspre¬ chenden Logik-Gatter (41). Jeweils ein Ausgang von vier (a bis d) der Logik-Gatter (41) ist mit einem entsprechenden Eingang der anderen vier (a bis d invertiert) der Logik-Gat¬ ter (41) verbunden.On these connecting lines (42) there are further metal contacts from the outputs of the corresponding logic gates (41) above the eight logic gate inputs (a, b, c, d and a, b, c, d inverted) ). One output each from four (a to d) of the logic gates (41) is connected to a corresponding input of the other four (a to d inverted) of the logic gates (41).
Die logischen Ausgangssignale (A bis J) des Decoders werden folgendermaßen gebildet (inv. bedeutet logisch invertiert) : + b(inv. ) + c(inv. + d(inv.The logical output signals (A to J) of the decoder are formed as follows (inv. Means logically inverted): + b (inv.) + c (inv. + d (inv.
+ b(inv. ) + c(inv. + d+ b (inv.) + c (inv. + d
+ b(inv. ) + c + d(inv.+ b (inv.) + c + d (inv.
+ b(inv. ) + c + d+ b (inv.) + c + d
+ b + c(inv. + d(inv.+ b + c (inv. + d (inv.
+ b + c(inv. + d+ b + c (inv. + d
+ b + c + d(inv.+ b + c + d (inv.
+ b + c + d+ b + c + d
+ b(inv. ) + c(inv. + d(inv.
Figure imgf000010_0001
+ b(inv. ) + c(inv. + d + b (inv.) + c (inv. + d (inv.
Figure imgf000010_0001
+ b (inv.) + c (inv. + d

Claims

P a t e n t a n s p r ü c h e Patent claims
1. MOS-Logik in integrierten BICMOS-Schaltkreisen, dadurch gekennzeichnet, daß MOS-Logik-Gatter (Fig. 1 bis 3) in einer I2L-ähnlichen Struktur (Fig. 1) aufgebaut sind.1. MOS logic in integrated BICMOS circuits, characterized in that MOS logic gates (Fig. 1 to 3) are constructed in an I2L-like structure (Fig. 1).
2. MOS-Logik nach Anspruch 1, dadurch gekennzeichnet, daß die Logik-Gatter (Fig. 1 bis 3) jeweils einen PMOS-Tran¬ sistor (17) enthalten, der eine Stromquelle bildet, und daß die Logik-Gatter (Fig. 1 bis 3) jeweils mindestens einen NMOS-Transistor (131, 132 bis 139) enthalten, des¬ sen Steuereingang an die Stromquelle angeschlossen ist und an dessen Steuereingang mindestens ein logisches Eingangssignal anliegt (11) und an dessen offenem Aus¬ gang (121, 122 bis 129) ein logisches Ausgangssignal abgreifbar ist.2. MOS logic according to claim 1, characterized in that the logic gates (Fig. 1 to 3) each contain a PMOS transistor (17) which forms a current source, and that the logic gate (Fig. 1 to 3) each contain at least one NMOS transistor (131, 132 to 139), the control input of which is connected to the current source and the control input of which has at least one logic input signal (11) and the open output (121, 122 to 129) a logical output signal can be tapped.
3. MOS-Logik nach Anspruch 2, dadurch gekennzeichnet, daß ein Strom (18) der Stromquelle für die Logik-Gatter (Fig. 1 bis 3) einstellbar ist.3. MOS logic according to claim 2, characterized in that a current (18) of the current source for the logic gates (Fig. 1 to 3) is adjustable.
4. MOS-Logik nach Anspruch 2 und/oder 3. dadurch gekenn¬ zeichnet, daß der Ausgang (121, 122 bis 129) ein offe¬ ner Drain-Ausgang ist.4. MOS logic according to claim 2 and / or 3. characterized gekenn¬ characterized in that the output (121, 122 to 129) is an open drain outlet.
5. MOS-Logik nach einem oder mehreren der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die jeweiligen PMOS-Transistoren (17) der Logik-Gatter (Fig. 1 bis 3) gemeinsam von einem weiteren PMOS-Transistor mit einem Strom versorgt werden und daß dieser weitere PMOS-Tran¬ sistor als Stromspiegel geschaltet ist. Layout für eine MOS-Logik nach einem oder mehreren der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß Source-Anschlüsse von Logik-Gattern (Fig. 3) spiegelsym¬ metrisch angeordnet sind und jeweils durch ein gemeinsa¬ mes N+ Diffusionsgebiet verbunden sind (Fig. 2 und 3) und dieses N+ Diffusionsgebiet in einem Bereich, der außerhalb des jeweiligen Bereichs für die Ein- und Aus¬ gänge (21, 221, 222, 223, 229, 31, 321, 322, 323, 329, 37) der jeweiligen Logik-Gatter liegt, mit einem Me¬ tall-Anschluß jeweils an eine Masse-Leitung (26, 361, 362) angeschlossen ist. 5. MOS logic according to one or more of the preceding claims, characterized in that the respective PMOS transistors (17) of the logic gates (Fig. 1 to 3) are supplied with a current by a further PMOS transistor and that this further PMOS transistor is connected as a current mirror. Layout for a MOS logic according to one or more of the preceding claims, characterized in that source connections of logic gates (FIG. 3) are arranged in mirror symmetry and are each connected by a common N + diffusion region (FIG. 2 and 3) and this N + diffusion region in a region which is outside the respective region for the inputs and outputs (21, 221, 222, 223, 229, 31, 321, 322, 323, 329, 37) of the respective logic Gate is connected with a metal connection to a ground line (26, 361, 362).
PCT/EP1990/001747 1989-10-25 1990-10-16 Mos logic in bicmos circuits WO1991006981A1 (en)

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Publication number Priority date Publication date Assignee Title
FR2493076A1 (en) * 1980-10-24 1982-04-30 Majos Jacques Universal MOS logic gate - has source and drains on single implantation layer with output and inverter transistor grids forming unique zone
EP0110313A2 (en) * 1982-11-24 1984-06-13 Hitachi, Ltd. Semiconductor integrated circuit device and a method for manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2493076A1 (en) * 1980-10-24 1982-04-30 Majos Jacques Universal MOS logic gate - has source and drains on single implantation layer with output and inverter transistor grids forming unique zone
EP0110313A2 (en) * 1982-11-24 1984-06-13 Hitachi, Ltd. Semiconductor integrated circuit device and a method for manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE Journal of Solid-State Circuits, Band SC-22, Nr. 1, February 1987, IEEE, (New York, US), Chung-Yu Wu et al.: "The analysis and design of CMOS multidrain logic and stacked multidrain logic", Seiten 47-56 *

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