DE3935538A1 - MOS LOGIC IN BICMOS CIRCUITS - Google Patents

Abstract

In BICMOS circuits, the complementary MOS logic requires more transistor functions than does a I2L logic in bipolar circuits. By means of an improved MOS gate structure similar to that of I2L (CWL logic), the space requirements of the MOS logic are considerably reduced, while maintaining the noise-voltage sensitivity at the same level as in prior art CMOS logics. Because of the slower logic behaviour, the analog circuit structures are exposed to lower levels of noise radiation.

Description

The invention relates to integrated MOS logic BICMOS circuits.

For the manufacture of highly integrated circuits, e.g. B. TV signal processors, can be advantageous the BICMOS technology be used. One uses on such a chip e.g. B. for analog circuits bipolar components and for digital circuits CMOS logic.

BICMOS means: Bipolar and CMOS technology become common sam used on a chip. CMOS means: complementary Metal Oxide Silicon (Complementary Metal Oxide Semiconduc gate). I2L means: Integrated injection logic. Bipolar Technology, CMOS and I2L are e.g. B. described in "Working sheet No. 110 ", from the magazine" Elektronik ", issue 4/1978, pages 129-130 and issue 5/1978, pages 97-98.

A bipolar I2L gate consists of an npn transistor, that works as a switch and its injector with a pnp Transistor is operated as a current source. I2L gate required only a very small chip area, but the number of Outputs per gate is severely limited, e.g. B. to four. Except I2L logic is sensitive to voltage drops on ground and injector lines.  

Compared to I2L gates, CMOS gates have a higher level of interference sensitivity, but you need for a convention nelles CMOS gate more transistors than for a correspond of the I2L gate.

The invention has for its object a circuit for specify an integrated circuit in which the advantage le of the I2L circuit technology with those of the CMOS circuit circular technology are connected.

This object is achieved by the specified in claim 1 Features solved. Advantageous developments of the invention are described in the subclaims.

The solution is that MOS gates in an I2L-like structure. This can be done e.g. B. good in integrated circuits with BICMOS technology chen.

By using an I2L-like structure for MOS Gate in BICMOS, hereinafter referred to as CWL or CWL technology The following advantages result:

• - CWL logic enables chip area savings of approx. 50% compared to conventional CMOS logic.
• - CWL logic is circuit compatible with I2L logic.
• - CWL gates are insensitive to voltage fluctuations on ground and injector lines.
• - The slower logic behavior results in on analog circuit structures adjacent to the chip have a ge less interference.  
• - If z. B. many I2L gates can be controlled simultaneously you need an I2L control logic for the I2L Gate with a corresponding number of parallel outputs. Because of limiting the number of outputs, e.g. B. on four the control logic then corresponds to a tree structure the time delay caused by several in a row switched logic gates and a corresponding Platzbe may be on the chip. However, CWL gates can e.g. B. more than provide twenty outputs. Simplified accordingly such control logic. The number of parallel Exits is essentially only through this conditional capacitive load and the required speed limited.
• - The circuit design of CWL logic can be very simple symbolic layout can be used.

An embodiment of the invention will now be described hand of the drawings explained. These show in

Fig. 1 is a CWL-gate structure,

Fig. 2 layout of a CWL inverter with four outputs,

Fig. 3 Layout of four combined CWL inverters,

Fig. 4 wiring for a decoder logic according to Tab. 1.

In Fig. 1, the structure of a CWL gate with one input ( 11 ) and several outputs ( 121 , 122 , 129 ) is Darge. For example, there may be over twenty such parallel outputs. The associated output N-MOS transistors ( 131 , 132 , 139 ) are connected on the one hand with their respective sources together to the ground line ( 16 ) and on the other hand with their respective gate to the input ( 11 ). With their respective drain, they form a multi-drain output ( 121 , 122 , 129 ).

The signals of the outputs ( 121 , 122 , 129 ) are formed in the form of a multiple input NAND link by a plurality of signals, not shown, at the input ( 11 ) supplied from the outside, or in the form of an NOT link with one from the outside supplied signal at the input ( 11 ). An injection current ( 18 ) into the gates of the N-MOS transistors ( 131 , 132 , 139 ) is delivered from the drain of a P-MOS transistor ( 17 ), which has its source connected to the supply voltage ( 14 ) and its gate to a reference current ( 15 ) is ruled out. The reference current ( 15 ), hereinafter referred to as I-bias, defines the size of the injection current ( 18 ), approximately in the range from 0.1 to 10 µA. The reference current ( 15 ) can, for. B. also feed a wide ren PMOS transistor, which is connected as a current mirror and to the I-bias connections ( 15 , 25 , 351 , 352 ) is connected. This PMOS transistor has the same construction as the PMOS transistor ( 17 ) from FIG. 1. This automatically compensates for manufacturing-related tolerances of the gate-source voltages of such transistors ( 17 ).

A CWL logic gate is thus characterized by a current source ( 17 , 18 ) at the input ( 11 ) and multi-open drain outputs ( 121 , 122 , 129 ). The input ( 11 ) forms a 'CMOS-wired AND' logic with the signals supplied to it from the outside.

Fig. 2 shows the physical layout of a CWL gate with a gate structure according to FIG. 1, which is arranged between a Me tall connection for the supply voltage ( 24 ) and a Me tall connection ( 26 ) for ground. There are also the metal connection of the input ( 21 ) and four metal connections for the four outputs ( 221 , 222 , 223 , 229 ). You can also see the I-bias line ( 25 ) made of polycrystalline silicon.

The fields ( 271-279 ) each show a type of marking for the different areas of the CWL gate:
Marking 271 : buried layer,
Mark 272 : epitaxial area,
Mark 273 : active area,
Mark 274 : P + diffusion,
Mark 275 : N diffusion,
Label 276 : N + diffusion,
Mark 277 : polycrystalline silicon,
Mark 278 : contact between metal and polycrystalline silicon,
Marking 279 : metallization level.

Fig. 3 shows four adjacent CWL gates according to Fig. 2. It can be seen that the ground connections of two gates ( 361 , 362 ) and the I-bias connections of two gates ( 351 , 352 ) are connected.

The supply voltage connections ( 34 ) of all four gates are also combined. The four inputs corresponding to the input ( 31 ) each correspond to the input ( 21 ) of the gate from FIG. 2, the sixteen outputs corresponding to the four outputs ( 321 , 322 , 323 , 329 ) each correspond to the four outputs ( 221 , 222 , 223 , 229 ) of the gate from FIG. 2.

The wiring of the CWL gates can be shifted the gate connections on the chip surface advantageously combine fold.

Are example, if the gate of Fig. 2 and Fig. 3 discloses Benach arranged on one chip and the input (21) to be connected of the gate of Fig. 2 to the output (37) of the four-gate of Fig. 3, the input ( 21 ) of the gate from FIG. 2 is advantageously simply moved to the location of the output ( 229 ). As a result, the input ( 21 ) of the first gate is directly adjacent to the output ( 37 ) of the gate from FIG. 3 and a connection between the two is very short.

In Fig. 2 and Fig. 3 it can be seen that the source connections of each gate are mirror-symmetrically connected in an H-shaped N + diffusion structure and only this common source area of each gate or double gate through a metal connection to ground ( 26 , 361 , 362 ) is connected. In addition, there are only common supply voltage metal connections (at 34 ) for all four gates in Fig. 3rd These measures advantageously lead to a further reduction in the chip area required and offer greater freedom in the wiring of the gates to one another.

This allows even more complex logic functions, such as. B. a Binary-to-decimal decoder, advantageously with little wiring effort. In the following table (tab. 1) are the logical inputs (a, b, c, d) and output signals (A, B, C, D, E, F, G, H, I, J) of such a decoder ben:  

Table 1

Fig. 4 shows a section of the wiring diagram for this decoder. Eight logic gate inputs (a, b, c, d and a, b, c, d inverted) of eight logic gates ( 41 ) with corresponding metal contacts ( 43 ) are shown. Of these, four logic gate inputs (a, b, c, d) correspond to the logic input signals a, b, c, d in Table 1. Furthermore, five (42) out of ten connecting lines for logic gate outputs and represents five (F to J) out of ten decoder outputs, which correspond to the logical output signals (A to J) in Table 1.

On these connecting lines ( 42 ) are over the eight logic gate inputs (a, b, c, d and a, b, c, d inverted) further metal contacts from the outputs of the corresponding logic gates ( 41 ). One output of four (A to D) of the logic gate (41) (inverted a to d) to a corresponding input of the other four of the logic Gat ter (41).

The logical output signals (A to J) of the decoder are formed as follows (inv. means logically inverted).  

Claims (6)

1. MOS logic in integrated BICMOS circuits, characterized in that MOS logic gates ( Fig. 1 to 3) are constructed in an I2L-like structure ( Fig. 1). 2. MOS logic according to claim 1, characterized in that the logic gates ( Fig. 1 to 3) each contain a PMOS transistor ( 17 ) which forms a current source, and that the logic gate ( Fig. 1st to 3) each contain at least one NMOS transistor ( 131 , 132 to 139 ), whose control input is connected to the power source and at the control input of which there is at least one logic input signal (11) and to whose open output ( 121 , 122 to 129 ) a logical output signal can be tapped. 3. MOS logic according to claim 2, characterized in that a current ( 18 ) of the current source for the logic gates ( Fig. 1 to 3) is adjustable. 4. MOS logic according to claim 2 and / or 3, characterized in that the output ( 121 , 122 to 129 ) is an open drain output. 5. MOS logic according to one or more of the preceding claims, characterized in that the respective PMOS transistors ( 17 ) of the logic gates ( Fig. 1 to 3) are supplied with a current by a further PMOS transistor and that this further PMOS transistor is connected as a current mirror. 6. Layout for a MOS logic according to one or more of the preceding claims, characterized in that source connections of logic gates ( Fig. 3) are arranged mirror-symmetrically and are each connected by a common N + diffusion region ( Fig. 2 and 3) and this N + diffusion region in an area which is outside the respective area for the inputs and outputs ( 21 , 221 , 222 , 223 , 229 , 31 , 321 , 322 , 323 , 329 , 37 ) of the respective logic Gate is connected with a Me tall connection to a ground line ( 26 , 361 , 362 ).