WO1991003788A1 - Parallel i/o network file server architecture - Google Patents
Parallel i/o network file server architecture Download PDFInfo
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- WO1991003788A1 WO1991003788A1 PCT/US1990/004711 US9004711W WO9103788A1 WO 1991003788 A1 WO1991003788 A1 WO 1991003788A1 US 9004711 W US9004711 W US 9004711W WO 9103788 A1 WO9103788 A1 WO 9103788A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/10—File systems; File servers
- G06F16/18—File system types
- G06F16/1858—Parallel file systems, i.e. file systems supporting multiple processors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/133—Protocols for remote procedure calls [RPC]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/40—Network security protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/329—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the application layer [OSI layer 7]
Definitions
- Client requests for file operations are transmitted to one of the file controllers which, independently of the Unix host, manages the virtual file system of a mass storage device which is coupled to the storage processors.
- the file controllers may also control data buffering between the storage processors and the network controllers, through the system memory.
- the file controllers preferably each include a local buffer memory for caching file control information, separate from the system memory for caching file data.
- the network controllers, file processors and storage processors are all designed to avoid any instruction fetches from the system memory, instead keeping all instruction memory separate and local. This arrangement eliminates contention on the backplane between microprocessor instruction fetches and transmissions of message and file data.
- SUBSTITUTESHEET Fig. 2 is a block diagram of a file server architecture according to the invention.
- NFS network file system
- the NFS network file system
- the combination of host address, program number, and procedure number in an RPC request can specify one remote NFS procedure to be called.
- NFS assumes a file system that is hierarchical, with directories as all but the bottom level of files.
- Client hosts can call any of about 20 NFS procedures including such procedures as reading a specified number of bytes from a specified file; writing a specified number of bytes to a specified file; creating, renaming and removing specified files; parsing directory trees; creating and removing directories; and reading and setting file attributes.
- the location on disk to which and from which data is stored and retrieved is always specified in logical terms, such as by a file handle or Inode designation and a byte offset. The details of the actual data storage are hidden from the client.
- the Network Controllers 110 each run an NFS server which, after all protocol processing is done up to the NFS layer, converts between external NFS requests and responses and internal LNFS requests and responses.
- NFS requests arrive as RPC requests with
- the optimized dataflow of the server 100 begins with the intelligent network controller 110.
- This processor receives Ethernet packets from client workstations. It quickly identifies NFS-destined packets and then performs full protocol processing on them to the NFS level, passing the resulting LNFS requests directly to the file controller 112.
- This protocol processing includes IP routing and reassembly, UDP demultiplexing, XDR decoding, and NFS request dispatching. The reverse steps are used to send an NFS reply back to a client. Importantly, these time-consuming activities are performed directly in the Network Controller 110, not in the host 118'.
- Non-NFS network traffic is passed directly to its destination host processor 118.
- the server 100 In addition to dedicating a separate processor for NFS protocol processing and IP routing, the server 100 also dedicates a separate processor, the intelligent file controller 112, to be responsible for all file system processing. It uses conventional Berkeley Unix 4.3 file system code and uses a binary-compatible data representation on disk. These two choices allow all standard file system utilities (particularly block- level tools) to run unchanged.
- the resulting LNFS request passes to the FC 112.
- the FC 112 first searches the system memory 116 buffer cache for the requested data. If found, a reference to the buffer is returned to the NC 110. If not found, the LRU (least recently used) cache buffer in system memory 116 is freed and reassigned for the requested block.
- the FC then directs the SP 114 to read the block into the cache buffer from a disk drive array. When complete, the SP so notifies the FC, which in turn notifies the NC 100.
- the NC 110 then sends an NFS reply, with the data from the buffer, back to the NFS client workstation out on the network. Note that the SP 114 transfers the data into system memory 116, if necessary, and the NC 110 transferred the data from system memory 116 to the networks. The process takes place without any involvement of the host 118.
- the intelligent storage processor 114 manages all disk and tape storage operations. While autonomous, storage processors are primarily directed by the file controller 112 to move file data between system memory 116 and the disk subsystem. The exclusion of both the host 118 and the FC 112 from the actual data path helps to supply the performance needed to service many remote clients.
- TCP Transmission Control Protocol
- Socket are used to establish TCP connections.
- the device layer is a standard software interface between the Unix device model and different physical device implementations.
- disk devices are not attached to host processors directly, so the disk driver in the host's device layer uses the messaging kernel to communicate with the storage processor 114.
- Route and Port Mapper Demons are Unix user-level background processes that maintain the Route and Port databases for packet routing. They are mostly inactive and not in any performance path.
- Yellow Pages and Authentication Demon The Yellow Pages and Authentication services are Sun-ONC standard
- SUBSTITUTE SH network services Yellow Pages is a widely used multipurpose name-to-name directory lookup service.
- the Authentication service uses cryptographic keys to authenticate, or validate, requests to insure that requestors have the proper privileges for any actions or data they desire.
- Fig. 3 is a block diagram showing the data path and some control paths for an illustrative one of the network controllers 110a. It comprises a 20 MHz 68020 microprocessor 210 connected to a 32-bit microprocessor data bus 212. Also connected to the microprocessor data bus 212 is a 256K byte CPU memory 214. The low order 8 bits of the microprocessor data bus 212 are connected through a bidirectional buffer 216 to an 8-bit slow-speed data bus 218. On the slow- speed data bus 218 is a 128K byte EPROM 220, a 32 byte PROM 222, and a multi-function peripheral (MFP) 224.
- the EPROM 220 contains boot code for the network
- the second Ethernet 122b shown in Fig. 2 connects to a second LAN data bus 252 on the network controller card 110a shown in Fig. 3.
- the LAN data bus 252 connects to the low order 16 bits of the microprocessor data bus 212 via a bidirectional buffer 250, and has similar components to those appearing on
- a LAN controller 254 interfaces the LAN data bus 252 with the Ethernet 122b, using LAN memory 256 for data and control, and a LAN DMA controller 262 controls DMA transfer of data between the LAN memory 256 and the 16-bit wide data port A of the parity FIFO 260.
- the microprocessor 210 is responsible for loading and unloading Port A directly.
- the microprocessor 210 reads an entire 32-bit word from port A with a single instruction using two port A access cycles. Port A
- Command FIFO 290 is a conventional two-port FIFO, except that additional circuitry is included for generating a Bus Error signal on VME bus 120 if an attempt is made to write to the data input port while the FIFO is full.
- Command FIFO 290 has space for 256 entries.
- NC 110a A noteworthy feature of the architecture of NC 110a is that the LAN buses 232 and 252 are independent of the microprocessor data bus 212. Data packets being routed to or from an Ethernet are stored in LAN memory 236 on the LAN data bus 232 (or 256 on the LAN data
- the CPU memory 214 contains mostly instructions for microprocessor 210, messages being transmitted to or from a remote board via FIFO 270, and various data blocks for controlling the FIFOs, the DMA controllers and the LAN controllers.
- the microprocessor 210 accesses the data packets in the LAN memories 236 and 256 by directly addressing them through the bidirectional buffers 230 and 250, respectively, for protocol processing.
- the local high-speed static RAM in CPU memory 214 can therefore provide zero wait state memory access for microprocessor 210 independent of network traffic. This is in sharp contrast to the prior art architecture shown in Fig. 1, in which all data and data packets, as well as microprocessor instructions for host CPU card 10, reside in the memory 16 and must communicate with the host CPU card 10 via the MMU 11.
- LAN data buses 232 and 252 are shown as separate buses in Fig. 3, it will be understood that they may instead be implemented as a single combined bus.
- the microprocessor 210 assembles a response packet in LAN memory 236 and, in a conventional manner, causes LAN controller 234 to transmit that packet back over Ethernet 122a. It is noteworthy that the data manipulation for
- SUBSTITUTE SHEET accomplishing this task is performed almost completely in LAN memory 236, directly addressed by microprocessor 210 as controlled by instructions in CPU memory 214. The function is accomplished also without generating any traffic on the VME backplane 120 at all, and without disturbing the local host 118.
- the microprocessor 210 first programs the LAN DMA controller 242 with the starting address and length of the packet in LAN memory 236, and programs the controller to begin transferring data from the LAN memory 236 to port A of parity FIFO 240 as soon as the FIFO is ready to receive data. Second, microprocessor 210 programs the VME/FIFO DMA controller 272 with the destination address in system memory 116 and the length of the data packet, and instructs the controller to begin transferring data from port B of the FIFO 260 onto VME bus 120. Finally, the microprocessor 210 programs FIFO 240 with the direction of the transfer to take place. The transfer then proceeds entirely under the control of DMA controllers 242 and 272, without any further involvement by microprocessor 210.
- SUBSTITUTESHEET message by writing a message descriptor to a software- emulated command FIFO on the host, which copies the message from CPU memory 214 on the NC via buffer 284 and into the host's local memory, in ordinary VME block transfer mode. The host then copies the packet from system memory 116 into the host's own local memory using ordinary VME transfers.
- the microprocessor 210 determines whether it is (1) an IP packet for the server 100 which is not an NFS packet; (2) an IP packet to be routed to a different network; or (3) an NFS packet. If it is an IP packet for the server 100, but not an NFS packet, then the microprocessor 210 causes the packet to be transmitted from the LAN memory 236 to the host 118 in the same manner described above with respect to certain ARP packets.
- the packet is copied into the LAN memory associated with the Ethernet to which the destination client is connected. If the destination client is on the Ethernet 122b, which is on the same NC board as the source Ethernet 122a, then the microprocessor 210 causes the packet to be copied from LAN memory 236 into LAN 256 and then causes LAN controller 254 to transmit it over Ethernet 122b. (Of course, if the two LAN data buses 232 and 252 are combined, then copying would be unnecessary; the microprocessor 210 would simply cause the LAN controller 254 to read the packet out of the same locations in LAN memory to which the packet was written by LAN controller 234.)
- the microprocessor 210 first programs the LAN DMA controller 242 with the starting address and length of the packet in LAN memory 236, and programs the controller to begin transferring data from the LAN memory 236 into port A of parity FIFO 240 as soon as the FIFO is ready to receive data. Second, microprocessor 210 programs the LAN DMA controller 262 with a destination address in LAN memory 256 and the length of the data packet, and instructs that controller to transfer data from parity FIFO 260 into the LAN memory 256.
- each of the LAN DMA controllers 242 and 262 When each of the LAN DMA controllers 242 and 262 complete their work, they so notify microprocessor 210 by a respective interrupt provided through MFP 224. When the microprocessor 210 has received both interrupts, it programs LAN controller 254 to transmit the packet on the Ethernet 122b in a conventional manner.
- IP routing between the two Ethernets in a single network controller 110 takes place over data bus 274, generating no traffic over VME bus 120.
- host processor 118 disturbed for such routing, in contrast to the prior art architecture of Fig. 1.
- all but the shortest copying work is
- SUBSTITUTE SHEET performed by controllers outside microprocessor 210, requiring the involvement of the microprocessor 210, and bus traffic on microprocessor data bus 212, only for the supervisory functions of programming the DMA controllers and the parity FIFOs and instructing them to begin.
- the VME/FIFO DMA controller 272 is programmed by loading control registers via microprocessor data bus 212; the LAN DMA controllers 242 and 262 are programmed by loading control registers on the respective controllers via the microprocessor data bus 212, respective bidirectional buffers 230 and 250, and respective LAN data buses 232 and 252, and the parity FIFOs 240 and 260 are programmed as set forth in the Appendix.
- the microprocessor 210 performs all necessary protocol preprocessing to extract the NFS message and convert it to the local NFS (LNFS) format. This may well involve the logical concatenation of data extracted from a large number of
- the directory maintenance commands which are supported by LNFS include the following messages based on conventional NFS: get attributes of a file (GETATTR) ; set attributes of a file (SETATTR) ; look up a file (LOOKUP); created a file (CREATE); remove a file (REMOVE); rename a file (RENAME); created a new linked file (LINK); create a symlink (SYMLINK); remove a directory (RMDIR); and return file system statistics (STATFS) .
- the data transfer commands supported by LNFS include read from a file (READ); write to a file (WRITE) ; read from a directory (READDIR) ; and read a link (READLINK) .
- the microprocessor 210 accommodates that situation by programming LAN DMA controller 242 successively for each portion of the data, in accordance with the linked list, after receiving notification that the previous portion is complete.
- the microprocessor 210 can program the parity FIFO 240 and the VME/FIFO DMA controller 272 once for the entire message, as long as the entire data block is to be placed contiguously in system memory 116. If it is not, then the microprocessor 210 can program the DMA controller 272 for successive blocks in the same manner LAN DMA controller 242.
- microprocessor 210 When each of the DMA controllers 242 and 272 complete their work, they so notify microprocessor 210 through MFP 224. The microprocessor 210 then performs all necessary protocol processing on the LNFS message in LAN memory 236 in order to prepare the message for transmission over the Ethernet 122a in the form of Ethernet IP packets. As set forth above, this protocol processing is performed entirely in network controller 110a, without any involvement of the local host 118.
- the microprocessor 210 For transfers from port A to port B of the parity FIFO 270, the microprocessor 210 loads port A word- by-word and forces a FIFO full indication when it is finished. The FIFO full indication enables unloading from port B. The same procedure also takes place for transfers from port A to port B of either of the parity FIFOs 240 or 260, since transfers of fewer than 128 bytes are performed under local microprocessor control rather than under the control of LAN DMA controller 242 or 262. For all of the FIFOs, the VME/FIFO DMA controller is programmed to unload only the desired number of 32-bit words.
- FC 112a comprises a 20MHz 68020 microprocessor 310 connected to a 32-bit microprocessor data bus 312. Also connected to the microprocessor data bus 312 is a 256K byte shared CPU memory 314. The low order 8 bits of the microprocessor data bus 312 are connected through a bidirectional buffer 316 to an 8-bit slow-speed data bus 318. On slow-speed data bus 318 are a 128K byte PROM 320, and a multifunction peripheral (MFP) 324. The functions of the PROM 320 and MFP 324 are the same as those described above with respect to EPROM 220 and
- FC 112a does not include PROM like the PROM 222 on NC 110a, but does include a parallel port 392.
- the parallel port 392 is mainly for testing and diagnostics.
- the FC 112a is connected to the VME bus 120 via a bidirectional buffer 380 and a 32- bit local data bus 376.
- a set of control registers 382 are connected to the local data bus 376, and directly addressable across the VME bus 120.
- the local data bus 376 is also coupled to the microprocessor data bus 312 via a bidirectional buffer 384. This permits the direct addressability of CPU memory 314 from VME bus 120.
- SUBSTITUTE SHEET addresses the CPU memory 314 or the FC memory 396 directly over the VME bus 120 through the bidirectional buffers 384 and, if appropriate, 394.
- the file related commands supported by LNFS are identified above. They are all specified to the FC 112a in terms of logically identified disk data blocks.
- the LNFS command for reading data from a file includes a specification of the file from which to read (file system ID (FSID) and file ID (inode)), a byte offset, and a count of the number of bytes to read.
- the FC 112a converts that identification into physical form, namely disk and sector numbers, in order to satisfy the command.
- the FC 112a runs a conventional Fast File System (FFS or UFS), which is based on the Berkeley 4.3 VAX release. This code performs the conversion and also performs all disk data caching and control data caching. However, as previously mentioned, control data caching is performed using the FC memory 396 on FC 112a, whereas disk data caching is performed using the system memory 116 (Fig. 2). Caching this file control information within the FC 112a avoids the VME bus congestion and speed degradation which would result if file control information was cached in system memory 116.
- the memory on the FC 112a is directly accessed over the VME bus 120 for three main purposes. First, and by far the most frequent, are accesses to FC memory 396 by an SP 114 to read or
- SUBSTITUTE SHE write cached file control information These are accesses requested by FC 112a to write locally modified file control structures through to disk, or to read file control structures from disk.
- the FC's CPU memory 314 is accessed directly by other processors for message transmissions from the FC 112a to such other processors. For example, if a data block in system memory is to be transferred to an SP 114 for writing to disk, the FC 112a first assembles a message in its local memory 314 requesting such a transfer. The FC 112a then notifies the SP 114, which copies the message directly from the CPU memory 314 and executes the requested transfer.
- FC 112a A third type of direct access to the FC's local memory occurs when an LNFS client reads directory entries.
- FC 112a When FC 112a receives an LNFS request to read directory entries, the FC 112a formats the requested directory entries in FC memory 396 and notifies the requestor of their location. The requestor then directly accesses FC memory 396 to read the entries.
- the version of the UFS code on FC 112a includes some modifications in order to separate the two caches.
- two sets of buffer headers are maintained, one for the FC memory 396 and one for the system memory 116.
- a second set of the system buffer routines (GETBLKO, BRELSEO, BREAD(), BWRITEO, and BREADAO) exist, one for buffer accesses to FC Mem 396 and one for buffer accesses to system memory 116.
- the UFS code is further modified to call the appropriate buffer routines for FC memory 396 for accesses to file control information, and to call the appropriate buffer routines for the system memory 116 for the caching of disk data.
- a description of UFS may be found in chapters 2, 6, 7 and 8 of "Kernel Structure and Flow, " by Rieken and Webb of . ⁇ h
- the FC When a read command is sent to the FC by a requestor such as a network controller, the FC first converts the file, offset and count information into disk and sector information. It then locks the system memory buffers which contain that information, instructing the storage processor 114 to read them from disk if necessary. When the buffer is ready, the FC returns a message to the requestor containing both the attributes of the designated file and an array of buffer descriptors that identify the locations in system memory 116 holding the data.
- a requestor such as a network controller
- FC 112a uses the information contained therein to determine which buffers to free.
- a write command is processed by FC 112a similarly to the read command, but the caller is expected to write to (instead of read from) the locations in system memory 116 identified by the buffer descriptors returned by the FC 112a. Since FC 112a employs write- through caching, when it receive ⁇ the relea ⁇ e command from the requestor, it instruct ⁇ storage processor 114 to copy the data from system memory 116 onto the appropriate disk sectors before freeing the system memory buffers for possible reallocation.
- the READDIR transaction is similar to read and write, but the request is satisfied by the FC 112a directly out of its own FC memory 396 after formatting the requested directory information specifically for this purpose.
- the FC 112a causes the storage processor read the requested directory information from disk if it is not already locally cached. Also,
- SUB S TITUTESHEET the specified offset is a "magic cookie" instead of a byte offset, identifying directory entries instead of an absolute byte offset into the file. No file attributes are returned.
- the READLINK transaction also returns no file attributes, and since links are always read in their entirety, it does not require any offset or count.
- the FC 112a acts as a central authority for dynamically allocating, deallocating and keeping track of buffers. If there are two or more FCs 112, each has exclusive control over its own assigned portion of system memory 116. In all of these transactions, the requested buffers are locked during the period between the initial request and the release request. This prevents corruption of the data by other clients.
- FC_V CE_PRESIDENT which maintains a list of which file systems are assigned to which FC.
- a client processor for example an NC 110
- FC_VTCE_PRESIDENT responds, and the • client processor sends the LNFS request to the designated FC.
- the client processor also maintains its own list of fsid/FC pairs as it discovers them, so as to minimize the number of such requests to the FC_VICE_PRESIDENT.
- each of the storage processors 114 can interface the VME bus 120 with up
- SUBSTITUTESHEET to 10 different SCSI buses. Additionally, it can do so at the full usage rate of an enhanced block transfer protocol of 55MB per second.
- Fig. 5 is a block diagram of one of the SPs 114a.
- SP 114b is identical.
- SP 114a comprises a microprocessor 510, which may be a Motorola 68020 microprocessor operating at 20MHz.
- the microprocessor 510 is coupled over a 32-bit microprocessor data bus 512 with CPU memory 514, which may include up to 1MB of static RAM.
- the microprocessor 510 accesses instructions, data and status on its own private bus 512, with no contention from any other source.
- the microprocessor 510 is the only master of bus 512.
- the low order 16 bits of the microprocessor data bus 512 interface with a control bus 516 via a bidirectional buffer 518.
- the low order 8 bits of the control bus 516 interface with a slow speed bus 520 via another bidirectional buffer 522.
- the slow speed bus 520 connects to an MFP 524, similar to the MFP 224 in NC 110a (Fig. 3), and with a PROM 526, similar to PROM 220 on NC 110a.
- the PROM 526 comprise ⁇ 128K bytes of EPROM which contains the functional code for SP 114a. Due to the width and speed of the EPROM 526, the functional code is copied to CPU memory 514 upon reset for faster execution.
- MFP 524 Additional information on the MFP 524 can be found in "MC 68901 Multi-Function Peripheral Specification," by Motorola, Inc., which is incorporated herein by reference.
- the eight general-purpose I/O bits provided by MFP 524 are configured according to the following table:
- VMEbus Interrupt Done Indicates the completion of a VMEbus Interrupt.
- Commands are provided to the SP 114a from the VME bus 120 via a bidirectional buffer 530, a local data bus 532, and a command FIFO 534.
- the command FIFO 534 is similar to the command FIFOs 290 and 390 on NC 110a and FC 112a, respectively, and has a depth of 256 32- bit entries.
- the command FIFO 534 is a write-only register as seen on the VME bus 120, and as a read ⁇ only register as seen by microprocessor 510. If the
- SUBSTITUTE SHEET FIFO is full at the beginning of a write from the VME bus, a VME bus error is generated. Pointers are removed from the command FIFO 534 in the order received, and only by the microprocessor 510. Command avai .able status is provided through I/O bit 4 of the MFP 524, and as a long as one or more command pointers are still within the command FIFO 534, the command available status remains asserted.
- the microprocessor 510 communicates with the control registers on the SCSI adaptors 542 via the control bu ⁇ 516 and an additional bidirectional buffer 546, and communicates with the control registers on FIFOs 544 via the control bus 516 and a bidirectional buffer 552.
- Both the SCSI adaptors 542 and FIFOs 544 employ 8-bit control registers, and register addressing of the FIFOs 544 is arranged such that such registers alias in consecutive byte locations. This allows the microprocessor 510 to write to the registers as a single 32-bit register, thereby reducing instruction overhead.
- the parity FIFOs 544 are each configured in their Adaptec 6250 mode. Referring to the Appendix, the
- bit 4 of the RAM Access Control Register (Long Burst) is programmed for 8-byte bursts.
- SCSI adaptors 542 each generate a respective interrupt signal, the status of which are provided to microprocessor 510 as 10 bits of a 16-bit SCSI interrupt register 556.
- the SCSI interrupt register 556 is connected to the control bus 516.
- a composite SCSI inte-rupt is provided through the MFP 524 whenever any one of the SCSI adaptors 542 needs servicing.
- An additional parity FIFO 554 is also provided in the SP 114a, for message passing. Again referring to the Appendix, the parity FIFO 554 is programmed with
- the Data Transfer Control Register is programmed as follows:
- bit 4 of the RAM Access Control Register (Long Burst) is programmed for 8-byte bursts.
- Port A of FIFO 554 is connected to the 16-bit control bus 516, and port B is connected to the common data bus 550.
- FIFO 554 provides one means by which the microproces ⁇ or 510 can communicate directly with the VME bus 120, as i ⁇ de ⁇ cribed in more detail below.
- the microproce ⁇ or 510 manage ⁇ data movement using a set of 15 channels, each of which has an unique status which indicates its current state. Channels are implemented using a channel enable register 560 and a channel status register 562, both connected to the control bus 516.
- the channel enable register 560 is implemented using a channel enable register 560 and a channel status register 562, both connected to the control bus 516.
- SUBSTITUTE SHEET is a 16-bit write-only register, whereas the channel status register 562 is a 16-bit read-only register.
- the two registers reside at the same addres ⁇ to microprocessor 510.
- the microproces ⁇ or 510 enables a particular channel by setting its respective bit in channel enable register 560, and recognizes completion of the specified operation by testing for a "done" bit in the channel status register 562.
- the microprocessor 510 then resets the enable bit, which cause ⁇ the re ⁇ pective "done” bit in the channel status register 562 to be cleared.
- the channels are defined as follows: CHANNEL FUNCTION 0:9 These channels control data movement to and from the respective FIFOs 544 via the comir. n data bus 550. When a FIFO i ⁇ enabled and a reque ⁇ t i ⁇ received from it, the channel becomes ready. Once the channel has been serviced a statu ⁇ of done is generated.
- this channel When enabled, this channel cause ⁇ the DRAM in local data buffer 564 to be refre ⁇ hed ba ⁇ ed on a clock which i ⁇ generated by the MFP 524.
- the refre ⁇ h consists of a burst of 16 rows. This channel does not generate a status of done.
- the microprocessor's communication FIFO 554 is serviced by this channel.
- enable is set and the FIFO 554 as ⁇ ert ⁇ a reque ⁇ t then the channel become ⁇ ready. This channel generates a status of done.
- U BS ⁇ LUTE TM 15 This is a null channel for which neither a ready ⁇ tatus nor done statu ⁇ i ⁇ generated.
- Channel ⁇ are prioritized to allow ⁇ ervicing of the more critical requests first.
- Channel priority is a ⁇ igned in a de ⁇ cending order ⁇ tarting at channel 14.
- channel 14 will be the first one served.
- the common data bus 550 is coupled via a bidirectional register 570 to a 36-bit junction bus 572.
- a second bidirectional register 574 connects the junction bus 572 with the local data bus 532.
- Local data buffer 564 which comprises 1MB of DRAM, with parity, is coupled bidirectionally to the junction bus 572. It is organized to provide 256K 32-bit words with byte parity.
- the SP 114a operates the DRAMs in page mode to support a very high data rate, which requires bur ⁇ ting of data in ⁇ tead of random single- word accesses.
- the local data buffer 564 is u ⁇ ed to implement a RAID (redundant array of inexpen ⁇ ive di ⁇ k ⁇ ) algorithm, and i ⁇ not u ⁇ ed for direct reading and writing between the VME bus 120 and a peripheral on one of the SCSI buses 540.
- RAID redundant array of inexpen ⁇ ive di ⁇ k ⁇
- a read-only register 576 containing all zeros, is also connected to the junction bus 572.
- Thi ⁇ register is used mostly for diagnostic ⁇ , initialization, and clearing of large block ⁇ of data in ⁇ y ⁇ tem memory 116.
- the microprocessor 510 places command parameters in the dual-port RAM 584, and uses the channel enables 560 to signal the VME/FIFO DMA controller 580 to proceed with the command.
- the VME/FIFO DMA controller is responsible for scanning the channel statu ⁇ and ⁇ ervicing reque ⁇ ts, and returning ending status in the dual-port RAM 584.
- the dual-port RAM 584 is organized as IK x 32 bits at the 32-bit port and as 2K x 16 bits at the 16-bit port.
- a example showing the method by which the microprocessor 510 controls the VME/FIFO DMA controller 580 is as follows.
- the microprocessor 510 writes into the dual-port RAM 584 the desired command and associated parameters for the desired channel.
- the command might be, "copy a block of data from FIFO 544h out into a block of sy ⁇ tem memory 116 beginning at a ⁇ pecified VME addre ⁇ .”
- the icropro ⁇ e ⁇ or sets the channel enable bit in channel enable register 560 for the desired channel.
- the appropriate FIFO may not yet be ready to send data. Only when the VME/FIFO DMA controller 580 does receive a "ready" status from the channel, will the controller 580 execute the command. In the meantime, the DMA controller 580 is free to execute commands and move data to or from other channels.
- the DMA controller 580 When the DMA controller 580 does receive a statu ⁇ of "ready” from the ⁇ pecified channel, the controller fetches the channel command and parameters from the dual-ported RAM 584 and executes. When the command is complete, for example all the requested data has been copied, the DMA controller writes statu ⁇ back into the dual-port RAM 584 and a ⁇ erts "done" for the channel in channel status register 562.
- SUBSTITUTE SHEET 510 is then interrupted, at which time it reads channel status register 562 to determine which channel interrupted.
- the microproces ⁇ or 510 then clear ⁇ the channel enable for the appropriate channel and checks the ending channel status in the dual-port RAM 584.
- the SP 114a also includes a high-speed register 590, which is coupled between the microproces ⁇ or data bu ⁇ 512 and the local data bu ⁇ 532.
- the high- ⁇ peed register 590 is used to write a single 32-bit word to an VME bu ⁇ target with a minimum of overhead.
- the register is write only as viewed from the microproces ⁇ or 510.
- the microproce ⁇ or 510 In order to write a word onto the VME bu ⁇ 120, the microproce ⁇ or 510 first writes the word into the register 590, and the desired VME target addres ⁇ into dual-port RAM 584.
- the DMA controller 580 transfers the data from the register 590 into the VME bus address specified in the dual-port RAM 584.
- the DMA controller 580 then writes the ending statu ⁇ to the dual-port RAM and sets the channel "done" bit in channel statu ⁇ register 562.
- This procedure is very efficient for transfer of a single word of data, but becomes inefficient for large blocks of data. Transfer ⁇ of greater than one word of data, typically for me ⁇ age passing, are usually performed using the FIFO 554.
- the SP 114a also includes a series of registers 592, similar to the register ⁇ 282 on NC 110a (Fig. 3)
- the 30 SCSI disk drive ⁇ supported by each of the SPs 114 are vi ⁇ ible to a client processor, for example one of the file controllers 112, either as three large, logical disks or as 30 independent SCSI drives, depending on configuration.
- the SP uses RAID 5 design algorithms to distribute data for each logical drive on nine physical drives to minimize disk arm contention. The tenth drive is left as a spare.
- the RAID 5 algorithm (redundant array of inexpensive drive ⁇ , revision 5) is described in "A Case For a Redundant Arrays of Inexpensive Disks (RAID)", by Patterson et al., published at ACM SIGMOD Conference, Chicago, 111., June 1-3, 1988, incorporated herein by reference.
- disk data are divided into stripes. Data stripes are recorded sequentially on eight different disk drives.
- a ninth parity stripe the exclusive-or of eight data ⁇ tripes, is recorded on a ninth drive. If a stripe size is set to 8K bytes, a read of 8K of data involves only one drive.
- a write of 8K of data involves two drives: a data drive and a parity drive. Since a write requires the reading back of old data to generate a new parity stripe, write ⁇ are al ⁇ o referred to as modify writes.
- the SP 114a support ⁇ nine ⁇ mall reads to nine SCSI drives concurrently. When stripe size is set to 8K, a read of 64K of data starts all eight SCSI drives, with each drive reading one 8K stripe worth of data.
- the parallel operation is transparent to the caller client.
- SUBSTITUTESHEET The parity stripes are rotated among the nine drives in order to avoid drive contention during write operations.
- the SP 114a can reconstruct the missing data from a parity stripe. In such case, the SP 114a is running in error recovery mode.
- the SP 114a can be instructed to restore data on the repaired drive while the system is on-line.
- the SP 114a proces ⁇ es multiple mes ⁇ age ⁇
- SP 114a (transactions, commands) at one time, up to 200 mes ⁇ age ⁇ per ⁇ econd.
- the SP 114a doe ⁇ not initiate any me ⁇ age ⁇ after initial ⁇ y ⁇ te configuration.
- the following SP 114a operations are defined:
- This command is ⁇ ued usually by an FC 112, cause ⁇ the SP 114a to transfer data between a specified block of system memory and a specified series of contiguous sectors on the SCSI disks.
- the particular sector ⁇ are identified in phy ⁇ ical term ⁇ .
- the particular disk sectors are identified by SCSI channel number (0-9), SCSI ID on that channel number (0-2), starting sector address on the specified drive, and a count of the number of sectors to read or write.
- the SCSI channel number is zero if the SP 114a is operating under RAID 5.
- the SP 114a can execute up to 30 messages on the 30 SCSI drives si ultaneou ⁇ ly. Unlike mo ⁇ t of the command ⁇ to an SP 114, which are processed by microprocessor 510 as soon as they appear on the command FIFO 534, read and write sectors commands (as well as read and write cache memory commands) are first sorted and queued. Hence, they are not served in the order of arrival.
- the microprocessor 510 determines which di ⁇ k drive is targeted and insert ⁇ the mes ⁇ age in a queue for that disk drive sorted by the target sector address.
- the microprocessor 510 executes commands on all the queues simultaneously, in the order present in the queue for each disk drive. In order to minimize disk arm movements, the microproces ⁇ or 510 move ⁇ back and forth among queue entrie ⁇ in an elevator fashion.
- Read/Write Cache Paces This command i ⁇ ⁇ imilar to read and write ⁇ ectors, except that multiple VME addresses are provided for transferring disk data to and from system memory 116. Each VME addres ⁇ point ⁇ to a cache page in ⁇ ystem memory 116, the size of which is also specified in the command.
- ⁇ ystem memory 116 When transferring data from a disk to system memory 116, data are scattered to different cache pages; when writing data to a disk, data are gathered from different cache pages in ⁇ y ⁇ tem memory 116. Hence, this operation is referred to as a scatter- gather function.
- the target ⁇ ector ⁇ on the SCSI di ⁇ k ⁇ are specified in the command in physical terms, in the same manner that they are specified for the read and write sectors command. Termination of the command with or without error conditions is the same as for the read and write sectors command.
- the dual-port RAM 584 in the DMA controller 580 maintains a ⁇ eparate ⁇ et of command ⁇ for each channel controlled by the bit slice engine 582. As each channel completes its previous operation, the microproces ⁇ or 510 writes a new DMA operation into the dual-port RAM 584 for that channel in order to sati ⁇ fy the next operation on a disk elevator queue.
- the commands written to the DMA controller 580 include an operation code and a code indicating whether the operation is to be performed in non-block mode, in standard VME block mode, or in enhanced block mode.
- the operation codes supported by DMA controller 580 are as follows:
- ZEROES -> FIFO Move zeros f ;eros register 57. o the currently selected FIFO on common data bus 550.
- ZEROES -> VMEbus Move zeros from zeros register 576 out onto the VME bus 120. Used for initializing cache buffers in system memory 116.
- VMEbus -> BUFFER Move data from the VME bus 120 to the local data buffer 564. This operation i ⁇ used during a write, to move target data intended for a down drive into the b u f f e r f o r participation in r e d u n d a n c y generation. Used only for RAID 5 application.
- VMEbus -> FIFO New data to be written from VME bus onto a drive Since RAID 5 requires redundancy data to be generated from data that is buffered in local data buffer 564, this operation will be used only if the SP 114a is not configured for RAID 5.
- Target data is moved from VME bus 120 to a SCSI
- SUBSTITUTE SHEET dev ' ice is also captured in the local data buffer 564 for participation in redundancy generation.
- SUBSTITUTE SHEET LFD 25 (Latched Flag Data) When set this bit causes the selected latched flag to be set. When reset this bit causes the selected latched flag to be cleared. This bits also functions as literal bit 3 for the alu bus.
- 1 SGL_CLK generates a single transition of buffer clock.
- 2 SET_VB forces vme and buffer enable to be set.
- DEST ⁇ 3:0> 16:13 DESTination select bits 3:0 These bits select one of 10 destinations to be loaded from the alu bus.
- NEXT_A ⁇ 8:0> 8:0 Selects an instruction ⁇ from the current page of the control ⁇ tore for execution.
- Dual Ported Ram The dual ported ram is the medium by which command, parameters and statu ⁇ are communicated between the DMA controller 580 and the microproce ⁇ or 510.
- the ram i ⁇ organized a ⁇ IK x 32 at the ma ⁇ ter port and as 2K x 16 at the DMA port. The ram may be both written and read at either port.
- SUBSTITUTE SHET Writing the ram is accomplished by loading data from the proces ⁇ or into the registers after loading the ram address. Succes ⁇ ive writes may be performed on every other proces ⁇ or cycle.
- the ram contains current block pointers, ending status, high speed bus address and parameter blocks.
- the Initial Pointer is a 32 bit value which points the fir ⁇ t command block of a chain.
- the current command block pointer ⁇ hould be initialized to 0x0000 by the microproce ⁇ sor 510 before enabling the channel. Upon detecting a value of 0x0000
- the DMA controller 580 will copy the lower 16 bits from the initial pointer to the current pointer. Once the DMA controller 580 has completed the specified operations for the parameter block the current pointer will be updated to point to the next block. In the event that no further parameter blocks are available the pointer will be set to 0x0000.
- statu ⁇ byte indicate ⁇ the ending ⁇ tatu ⁇ for the la ⁇ t channel operation performed.
- the following status bytes are defined: STATUS MEANING
- the format of the parameter block is: OFFSET 31 0
- SUBSTITUTE SHET A31:A2,0,0 The format dictate ⁇ that the parameter block mu ⁇ t start on a quad byte boundary.
- a pointer of 0x00000000 is a special case which indicates no forward link exists.
- WORD COUNT The word count specifies the number of quad byte words that are to be transferred to or from each buffer address or to/from the VME address.
- a word count of 64K words may be specified by initializing the word count with the value of 0.
- the word count has the following format:
- Word count i ⁇ updated by the DMA controller 580 at the completion of a transfer to/from the last specified buffer address. Word count is not updated after transferring to/from each buffer address and is therefore not an accurate indicator of the total data moved to/from the buffer. Word count represents the amount of data transferred to the VME bus or one of the FIFOs 544 or 554.
- VME ADDRESS - The VME address ⁇ pecifie ⁇ the starting addres ⁇ for data tran ⁇ fer ⁇ . Thirty bit ⁇ allow ⁇ the address to start at any quad byte boundary.
- ENH - This bit when set selects the enhanced block transfer protocol described in the above-cited ENHANCED VMEBUS PROTOCOL UTILIZING PSEUDOSYNCHRONOUS HANDSHAKING AND BLOCK MODE DATA TRANSFER application, to be used during the VME bus transfer.
- Enhanced protocol will be disabled automatically when performing any transfer to or from 24 bit or 16 bit address space, when the starting address is not 8 byte aligned or when the word count is not even.
- the buffer addres ⁇ ⁇ pecifie ⁇ the starting buffer address for the adjacent operation. Only 16 bits are available for a 1M byte buffer and as a result the starting address always falls on a 16 byte boundary. The programmer must ensure that the starting address is on a modulo 128 byte boundary.
- the buffer addres ⁇ i ⁇ updated by the DMA controller 580 after completion of each data burst.
- the DMA controller 580 continues to fetch buffer addresses and operations to perform until this bit is encountered. Once the last operation within the parameter block is executed the word counter is updated and if not equal to zero the series of operations is repeated. Once the word counter reaches zero the forward link pointer is used to access the next parameter block.
- the op code byte has the following format: !0
- FIFO refers to any of the FIFOs 544 or 554.
- the enhanced VME block transfer protocol is a
- VMEbus compatible pseudo-synchronous fast transfer handshake protocol for use on a VME backplane bus having a master functional module and a slave functional module logically interconnected by a data transfer bus.
- the data transfer bus includes a data strobe signal line and a data transfer acknowledge signal line.
- the master transmit ⁇ a data ⁇ trobe ⁇ ignal of a given duration on the data strobe line.
- the master then awaits the reception of a data transfer acknowledge signal from the slave module on the data transfer acknowledge signal line.
- the slave then responds by transmitting data transfer acknowledge signal of a given duration on the data transfer acknowledge signal line.
- the data to be transferred is referenced to only one signal depending upon whether the transfer operation is a READ or WRITE operation.
- the master In transferring data from the master functional unit to the slave, the master broadcasts the data to be transferred.
- the master asserts a data strobe signal and the slave, in respon ⁇ e to the data ⁇ trobe ⁇ ignal, capture ⁇ the data broadcast by the master.
- the slave In transferring data from the slave to the master, the slave broadcast ⁇ the data to be transferred to the master unit.
- the slave then asserts a data transfer acknowledge signal and the master, in respon ⁇ e to the data tran ⁇ fer acknowledge ⁇ ignal, capture ⁇ the data broadcast by the slave.
- the fast transfer mode reduces the number of bus propagations required to accomplish a handshake from four propagations, as required under conventional VMEbus protocols, to only two bus propagations. Likewise, the number of bus propagations required to effect a BLOCK READ or BLOCK WRITE data transfer i ⁇ reduced. Consequently, by reducing the propagations acros ⁇ the VMEbus to accomplish handshaking and data transfer function ⁇ , the tran ⁇ fer rate i ⁇ materially increased.
- the master then waits for an acknowledgement from the slave. Subsequent pulsing of DSO* cannot occur until a respon ⁇ ive DTACK* signal is received from the slave.
- the master Upon receiving the slave' ⁇ a ⁇ sertion of DTACK*, the master can then immediately reas ⁇ ert data ⁇ trobe, if ⁇ o de ⁇ ired.
- the fa ⁇ t tran ⁇ fer mode protocol does not require the master to wait for the deassertion of DTACK* by the slave as a condition precedent to subsequent as ⁇ ertions of DSO*.
- the fast transfer mode protocol may be characterized as pseudo-synchronous as it includes both synchronous and asynchronou ⁇ a ⁇ pect ⁇ .
- the fa ⁇ t transfer mode protocol is synchronou ⁇ in character due to the fact that DSO* is asserted and deasserted without regard to a response from the slave.
- the asynchronous aspect of the fa ⁇ t transfer mode protocol is attributable to the fact that the master may not subsequently assert DSO* until a response to the prior strobe is received from the slave. Consequently, because the protocol includes both ⁇ ynchronous and a ⁇ ynchronous components, it i ⁇ mo ⁇ t accurately cla ⁇ ified a ⁇ "pseudo-synchronous."
- SUBSTITUTE SHET module ⁇ u ⁇ t be prepared to capture data at any time, a ⁇ DTACK* is not referenced during the transfer cycle.
- the transfer of data during a BLOCK READ cycle in the fast transfer protocol i ⁇ referenced only to DTACK*.
- the master first assert ⁇ DSO*.
- the ⁇ lave then broadca ⁇ ts data to the master and then asserts DTACK*.
- the master is given a predetermined period of timeafter the assertion of DTACK in which to capture the data.
- ma ⁇ ter module ⁇ mu ⁇ t be prepared to capture data at any time as DSO is not referenced during the transfer cycle.
- Fig. 7, parts A through C is a flowchart illustrating the operations involved in accompli ⁇ hing the fa ⁇ t transfer protocol BLOCK WRITE cycle.
- the master broadcast ⁇ the memory address of the data to be transferred and the address modifier across the DTB bu ⁇ .
- the master also drives interrupt acknowledge signal (IACK*) high and the LWORD* signal low 701.
- IACK* interrupt acknowledge signal
- LWORD* LWORD* signal
- the starting memory addre ⁇ of the data to be tran ⁇ ferred ⁇ hould reside on a 64-bit boundary and the size of block of data to be transferred should be a multiple of 64 bits.
- the block mu ⁇ t not cross a 256 byte boundary without performing a new addre ⁇ cycle.
- the slave modules connected to the DTB receive the address and the addres ⁇ modifier broadcast by the master across the bus and receive LWORD* low and IACK* high 703. Shortly after broadcasting the address and addres ⁇ modifier 701, the master drives the AS* signal low 705.
- the ⁇ lave modules receive the AS* low signal 707. Each slave individually determines whether it
- SUBSTITUTE SHET will participate in the data transfer by determining whether the broadcasted address is valid for the slave in question 709. If the address i ⁇ not valid, the data tran ⁇ fer doe ⁇ not involve that particular slave and it ignores the remainder of the data transfer cycle.
- the master drives WRITE* low to indicate that the transfer cycle about to occur is a WRITE operation 711.
- the slave receives the WRITE* low signal 713 and, knowing that the data transfer operation is a WRITE operation, awaits receipt of a high to low transition on the DSO* signal line 715.
- the master will wait until both DTACK* and BERR* are high 718, which indicates that the previous slave i ⁇ no longer driving the DTB.
- the ma ⁇ ter proceed ⁇ to place the first segment of the data to be transferred on data lines D00 through D31, 719.
- the master After placing data on D00 through D31, the master drives DSO* low 721 and, after a predetermined interval, drive ⁇ DSO* high 723.
- the slave In response to the transition of DSO* from high to low, respectively 721 and 723, the slave latches the data being transmitted by the master over data lines D00 through D31, 725.
- the master places the next segment of the data to be transferred on data lines D00 through D31, 727, and awaits receipt of a DTACK* signal in the form of a high to low transition signal, 729 in Fig. 7B.
- the slave then drives DTACK* low, 731, and, after a predetermined period of time, drives DTACK high, 733.
- the data latched by the slave, 725 is written to a device, which has been selected to store the data 735.
- the slave also increments the device addres ⁇ 735.
- the ⁇ lave then waits for another transition of DSO* from high to low 737.
- SUBSTITUTE SHET To commence the transfer of the next segment of the block of data to be transferred, the ma ⁇ ter drive ⁇ DSO* low 739 and, after a predetermined period of time, drive ⁇ DSO* high 741.
- the slave In re ⁇ ponse to the transition of DSO* from high to low, respectively 739 and 741, the slave latches the data being broadcast by the master over data lines DOO through D31, 743.
- the master places the next segment of the data to be transferred on data lines DOO through D31, 745, and awaits receipt of a DTACK* signal in the form of a high to low transition, 747.
- the slave then drives DTACK* low, 749, and, after a predetermined period of time, drives DTACK* high, 751.
- the data latched by the slave, 743 is written to the device selected to store the data and the device addres ⁇ i ⁇ incremented 753.
- the ⁇ lave waits for another transition of DSO* from high to low 737.
- the transfer of data will continue in the above- described manner until all of the data has been transferred from the master to the slave.
- the master will release the addres ⁇ lines, address modifier lines, data lines, IACK* line, LWORD* line and DSO* line, 755.
- the master will then wait for receipt of a DTACK* high to low transition 757.
- the slave will drive DTACK* low, 759 and, after a predetermined period of time, drive DTACK* high 761.
- the master In respon ⁇ e to the receipt of the DTACK* high to low transition, the master will drive AS* high 763 and then relea ⁇ e the AS* line 765.
- Fig. 8 parts A through C, is a flowchart illustrating the operations involved in accomplishing the fast transfer protocol BLOCK READ cycle.
- the master broadcasts the memory address of the data to be transferred and the address modifier across the DTB bus 801. The master
- SUBSTITUTE SHET drives the LWORD* signal low and the IACK* signal high 801.
- a special address modifier indicates to the ⁇ lave module that the fast transfer protocol will be used to accomplish the BLOCK READ.
- the ⁇ lave module ⁇ connected to the DTB receive the address and the address modifier broadcast by the master acro ⁇ the bu ⁇ and receive LWORD* low and IACK* high 803.
- the master drives the AS* signal low 805.
- the slave modules receive the AS* low signal 807.
- Each slave individually determines whether it will participate in the data transfer by determining whether the broadcasted address is valid for the slave in question 809. If the address is not valid, the data transfer does not involve that particular slave and it ignores the remainder of the data transfer cycle.
- the master drives WRITE* high to indicate that the transfer cycle about to occur i ⁇ a READ operation 811.
- the ⁇ lave receives the WRITE* high signal 813 and, knowing that the data transfer operation is a READ operation, places the first segment of the data to be transferred on data lines DOO through D31 819.
- the master will wait until both DTACK* and BERR* are high 818, which indicates that the previous slave is no longer driving the DTB.
- the raster then drives DSO* low 821 and, after a predete mined interval, drives DSO* high 823.
- the master then awaits a high to low transition on the DTACK* signal line 824.
- the slave then drives the DTACK* signal low 825 and, after a predetermined period of time, drives the DTACK* sigral high 827.
- a conventional 64 mA tri- ⁇ tate driver is substituted for the 48 mA open collector driver conventionally used in VME slave modules to drive DTACK*.
- the conventional VMEbus data drivers are replaced with 64 mA tri-state drivers in SO-type packages.
- the latter modification reduces the ground lead inductance of the actual driver package itself and, thus, reduces "ground bounce" effects which contribute to skew between data, DSO* and DTACK*.
- signal return inductance along the bus backplane is reduced by u ⁇ ing a connector system having a greater number of ground pins ⁇ o as to minimize signal return and mated- pair pin inductance.
- One such connector sy ⁇ tem i ⁇ the "High Den ⁇ ity Plu ⁇ " connector, Model No. 420-8015- 000, manufactured by Teradyne Corporation.
- Port A is the 8 bit data port.
- Port A P if used, is the odd parity bit for this port.
- the clock input is used to generate some of the chip timing. It is expected to be in the 10-20 Mhz range.
- Bit 2 Port A to Port B If set, data transfer is from Port A to Port B. If reset, data tran ⁇ fer i ⁇ from Port B to Port A. In order to avoid any glitche ⁇ on the request lines, the state of thi ⁇ bit ⁇ hould not be altered at the same time as the enable data transfer bits 0 or 1 above.
- Bit 3 Port B Parallel Parity Error Set if the chip is configured as the parity chip, i ⁇ not in parity correct mode, and a non zero re ⁇ ult is detected when the Parity Sync signal is true. It is also set whenever data is read out onto Port B and the data being read back through the bidirectional buffer does not compare.
- Port A Ack/Rdy will be negated every 16 byte ⁇ , or 8 words in 16 bit mode.
- Bits 0-7 are Fifo Data.
- the microproces ⁇ or may acce ⁇ the FIFO by reading or writing thi ⁇ register.
- config_data This is the data to be written to the configuration register.
- control_data This is the data to be written to the Data Transfer Control
- FIFO1->control & -FIFO PORT ENABLES; /* Disable Ports A & B */ " if (PORT_A TO PORT B(FIFO1)) ⁇ if (PORT_A_TO_RAM_Y(FIF01)) ⁇
- the following routine tests the microprocessor interface of the chip. It first writes and reads the first 6 registers. It then writes 1s, Os, and an address pattern to the RAM, reading the data back and checking it.
- the test returns a bit significant error code where each bit represents the address of the registers that failed.
- Bit 0 config register failed
- Bit 3 ram access control register failed
- Bit 4 ram X address register failed
- Bit 5 ram Y address register failed
- FIFO1-> config FIFO RESET
- j; /* read & check data */ if (FIFO1->checksum) error
- FIFO1-> config FIFO_RESET
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Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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DE69032069T DE69032069D1 (en) | 1989-09-08 | 1990-08-20 | FILE PROCESSOR STRUCTURE IN PARALLEL INPUT / OUTPUT NETWORK |
EP97112889A EP0837402A3 (en) | 1989-09-08 | 1990-08-20 | Parallel I/O network file server architecture |
EP90913922A EP0490973B1 (en) | 1989-09-08 | 1990-08-20 | Parallel i/o network file server architecture |
CA002066443A CA2066443C (en) | 1989-09-08 | 1990-08-20 | Parallel i/o newtork file server architecture |
AU64125/90A AU647414B2 (en) | 1989-09-08 | 1990-08-20 | Parallel I/O network file server architecture |
KR1019920700524A KR100201574B1 (en) | 1989-09-08 | 1992-03-07 | Parallel i/o network file server architecture |
HK98112876A HK1011772A1 (en) | 1989-09-08 | 1998-12-03 | Parallel i/o network file server architecture |
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US404,959 | 1989-09-08 | ||
US07/404,959 US5163131A (en) | 1989-09-08 | 1989-09-08 | Parallel i/o network file server architecture |
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WO1991003788A1 true WO1991003788A1 (en) | 1991-03-21 |
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PCT/US1990/004711 WO1991003788A1 (en) | 1989-09-08 | 1990-08-20 | Parallel i/o network file server architecture |
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EP (2) | EP0837402A3 (en) |
JP (1) | JPH05502525A (en) |
KR (1) | KR100201574B1 (en) |
AT (1) | ATE163485T1 (en) |
AU (2) | AU647414B2 (en) |
CA (1) | CA2066443C (en) |
DE (1) | DE69032069D1 (en) |
HK (1) | HK1011772A1 (en) |
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ATE179811T1 (en) * | 1989-09-08 | 1999-05-15 | Auspex Systems Inc | OPERATING SYSTEM STRUCTURE WITH SEVERAL PROCESSING UNITS |
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US5611070A (en) * | 1990-05-10 | 1997-03-11 | Heidelberger; Philip | Methods and apparatus for performing a write/load cache protocol |
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US7984221B2 (en) | 1997-12-31 | 2011-07-19 | Crossroads Systems, Inc. | Storage router and method for providing virtual local storage |
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US8046515B2 (en) | 1997-12-31 | 2011-10-25 | Crossroads Systems, Inc. | Storage router and method for providing virtual local storage |
US9785583B2 (en) | 1997-12-31 | 2017-10-10 | Crossroads Systems, Inc. | Storage router and method for providing virtual local storage |
US9565013B2 (en) | 1998-09-10 | 2017-02-07 | International Business Machines Corporation | Controlling the state of duplexing of coupling facility structures |
US9253046B2 (en) | 1998-09-10 | 2016-02-02 | International Business Machines Corporation | Controlling the state of duplexing of coupling facility structures |
US9860315B2 (en) | 1998-09-10 | 2018-01-02 | International Business Machines Corporation | Controlling the state of duplexing of coupling facility structures |
US10491675B2 (en) | 2001-10-01 | 2019-11-26 | International Business Machines Corporation | Controlling the state of duplexing of coupling facility structures |
US9542310B2 (en) | 2002-11-01 | 2017-01-10 | Hitachi Data Systems Engineering UK Limited | File server node with non-volatile memory processing module coupled to cluster file server node |
US9753848B2 (en) | 2002-11-01 | 2017-09-05 | Hitachi Data Systems Engineering UK Limited | Apparatus for managing a plurality of root nodes for file systems |
FR3103073A1 (en) * | 2019-11-12 | 2021-05-14 | Thales | MULTIMEDIA SERVER INTENDED TO BE ON BOARD AN AIRCRAFT, ELECTRONIC ENTERTAINMENT SYSTEM INCLUDING SUCH SERVER, SOFTWARE CONFIGURATION PROCESS FOR SUCH SERVER AND ASSOCIATED COMPUTER PROGRAM |
WO2021094180A1 (en) * | 2019-11-12 | 2021-05-20 | Thales | Multimedia server intended to be installed on board an aircraft, electronic entertainment system comprising such a server, method for configuring software of such a server and associated computer program |
Also Published As
Publication number | Publication date |
---|---|
JPH05502525A (en) | 1993-04-28 |
EP0490973A4 (en) | 1993-10-20 |
AU6412590A (en) | 1991-04-08 |
KR100201574B1 (en) | 1999-06-15 |
HK1011772A1 (en) | 1999-07-16 |
US5355453A (en) | 1994-10-11 |
CA2066443C (en) | 2003-10-21 |
CA2066443A1 (en) | 1991-03-09 |
ATE163485T1 (en) | 1998-03-15 |
IL95447A (en) | 1994-05-30 |
US5163131A (en) | 1992-11-10 |
IL107645A (en) | 1996-09-12 |
KR920704227A (en) | 1992-12-19 |
US5802366A (en) | 1998-09-01 |
DE69032069D1 (en) | 1998-04-02 |
US20020083111A1 (en) | 2002-06-27 |
EP0490973A1 (en) | 1992-06-24 |
US5931918A (en) | 1999-08-03 |
IL95447A0 (en) | 1991-06-30 |
AU670376B2 (en) | 1996-07-11 |
EP0490973B1 (en) | 1998-02-25 |
EP0837402A2 (en) | 1998-04-22 |
AU647414B2 (en) | 1994-03-24 |
EP0837402A3 (en) | 2000-08-09 |
AU6590594A (en) | 1994-09-01 |
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