WO1990015388A1 - Systeme informatique - Google Patents

Systeme informatique Download PDF

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Publication number
WO1990015388A1
WO1990015388A1 PCT/SU1990/000134 SU9000134W WO9015388A1 WO 1990015388 A1 WO1990015388 A1 WO 1990015388A1 SU 9000134 W SU9000134 W SU 9000134W WO 9015388 A1 WO9015388 A1 WO 9015388A1
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WO
WIPO (PCT)
Prior art keywords
memory
bus
block
output
data
Prior art date
Application number
PCT/SU1990/000134
Other languages
English (en)
Russian (ru)
Inventor
Boris Artashesovich Babaian
Vladimir Jurievich Volkonsky
Valery Yakovlevich Gorshtein
Alexandr Kiirovich Kim
Leonid Nikolaevich Nazarov
July Khananovich Sakhin
Sergei Vladimirovich Semenikhin
Original Assignee
Institut Tochnoi Mekhaniki I Vychislitelnoi Tekhniki Imeni S.A.Lebedeva Akademii Nauk Sssr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Institut Tochnoi Mekhaniki I Vychislitelnoi Tekhniki Imeni S.A.Lebedeva Akademii Nauk Sssr filed Critical Institut Tochnoi Mekhaniki I Vychislitelnoi Tekhniki Imeni S.A.Lebedeva Akademii Nauk Sssr
Publication of WO1990015388A1 publication Critical patent/WO1990015388A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode

Definitions

  • the invention is subject to computing technology, and more specifically, computing systems are concerned. 5
  • the invention may be used for engineering and technical calculations in the aerospace, geodesy, hydrometeorology, and other industries.
  • P ⁇ edshes ⁇ vuyuschy u ⁇ ven ⁇ e ⁇ ni ⁇ i Izves ⁇ na vychisli ⁇ elnaya sis ⁇ ema for nauchn ⁇ - ⁇ e ⁇ ni- Yuches ⁇ i ⁇ ⁇ asche ⁇ v s ⁇ de ⁇ zhaschaya tsen ⁇ alnye ⁇ tsess ⁇ y, us ⁇ ys ⁇ va vv ⁇ da-vyv ⁇ da in ⁇ matsii, us ⁇ ys ⁇ va ⁇ bschey ⁇ e ⁇ a- ⁇ ivn ⁇ y ⁇ amya ⁇ i, u ⁇ avlyayuschie v ⁇ dy-vy ⁇ dy ⁇ y ⁇ s ⁇ edine-
  • Computing systems for engineering systems are known, which contain input-output devices for computer processing, memory and central processing.
  • Such systems have a processor that supports arithmetic devices for operations on integers and floating-point numbers, which is a short-circuited instruction.
  • the computational system can contain up to fourteen processing nodes, controlled by a single basic meter.
  • the processing unit contains blocks of integer and floating arithmetic and registration files.
  • the main task of the invention was to create a computational system, which would have increased the profitability of the calculation and the calculation of the value of the calculation
  • Each central process is connected to each input / output device and to each shared memory.
  • the central process can contain a block of local memory, the input and output interface
  • an auxiliary storage device are not required to be removed - 4 - za ⁇ isi and mn ⁇ g ⁇ analny bl ⁇ inde ⁇ satsii, ⁇ bes ⁇ echivayuschy s ⁇ vmes ⁇ n ⁇ with bl ⁇ m vyz ⁇ va za ⁇ isi vy ⁇ ab ⁇ u ad ⁇ es ⁇ v in bl ⁇ l ⁇ aln ⁇ y ⁇ e ⁇ a ⁇ ivn ⁇ y ⁇ amya ⁇ i in any ⁇ bschuyu ⁇ e ⁇ a- ⁇ ivnuyu ⁇ amya ⁇ che ⁇ ez bl ⁇ ⁇ e ⁇ ev ⁇ da ma ⁇ ema ⁇ iches ⁇ g ⁇ ad ⁇ esa 5 ⁇ iziches ⁇ y ad ⁇ es, ⁇ susches ⁇ vlyayuschy ⁇ edva ⁇ i ⁇ elny You are a z ⁇ v s ⁇ i following
  • the computational system for scientific and technical research is based on the processing of information on the basis of the research.
  • the system is executed by a multi-process and contains many devices of I (fig.) Input-output of information, many of which have two memory devices
  • the bus serves for the exchange of auxiliaries; not shown), but the bus
  • 207 is the external bus for the computing system.
  • the maximum number of processes 3 is shared between the communication processors 3 and the general process memory 2.
  • the central process 3 contains unit 8 (Fig. 2) of the local electronic memory, the input / output terminal is connected (2), the drive is connected device 10 connection, connecting all units of process 3 (fig. ⁇ )
  • FIG. 30 with a block 8 (Fig. 2) of the local operational memory and bus 4 - with the general operating memory 2 (Fig. 2).
  • Process 3 also contains two or more arithmetic-logical devices II (Fig. 2), 12 data commutator connecting the aromatic-II logical device
  • the local address for the physical address and device is 10 connections, which are specified in the indicated order with tires 18.26 and 27 - block 8 and tires 18.26.4 - 2 k.
  • Process 3 also contains block 28 (Fig. 2).
  • 2524 bus adapter 37 is connected to the inputs of devices II, unit 21, unit 19, memory 13, unit 28, unit 30, and the unit is equipped with 12 data outputs, output from the 21 memory outlet 13 bus 39 is connected to the other input-
  • Each arithmetic-logical device II contains two 40.41 (fig. 3) units of service, two 42.43 units of multiplication, 44 and 45 units of division. First entrances of all blocks 40-46 are united, obra-
  • the recording call contains block 47 of the input registers, the output bus 48 of the received communication unit is connected to the total amount of 49 data transmission
  • the channel block 19 (Fig. 5) of the indexation contains all identical nodes; on the drawing, only one of these nodes is shown. It contains a buffer memory of 59 operations, inputs with 37 and 20 tires are connected to
  • 25 prices also include the sum of 63 phrases of the current address, the sum of 64 phrases of the current index, the sum of 65 65 phrases of the recording address and the sum of 66 of the base value. Amounts of 63-65 are connected to the output of 67 buffer memory 60, one input is
  • the outputs of sums 63 and 65 are the outputs of unit 19 and are connected by bus 18 to the outputs of unit 25 (Fig. 2) and devices
  • Week 70 (Fig. 5) of the total 64 connected to the external memory 60, output 71 of the 66 connected to the entrance of the resort 62.
  • Switch 12 (Fig. 6) this data contains memory 72 - 8 - incidents, inputs of the bus are connected by tires 37,23 with device 24 (Fig. 2) and devices II, reg. 73 (Fig.
  • One input connecting 74 and 75 is connected to the output 76 of the memory 72, the other input is connected to the bus 15 with the by-pass memory 13 (Fig. 2); , 75 connected to bus 37, leaving the exit 74 connected
  • circuit 75 is with bus 38.
  • the output of the buffer registers 92 (Fig. 7) is connected to bus 37.
  • the buffer memory 13 of this data contains a memory of 94 bits, a buffer memory of 95 stacks, a buffer memory of 96 reads.
  • the integrated inputs of the memory 94-96 are connected by buses 35,17,38 with the outputs of the device 10 (Fig. 2) of the connection, the device 16 and the data connection 12. ⁇ ique special
  • 35 memory inputs 94-96 are connected to bus 37 with a 24-speed device, and outputs 97, 98 memory 95.96 are connected to a memory card 99, and a memory card is connected .2).
  • Memory Card 94 (Fig. 7) - 9 - connected to a bus 39 with an external buffer system of 92 devices of 24 devices.
  • BLOCK 30 (FIG. 7) OF CONTROL OF THE BUFFER MEMORY OF THE COMMANDS CONTAINS REGULATIONS 100-102 NOMERA OF THE COMMANDS
  • Block 25 (Fig. 2) converting the mathematical address to the physical address contains a number of identical assistive devices and the node 112 (Fig. 8) of the table
  • Buffer memory 113 inputs connected bus 31 to block 28 (Fig. 2), bus 22 (Fig. 8) - block 21 (Fig. 2) call recording, bus 18 (Fig. 8) - to block 19 ( Fig. 2), and the output 118 is connected to the inputs
  • Output 123 is 116 output; - 10 - ass ⁇ tsia ⁇ ivn ⁇ g ⁇ za ⁇ minascheg ⁇ us ⁇ ys ⁇ va bl ⁇ a 25 ( ⁇ ig.2) and s ⁇ edinen s ⁇ v ⁇ d ⁇ m node 112 ( ⁇ ig.8) ⁇ ablitsy s ⁇ anits ⁇ e ⁇ a ⁇ ivn ⁇ y ⁇ amya ⁇ i, ⁇ y s ⁇ de ⁇ zhi ⁇ ⁇ egis ⁇ base s ⁇ anits 124, 125 summa ⁇ ⁇ mi ⁇ vaniya ad ⁇ esa s ⁇ i ⁇ ablitsy 5 and 126 ⁇ amya ⁇ ⁇ ablitsy s ⁇ anits, vy ⁇ d 127 is the output of node 112 and is connected to the inputs of associative storage devices of unit 25 (Fig.
  • the outlet 124 (FIG. 8) is connected to bus 22, its output 128 is connected to the output 125, output 129 is YUKOTO, and also output 127 is 126 and the bus is 22 pending.
  • Block 28 (Fig. 9) is equipped with a cheap 130 command, input to bus 37 is connected to 24 (Fig. 2), 131 basic utilities, 131 and the sum of 135.
  • the registers 131, 132,134 and the memory 133 are connected to the output 136 of the 130 unit, other inputs of the 133 memory and the 132 group are 38, 29 are 21 10 power and wiring 12 data.
  • Registration 131 (Fig. 9) and 132 and the secondary memory 133 are connected between themselves, the output of the engine line 131 is the output of unit 28 and is connected to bus 31, and output 137 is on buffer memory 133; 36 with a device of 10 (FIG. 2) conjugation.
  • a computational system works by managing an operating system, receiving tasks for 6 bus exchanges - II - the basis of the "family scheme".
  • Shared memory 2 is used for storing large arrays and general data for parallel process of different central processes.
  • the device has 10 connections between the general 2 and the local 8.
  • Availability in the system of a computing system is one-type
  • Each process 3 works as follows.
  • Bl ⁇ 30 vy ⁇ lnyae ⁇ ⁇ d ⁇ ach ⁇ u ⁇ g ⁇ ammn ⁇ g ⁇ ⁇ da of bl ⁇ - ⁇ a 8.
  • e ⁇ y purpose ⁇ n vydae ⁇ za ⁇ sy ⁇ bus 34
  • bl ⁇ 8 ⁇ g ⁇ ammny ⁇ d of ⁇ -5 ⁇ g ⁇ che ⁇ ez us ⁇ ys ⁇ v ⁇ 10 s ⁇ yazheniya ⁇ bus 35 ⁇ s ⁇ u ⁇ a- e ⁇ in bu ⁇ e ⁇ nuyu ⁇ amya ⁇ 29 ⁇ mand.
  • Unit 30 of the 32-bus control unit selects a different program memory from the memory 29, and the bus 33 runs on the 24-bus device.
  • Devices 24 for control on the bus 37 issue a command to the arithmetic-logical device II, in block 21 the recording, in block 19 of the program, and in the block 28 of the program
  • the bus 38 contains the indicated data to the memory bus 13. Data required for operation of block 19 of indexing is transmitted through block 21 of a call for recording
  • block 21 The basic purpose of block 21 is to read the scalar variable in memory of reading and writing. ⁇ in case of reading data in memory 13 block 21 via bus 22 it will give out addresses to an associative memorizing device 16 and in block 25 pane
  • Block 19 of the indexation is considered by the generatrix of the addresses of the elements of the arrays.
  • the bus 20 is loaded with disk arrays, which are protected by the use of the device, which is protected by
  • Case 16 and block 25 are similar to those described above for block 21 of the data recording call.
  • the command in process 3 has a variable length and can reach three hundred and six bytes.
  • ⁇ In command of maximum length, seven arithmetic-logical operations can be achieved (two services, two multiplications, two logical operations and one division), an operation for
  • device 10 provides for each reading of two words and commands and writing two words in memory 2 or block 8.
  • the buffer memory of 29 commands is executed by two instructions.
  • Buffer memory 13 is executed for sixteen schemes and provides for reading and writing in all eight ⁇ ⁇ 90/15388
  • Block 19 of the indexing is carried out by bus 18 for all, and block 21 of the call for writing to bus 22 is two addresses of 10 memory accesses.
  • the optional memory device 16 each processes two, and the block 25 converts the physical address into the physical memory.
  • Each process consumes a fee for all command words and prevents the transmission of a drive from one of the non-compliant transfers.
  • command word allows you to use the parallel process 3 to solve the problem, for example,
  • Transmission of control is carried out in two stages. ⁇ a 35 ⁇ e ⁇ v ⁇ m e ⁇ a ⁇ e ⁇ ⁇ mande ⁇ dg ⁇ v ⁇ i ⁇ e ⁇ e ⁇ da ⁇ is ⁇ di ⁇ za ⁇ minanie inde ⁇ sa ⁇ e ⁇ e ⁇ da on ⁇ dn ⁇ m ⁇ egis ⁇ v of 100- 102 n ⁇ me ⁇ a ⁇ mand, ⁇ is ⁇ ⁇ zadann ⁇ mu inde ⁇ su in ass ⁇ tsia- ⁇ ivn ⁇ m za ⁇ minaschem node 104 and issuing a s ⁇ ve ⁇ s ⁇ vuyuschy - 15 - Reg. 107-109 of the command index of the address of the memory card of 29 commands.
  • the device is executed with the help of the registry 83, in which the bus 23 is loaded with the conditional terms of the transmission of the calculations, calculated by the users of the computer;
  • the programmed storage is stored in a reserved memory of 29 commands in the packed form. This means that, with any widespread command, part of the group may be absent and significant part is placed without incident.
  • the sum of 89 is the number of the command decryption process, which is the basic address of the resultant of the resulting 72 results. - 16 - are used and performed by the current wide command.
  • the sum of 90 records the address of the recorded results of the memory 13.
  • the sum of 91 reads the address of the read memory of 95 memory and the buffer
  • the opened command is sent to the registers 92 and further to the bus 37 to the memory 13 (reading the instructions), to the command
  • Utility 12 data extracting the results, switching the components and the results), in the device II and the unit 21,19,28,30 (the operating system and the consumer)
  • the accessibility of the registers 92 is caused by the possibility of breaking the synchronized execution of commands due to
  • variable time of reading data operations from the operative memory to the backup memory of 13 data The variable time of reading data operations from the operative memory to the backup memory of 13 data.
  • the 3596 is an intermediate buffer between the portable memory 2 and the optional II devices, when the data is lost, it is used for this.
  • working - 17 - the use of variable (stack) is often used.
  • Commutation 12 (Fig. 6) of these data is provided with independently adjustable commutations of 74 process and commutators of 75 results.
  • the disconnector 74 of the devices commits the outputs of the 5 devices II and 21 to the same inputs, and the switch 75 to the inputs of the memory 13.
  • the 24 devices on the 37 bus are included in block 19 of the second part of the memory 59. The whole end of the
  • the address of the array element is aggregated to a total of 63 by compiling the base address of the array with the value of the current index of the array. For a total of 64 photos, - 18 - the value of the current index for the next conversion to the array (it changes by a step on moving to the array) and is entered into the buffer memory of 60 array descriptors.
  • the sums of 65 and 66 are used to configure addresses of 5 purposes with 96 read-only memory.
  • ⁇ bes ⁇ e- cheniya d ⁇ s ⁇ u ⁇ a in ⁇ amya ⁇ 96 is ⁇ lzue ⁇ sya me ⁇ d ⁇ e ⁇ edviga- emy ⁇ bases ⁇ gda in tsi ⁇ liches ⁇ y ⁇ g ⁇ amme ad ⁇ es zag ⁇ uzhae- m ⁇ y yachey ⁇ i ⁇ s ⁇ ae ⁇ sya ⁇ s ⁇ yannym and apel ⁇ vy ad ⁇ es for perform ⁇ g ⁇ node ⁇ b ⁇ ascheniya m ⁇ zhe ⁇ izmenya ⁇ sya in ⁇ azhd ⁇ m tsi ⁇ le 10 step ⁇ i ⁇ ascheniya base.
  • each node of block 19 of the indexation there are registers 61 and 62 of the rotation of the base and base.
  • the current address of destination is 96
  • the current value of base 15 is changed per step of rotation.
  • the new value of the base is recorded in the register 61 of the expansion of the base, and the formatted mathematical address of the array element and the destination address of the bus 18 out of all the nodes are 16- and 20-
  • Registry 124 is executed for a two-way flow, and in parallel with the corresponding speed of the fixed address, there is a fast process speed. For general applications - this is a mathematical address from a country that has been increased by one step to move to the mass. Formation of the address of the next page is the sum of 114.
  • the memory 126 of the pages of the pages contains the material and physical requirements. At a total of 125, the address of the required line of the table is read, and reading from the memory of the 26th table of the page is performed - 19 - prostrate. In case of organization of the page of the country, the method of loading is used, in connection with which it is possible to withdraw directly from the exit of the memory 126 to the free entrance.
  • the selected compliance line is entered into the 5th active memory of the 116 preset channel.
  • the download is made for the next material page.
  • Memory 113 serves for storage of memory in the case of 10 memory replenishment of 26 pages (the last of the current mathematical page. After recalling the memory to the optional memory 116).
  • the sum 117 serves to form the physical address of the word (the physical address of the current page is 15 and the word address inside the page).
  • the buffer memory of 115 data serves for storing the records recorded in the portable memory of the memory during the recording of the physical address of the record in the physical.
  • Block 28 prepares the product and switches off the 25th component of the process and the safety procedures.
  • General system registers time, clock
  • a pre-mated mathematical address after 5 exits to 54 is transmitted via bus 23 to the second input to 13 data card and to the other one to the bus - 21 - P ⁇ i ⁇ b ⁇ aschenii in ⁇ amya ⁇ i 2 us ⁇ ys ⁇ v ⁇ 16 bl ⁇ 8 ⁇ ch ⁇ eniyu s ⁇ mi ⁇ vanny ad ⁇ es with vy ⁇ dn ⁇ g ⁇ ⁇ egis ⁇ a 54 ad- ⁇ esa ⁇ ⁇ e ⁇ edae ⁇ sya on bus 22 and ⁇ e ⁇ vy ad ⁇ esny in ⁇ matsi ⁇ nny v ⁇ d ass ⁇ tsia ⁇ ivn ⁇ g ⁇ za ⁇ minascheg ⁇ us ⁇ ys ⁇ va May 16 and ⁇ e ⁇ vy ad ⁇ esny and in ⁇ matsi ⁇ nny v ⁇ d bl ⁇ a 25 Converting a mathematical address into a physical one.
  • the claimed computing system 20 ensures a high productivity of scalar and vertical computations due to the combination of the speed of the arsenal Intended use
  • the invention may be used for engineering purposes. Calculations in the space and aeronautical engineering, in geodesy, hydrometeorology and in the other environment.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Complex Calculations (AREA)

Abstract

Un système informatique de calculs techniques spécifiques, comprend au moins deux dispositifs (1) d'entrée et de sortie d'informations, au moins deux mémoires (2) opérationnellles communes et au moins deux processeurs centraux (3), dont chacun est connecté au dispositif (1) d'entrée-sortie d'informations, et à chaque mémoire (2) opérationnelle commune, de manière à permettre un traitement des informations sur le principe d'un mot de commande long.
PCT/SU1990/000134 1989-05-30 1990-05-28 Systeme informatique WO1990015388A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SU894691857A RU1777148C (ru) 1989-05-30 1989-05-30 Вычислительна система
SU4691857/24 1989-05-30

Publications (1)

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WO1990015388A1 true WO1990015388A1 (fr) 1990-12-13

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PCT/SU1990/000134 WO1990015388A1 (fr) 1989-05-30 1990-05-28 Systeme informatique

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WO (1) WO1990015388A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU692400A1 (ru) * 1977-05-20 1980-08-07 Предприятие П/Я А-3162 Вычислительна система
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
SU1168960A1 (ru) * 1982-12-21 1985-07-23 Ордена Ленина Институт Проблем Управления Многопроцессорна вычислительна система

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
SU692400A1 (ru) * 1977-05-20 1980-08-07 Предприятие П/Я А-3162 Вычислительна система
SU1168960A1 (ru) * 1982-12-21 1985-07-23 Ордена Ленина Институт Проблем Управления Многопроцессорна вычислительна система

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON COMPUTERS, Volume 7, No. 8, 1988, (US), ROBERT P. COLWELL et al., "A VLIW Architecture for a Trace Scheduling Compiler", pages 967-979. *

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