WO1990014715A1 - Magnetic effect transistor - Google Patents

Abstract

By applying a magnetic field perpendicular to a thin film high temperature superconductor (HTS) material (104) the HTS material may enter a mixed state, where the resistance can be controlled by varying the magnetic field. This variance of resistance may be utilized to develop a transistor-like device which can be combined to form logic gates. Using thin film techniques a scaled device can be constructed which allows use of the device in integrated circuits. A thin film magnet core is constructed in this integrated form to concentrate the magnetic field applied to the HTS material, thus reducing drive current requirements. Devices can be combined to form various logic gates and memory cells. A core memory using thin film magnet cores and HTS material is also described.

Description

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MAGNETIC EFFECT TRANSISTOR

Specification

Background of the Invention:

1. Field of the Invention:

The invention relates to superconducting materials, and more particularly to devices constructed of thin film, high temperature superconducting materials.

2. Description of the Related Art:

The use of superconducting materials in electrical applications has always been a goal of researchers. Early predicted uses, and in some cases rough prototype devices, included transmission lines, generators and motors. These applications were targeted because of the large currents that were present and the resulting thermal losses or resistance losses if conventional materials were used. The use of superconducting materials promised the use of the same or greater current levels with little heat generation or resistance loss. However, for many reasons, including the very low critical temperatures of the materials, the applications have not developed.

The low power dissipation was also a reason that superconducting materials were studied for use in microelectronic circuitry. The use of conventional semiconductor materials, even in CMOS configurations, resulted in significant power consumption and heat generation which posed significant heat dissipation problems. Josephson junction technology was developed and prototype devices were constructed. However, the very low critical temperatures necessary resulted in extreme handling and device construction problems. These problems, coupled with only a small performance improvement over alternate semiconductor technologies resulted in a general reduced effort of the research, even though the low dissipation properties were proven.

Magnetic switching has been done using thin films of superconducting materials. In these experiments, a magnetic field was utilized parallel to the thin film. The film was in superconducting state when no magnetic field was applied and in a normal state when the magnetic field was applied. Because the resistance of the thin film changed dramatically between superconducting and normal states, switching properties developed. However, the requirement that the magnetic field be in parallel imposed size limitations such that these prior devices could not be scaled down appropriately for use in large or very large scale integrated circuits. Additionally, the devices had very low critical temperatures.

The development of high temperature (greater than 77°K) superconducting (ΞTS) materials that required cooling only to liquid nitrogen temperatures removed some of the limitations associated with previous devices, but problems still existed. One group developed a high temperature superconducting switch using Y-Ba-Cu-O- .. (123) bulk material. A magnetic field was applied perpendicular to the rod of 123 bulk material. The applied field resulted in the 123 bulk material changing to the normal, resistive state, thus performing the switching function. A switching frequency of 1 kHz was shown for the particular sample.

SUBSTITUTESHEET -3-

Summary of the Invention:

The present invention uses a thin film, high temperature superconducting (HTS) material and a perpendicular magnetic field, with the applied magnetic field strength being less than the upper critical field (H ) strength. This results ^c2 in mixed state operation, where the superconducting material is slightly resistive, with the resistance controllable by the strength of the magnetic field applied. A transfer characteristic develops which is analogous to a field effect transfer (FET), with the device being able to be used in a similar fashion.

By the use of thin film materials combined with planar technology, lower strength, perpendicular magnetic fields can perform the switching and amplification functions on HTS thin film devices with reduced size individual unit cells, the individual cells being of a size acceptable for large scale integration to develop complex electronic circuits. In the simplest form of such a cell, a loop of HTS material is developed, with the center of the loop located over a strip of HTS material. Applying a current to the loop results in a perpendicular magnetic field being applied to the strip causing the resistance of the strip to change. Because of the relatively high currents required by this configuration to create the magnetic field needed for operation, a magnet core has also been developed which allows effective concentration of the magnetic field produced by the current in the loop. The loop surrounds or encircles a portion of the magnet core and the HTS strip is located in a narrow gap in the magnet core, so that higher field strengths result, reducing the amount of current needed to produce a given field strength. Sample logic gates utilizing the resistance change have been designed, such as AND, OR, inverter, flip-flop, and memory cells. A core memory using the magnet cores and HTS material conductors has been designed. Additionally, several methods for fabricating the device in an integrated size has been developed, so that a complex miniature device can be constructed. The methods use conventional thin film and semiconductor processing techniques.

Brief Description of the Drawings:

A better understanding of the invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:

Figure 1 is a perspective view of a device according to the present invention; Figures 2, 3 and 4 are various curves relating to the device of Figure 1;

Figures 5 and 6 are schematic diagrams illustrating a device according to the present invention of a circuit;

Figures 7A, 7B, 7C, and 7D are various logic gates formed from devices according to the present invention;

Figure 8 is a perspective view of an integrated unit cell;

Figures 9A, 9B, 9C, 9D, 9E and 9F are perspective views of an integrated unit cell with a magnet core in various states of fabrication;

Figures 10 and 11 are cross-sectional views of portions of devices made in accordance with the present invention;

Figures 12A and 12B are memory devices formed from devices according to the present invention; Figure 13 is a core memory formed from devices according to the present invention; and

Figure 14 is a cross-sectional view of one core of the core memory of Figure 13.

Detailed Description of the Preferred Embodiment: Referring now to Fig. 1, which generally shows a prototype of the invention, an electromagnet 10 was developed utilizing a ferrite core 12 having an air gap 14 and a coil 16 being formed by approximately 100 turns of copper wire. The core 12 was formed into a square shape approximately 1 5/8" wide and used material having a circular cross-section of approximately 7/16." diameter and was made of a material having a very low hysteresis effect so that a residual field is essentially not present when current is removed. A high temperature superconducting (HTS) material 18 was placed on a circuit board 20. For purposes of this description, high temperature refers to temperatures over 77°K, the liguification point of nitrogen. The circuit board contained four copper traces or conductors 22 which were connected to four contact points on the HTS material 18, two contact points near each end of the HTS material 18. The particular HTS material 18 used was a thaliu compound having the formula Tl₂Ca₂Ba₂Cu3θ₁₀ • The two inner conductors 22 were connected to a nanovolt meter 24 so that the voltage across the HTS material 18 could be determined. A controllable constant current source 26 was connected to the two outer conductors 22 so that a known current could be passed through the HTS material 18, with the resistance of the HTS material 18 then being able to be determined from the voltage across the material as measured by the nanovolt meter 24 and the current supplied by the current source 26. A second controllable constant current source 28 was connected to the coil winding 16 to produce a magnetic field B in the electromagnet 10.

The electromagnet 10 was hand-constructed and therefore was calibrated with the resulting curve of Fig. 2. As can be seen, the electromagnet 10 was calibrated over a range of produced magnetic field in the gap 14 of 100 to 900 gauss. In these cases, the current applied to the coil 16 by the current source 28 ranged from 1 amp to approximately 8 amps. It is noted that magnetic fields thus produced are well below the H or upper critical field density for the particular ^c2

HTS material 18 which was utilized.

The circuit board 20 containing the HTS material 18 was inserted in the air gap 14 of the electromagnet 10 and the device was placed in liquid nitrogen so that the HTS material 18 became superconducting. Varying currents were supplied by the current sources 24 and 28 so that different magnetic fields B were produced in the electromagnet 10 and differing currents of 1 mA and 5 mA were passed through the HTS material 18. This testing resulted in the curve of Fig. 3 which shows the relationship between the magnetic field current supplied to the coil 16 and the resistance of the HTS material 18. Thus, it is shown that magnetic fields in the range of several hundred gauss produce a significant resistive state in the HTS material 18, even though the HTS material 18 is just forced into a mixed state.

A series of tests were made which resulted in a voltage-current curve for a series of different magnetic fields and HTS material currents. These curves are shown in Fig. 4, with load lines of 0.1 and 0.01 ohms drawn over the curves. As can be seen, there is a relationship between the voltage and current curves and the magnetic field applied perpendicular to the HTS material 18. The change in voltage in the presence of varying or different magnetic fields can be utilized to develop electrical devices. These curves are similar to the drain to source voltage versus drain current curves of field effector transistors (FET's), with which many analogies then develop. Thus the operation of a device referred to as a magnetic effect transistor (MET) is shown.

While the experiment described above was conducted using a particular HTS material of Tl₂Ca₂Ba₂Cu₃0_1Q, recently several classes of metal oxides have become known which are bulk superconductors at a temperature above 77°K, the boiling point of liquid nitrogen. One class of such high temperature superconductors is now widely known as the "123" superconductor. The "123" type of HTS material comprises a metal oxide of the formula L_lM2Cu₃0_6+d wherein L is Y or a rare earth element of atomic number 57 through 71, preferably Y, La, Nd, Sm, Eu, Gd, Dy, Ho, Er, Yb, Lu, or mixtures thereof; M is an alkaline earth metal, preferably Ba, Sr, Ca or mixtures thereof; and "d" is a value between 0.1 to about 1.0, preferably between 0.5 to 1.0. -7-

The "123" class of superconductor materials exhibit zero electrical resistance at temperatures above 77°K. The most preferred types of "123" superconductor are Y Ba.Cu-0, ,.

The "123" class of high temperature superconductor materials may be prepared by intimately mixing the requisite metal oxides, metal hydroxides, metal nitrides, metal-organic compounds or metal carbonates in quantities appropriate to provide the desired atomic ratio of cations, the most preferred ratio being L-R^Cu-, and reactively sintering the mixture until the maximum content of

is obtained.

Generally, at or about the temperature wherein reactive sintering is accomplished the species produced is one wherein the oxygen content is close to L-M₂Cu₃0₆ and this species is not generally superconductive. As the reaction product species cools from its reaction temperature to ambient temperature in air, or more preferably, in an oxygen atmosphere, its oxygen content increases to a value close to L₁M₂Cu₃0₇, which is the superconductive species. Accordingly, in preparing a "123" superconductor of optimum superconductive properties, it is preferred to slowly cool the product from its reaction temperature (i.e., about 850-1000°C) to about 400°C in an oxygen atmosphere. This procedure provides oxygen the maximum opportunity to diffuse into the material and to maximize the oxygen content of the product towards the ₁M₂Cu₃0„ limit. Alternatively, and equally suitable, the 123 composition may be produced to a stoichiometry close to ₁M₂Cu₃O_{g 5} by quickly cooking it from its reactive sintering temperature to ambient temperature, and thereafter subsequently annealed in air or, preferably an oxygen atmosphere, at a temperature of from about 600 to about 400°C to increase its oxygen content to a value close to L₁M₂Cu₃0₇.

In utilizing the "123" class of superconductive materials for fabricating devices of this invention, it is preferred that after deposit of a layer of "123" material on the substrate, the substrate with deposited "123" be annealed in an oxygen atmosphere to insure that the "123" composition attains an oxygen content close to I^M^ -O-. The conditions necessary for preparing the 123 type superconductive compositions are now well known to those of skill in the art. See for instance Chemtech, Vol. 17, pp. 542-551 (1987). Further, variants of the "123" types of materials, such as those prepared as thin films having a stoichiometry of YBa₂Cu₄0_, are now known. See Nature, Vol. 334, pp. 141-143 (1988). Accordingly, as used herein the term "123" superconductor is intended to include mixed phase composition containing a sufficient quantity of the species ₁M₂Cu₃0_g+, as to render the composition a bulk superconductor. Further, as used herein the formula

is intended to include variants of the L1,M2Cu3_0„7 species, such as for example YBa₂Cu₄0_g, which are superconductive at temperatures above 77°K. Other representative classes or systems of superconductors which have zero resistance above 77°K which may be used in fabricating devices of this invention are: 1. The Bi-Ca-Sr-Cu-0 System. Such systems are produced by the solid-state reaction of Bi₂0₃, CuO, SrC0₃ and CaC0₃ in air and are well known to those skilled in the art. For example, R.H. Hazen, et al., Phys. Rev. Lett. 60, 1174 (1988) discloses four distinct phases in such oxide systems. The superconducting phase, having an onset temperature of approximately 120°K, is of the formula Bi₂Ca₂Sr₂Cu₃0 . 2. The Tl-Ca-Ba-Cu-0 System. Such oxide systems are produced by mixing, grinding and pressing into a pellet T1₂0₃, CaO and BaCU_gO-. The resulting pellet is then heated for approximately 3 to 5 minutes in the presence of oxygen in a preheated furnace, at approximately 880 to about 920°C and then cooled to room temperature in about 1 hour.

Alternatively, the samples can be prepared in a molten state at a temperature between about 900 and about 950°C. Samples of nominal composition Tl₂Ca₂Ba_Cu_0₁₀ are reported in Sheng, Appl. Phys. Lett. 52, 1738 (1988). The materials of these systems are also capable of being deposited and annealed, as is the "123" material. Various doping materials can also be added, to the HTS materials to alter their characteristics as necessary.

Additionally, while the magnetic field is described as being perpendicular to the HTS material, this is the preferred embodiment and deviations from perpendicular are allowable, the deviations changing the strength of the magnetic field which must be applied for a given resistance. An MET device according to the present invention can be miniaturized as necessary for large scale or very large scale integration. A unit cell of the simplest MET device is shown in Fig. 8. An insulator 100 is applied over a satisfactory substrate material 102. The substrate material may be a polycrystalline material or can be monocrystalline silicon or other semiconductor materials. The insulator 100 can be made from insulating materials commonly utilized with HTS materials which serve as diffusion barriers and electrical insulators such as 2r0₂, MgO, SrTi0₃, Si0₂, A1₂0₃, LiNb0₃, NdGaθ₃, LaGaθ₃, KTa0₃, BaTi0₃, MgAl₂0₄ or other insulating materials which can withstand the temperatures developed in annealing the HTS material, have a coefficient of expansion sufficiently close to the HTS material and the substrate and have negligible interaction with the HTS material and the substrate during heating. CaF₂ can be used as an electrical insulator and diffusion barrier between 123 material and the substrate. Additionally, the substrate 102 and the insulator 100 can be combined into a single material or can be two different materials as generally used in this description.

In the device of Fig. 8, an HTS strip 104 is deposited over the insulator 100. This HTS strip 104 is equivalent to the HTS material 18 of the device of Fig. 1. A layer of insulator (not shown for clarity reasons) is deposited over at least the HTS strip 104 and preferably over the entire surface. A loop 106 of HTS material, or conventional thin film metal or alloy materials if higher current densities are required, is then placed over the insulated surface so that the effective center of the magnetic field produced if current is passed through the loop 106 is located vertically with respect to the active area of the HTS strip 104. Thus, when a current is passed through the loop 106, a magnetic field is developed substantially perpendicular to the plane containing the upper surface of HTS strip 104, thus causing the HTS strip 104 to enter mixed state and develop the resistance effects previously discussed. The HTS material usually needs to be annealed, with this annealing being done after each deposition of the HTS material. Some in situ lower temperature HTS thin film processes recently developed can also be used. This avoids the high temperature post-annealing step and makes the process more compatible with the magnetic material processing. While the use of HTS materials is preferred, low temperature superconductors such as Nb₃Sn, Pb, Ta, tin and so on can be used in the place of the HTS material if desired.

The simple cell of Fig. 8 has a drawback in that a relatively large current must be passed through the loop 106 to develop the magnetic field, preferably in the range of several hundred gauss, used to induce mixed state operation in the HTS strip 104. This high current requirement may approach the critical current density of the HTS material when the unit cell is -of dimensions suitable for integration, such as a 5 micron by 5 micron unit cell dimension, such that the strip 104 and loop 106 are approximately 1000 A to 1 micro thick and have widths of 1 to 2 microns. To overcome this current limitation a magnet core can be utilized as in the large scale embodiment of Fig. 1, wherein the magnet core is formed with a gap which focuses and concentrates the magnetic flux lines of the field so that the magnetic energy is more effectively utilized in the HTS material. The magnet core allows the magnetic field to be concentrated on the HTS strip 104 by two to three orders of magnitude, thus greatly reducing necessary current densities or allowing smaller conductors to be used. In this preferred embodiment, a portion of the controlled HTS material strip is situated within the gap of the magnet core so that the induced magnetic field is focused thereon to more effectively control the state and therefor the resistivity of the controlled HTS material. -11-

A unit cell having a magnet core can be fabricated as shown in the sequence of drawings of Figs. 9A-9F. In Fig. 9A, an insulator 100 is again over a substrate 102, the insulator performing the functions of electrical insulation and diffusion barrier, as in the cell of Fig. 8. Two separate materials which dependently perform the electrical insulation and diffusion barrier functions can be used if desired. Over this insulator 100 is deposited a strip or bar of magnetic material 108. The magnetic material is material which preferably has a relatively high permeability, is high frequency compatible, and has a low residual field. As examples, iron nickel alloys, such as Fe-Ni, Fe-Ni-Mo, Fe-Ni-Mo-Mn, Fe-Ni-Cr, Fe-Ni-Mo-Cu, Fe-Ni-Cu-Cr, Fe-Ni-Mn, and others; and ferromagnetic ferrites, such as Ni-Zn ferrite, Cu-Zn ferrite, Mn-Mg ferrite, Mn-Mg-Al ferrite, YIG (Y₃Fe₅0₁₂), hexagonal ferrite and others, can be used. The insulator 100 is preferably 1 to 2 microns thick while the magnetic material is preferably approximately 1000 & to 2 microns thick and is approximately 1 to 2 microns wide. The various unit cells of Figures 8, 9A-9F, 10 and 11 are shown greatly exaggerated and not in a consistent scale to more easily show the development of the cells for purposes of explanation. The thickness of the magnetic bar 108 is a balance based on the field to be carried and the process techniques used. If the bar 108 is made thin to allow certain techniques to be used, it may be too thin to carry a sufficient magnetic field while, if it is made thick, shadowing results, complicating the processing. The length of the magnetic bar 108 is as necessary for a given cell size, the cell preferably being 2 to 10 microns square.

A center region 110 (Fig. 9B) is next etched from the magnetic bar 108 so that the magnetic material has two raised ends 112 and 114 with a central depression 110. The magnetic bar 108 thus forms a portion of the magnet core to be used in concentrating the magnetic fields. Alternatively, the magnetic bar 108 can be formed of a uniform thickness and additional ferromagnetic material deposited to develop the raised ends 112 and 114 and the depressed central depression 110. In yet another alternative embodiment, no depressed center region is developed, but the magnetic material closing -12-

the core has an elevated center section based on layer thickness. The depressed center region embodiment is preferred. Over the magnetic material and preferably the entire surface 100 a layer 107 (Fig. 10) of insulator is deposited, this insulator layer preferably being approximately 500 A thick. For clarity this insulating layer is not shown in the construction drawings.

In the next step of the process the HTS material is deposited. The HTS material is applied in two locations, a strip 115 and a loop 116 (Fig. 9C). The strip 115 is formed to overlay the raised end 112 of the magnetic bar 108 so that it will be located in the gap when the magnet core is completed. The loop 116 is located such that it passes through the recessed center portion 110 of the magnetic bar 108, thus forming a one loop coil around the other raised end portion 114 of the magnetic bar 108. The loop 116 can have several different shapes, such as those shown in Figs. 8 and 9A-9F, to confine the magnetic field in an area as desired. The HTS material is preferably 500 to 2000 A thick and 1 micron wide, with the loop 116 being preferably 4 microns wide measured across the ends 113 and 117. The HTS material is annealed at this stage, if required.

After the HTS material has been annealed, yet another layer 119 (Fig. 9D) of insulator is placed over the entire cell, with the layer 119 being approximately 200-1000 . thick, preferably just enough for diffusion barrier and electrical insulation. Only a portion of this layer 119 is shown in the figure for clarity. The HTS material strip 115 and the insulating layers 107 and 119 are preferably as thin as possible to reduce the gap in the magnet core being formed. By keeping the gap thin, less current is needed in the loop 116 to produce the desired magnetic field of several hundred gauss in the gap. For example, if a 1 milliamp current is used, a gap of approximately 5000 X results in a field of approximately 30 gauss, while narrowing the gap to 1000 results in a field of approximately 150 gauss, the desired range. Keeping the gap size small reduces the possibility of approaching the critical current density of the HTS material forming the loop 116, thus allowing HTS material to be used -13-

for all conductors and not requiring conventional metal or alloy conductors to be used to form the loop 116.

In the next step of the process, two holes are formed in the insulation layers by etching. The first hole 118 (Fig. 9D) is located over the second raised end 114 of the magnetic bar 108, to allow access to the magnetic material forming the raised end 114. This hole is formed by etching through insulating layers 107 and 119. The second hole 120 is located over the HTS strip 115 on the raised end 112 by etching through insulating layer 119 to expose a portion of HTS strip 115. While this hole is not required, the development of this hole allows the magnetic material which will be deposited next to come in closer contact with the HTS strip 115, thus reducing the gap of the magnetic core and further concentrating the magnetic flux. The holes are preferably 1 micron square.

In the next stage of the process a strip of magnetic material 122 is deposited spanning between and filling holes 118 and 120, thus completing the magnet core (Fig. 9E). The magnetic material 122 is preferably approximately 1000 & to 2 microns thick and approximately 2 microns wide. Because of the etched hole 118, the magnetic material 122 is in contact with the raised end 114, so that a magnetic path having a high permeability is developed, thus concentrating the magnetic flux in the gap formed between raised end 112 of strip 108 and end 123 of the magnetic strip 122 (Fig. 9E). The magnetic core material may need treatment after deposition. The magnetic materials may be post-annealed, followed by slow or fast cooling or quenching processes, in order to obtain the appropriate properties. The annealing temperature may range from a few hundred degrees to about 1000°C. The deposition and/or annealing may be carried out in a magnetic field or appropriate atmosphere or both, depending on the properties desired. The annealing can be performed at this time, when the magnetic material is deposited, or can be combined with the annealing step of the HTS materials whenever the annealing temperature and atmosphere are compatible_^,for both materials. A final layer of insulating material 121, approximately 5000 A thick, is then deposited over this entire cell, thus insulating and protecting the cell. For clarity this final layer of insulation is not shown in the construction drawings. The cross-sectional view of Fig. 10 is provided to illustrate the insulation layers with regard to the other elements of the unit cell.

If connection to external leads is desired, contact holes can be etched into appropriate locations on the strip 115 and the loop 116 to allow contacts to be made. After the contact holes are formed, metallic contacts 124, 126, 128 and 130 can be deposited as is customary in semiconductor applications. Alternatively, these contacts are not necessary if the unit cell is to be connected with other similar unit cells in an integrated device, wherein the HTS material can be extended to provide the interconnections between the various unit cells.

Construction of the unit cell may be accomplished using some conventional suitable deposition techniques available for thin film depositions, such as sputtering, resistance heating, laser ablation, chemical vapor deposition, electron beam deposition and so on. Sputtering is preferred for uniform coating in all directions to protect edges and corners of the structures as well as reducing shadowing effects. If shadowing effects are prevalent with the material thicknesses and deposition process used, planarization techniques can be employed to eliminate shadowing effects. The depositions are performed after appropriate masking of the surface so that materials are deposited only where desired. The various etching steps can be performed by any of a series of etching processes which are compatible with the materials, such as sputtering, wet or dry etching or plasma etching. Photoresist lift-off or ion implantation processes can also be used for the various patterning steps. In general, the processes to be utilized in forming the unit cells and in an integrated device using a plurality of the unit cells is based on variations in -15-

customary and conventional semiconductor and thin film processing techniques.

The unit cell could be, for example, 2 microns, 5 microns, or 10 microns square, depending upon scaling factors and the sophistication of the technology used. One concern in the scaling process is that the current density contained in the various strips and loops of HTS material not exceed the critical current density of the material. For this reason, the magnet core design is considered preferable because this allows a reduction by several orders of magnitude in the actual currents required to produce the desired magnetic fields. This, coupled with the currently high and still ever-increasing critical current densities for available HTS materials, shows that the large device demonstrated is capable of being scaled down to appropriate levels for semiconductor-type large scale integration.

An alternate embodiment of the unit cell is shown in cross-section in Figure 11 with the layers of the device being visible. The unit cell of Figure 11 is readily adaptable for planarization or readily adapted so that shadowing does not occur by using sufficiently thin dimensions to allow use of sputtering or other techniques to eliminate shadowing problems. A combined insulator and substrate 101 is used as the basis for forming the device. Over the combined isulator and substrate 101 is deposited magnetic material forming the lower magnet base 150. This strip of magnetic material is preferably 1000 to 5000 & thick. A thin insulating layer 152 is deposited over the entire surface. This insulating layer is preferably 200 to 1000 A thick and is sufficiently thin to form a diffusion barrier and electrical insulation but is preferably no thicker than necessary for gap size reasons. Over this insulating layer 152 is deposited the HTS strip 154 and the HTS loop 156. The HTS strip 154 is preferably as thin as possible for reasons previously discussed and both the strip 154 and the loop 156 are preferably from 500 to 5000 thick. Over this, a very thick layer of insulator 158 is developed. This insulator is preferably several microns thick. Two holes or windows are etched in the thick insulator 158 and the thin insulator 152 so that a first vertical portion 160 and a second vertical portion 162 are developed. The vertical portion 160 preferably stops leaving from 500 to 1000 of insulating material remaining over the HTS strip 154. The vertical portion 162 reaches to the lower magnet base 150 to allow a complete magnetic circuit to be performed. This etching to two different levels can be done by utilizing two masks or by utilizing a single mask then covering one hole while the second hole is etched to a deeper depth. Inside the vertical portions 160 and 162, magnetic material is deposited until the magnetic material reaches the top of the insulating layer 158. Over the insulating layer 158 is then deposited the upper magnet bar 164, thus forming a magnet core having a small gap with the HTS material 154 located in that gap between two insulating layers which provide the necessary electrical insulation. The magnet bar 164 is preferably 1000 to 5000 . thick. A final insulating layer 166 is applied over the entire surface for protection. If contact holes are desired, they are then made after this insulation layer is performed and the appropriate metallic contacts deposited as in the previous unit cell.

If semiconductor-grade materials are utilized as the substrate 102, then it is possible to mix semiconductor and superconducting devices on the same substrate. The semiconductor devices could be processed in normal methods and the superconducting devices could be developed as stated above. Thus, the present invention provides a method of combining the two different technologies so that optimization of the overall circuit can be developed, utilizing the advantages of each technology. For example, the semiconductor devices can readily be configured to form the current sources used in current mode operation of the device as will be described.

Several MET devices utilizing the circuit of Fig. 1 are shown in Figs. 5 and 6. Figure 5 is a current mode device wherein a current source 50 provides a current through the -17-

HTS material 18. The HTS material 18 has a resistance of R_a-,_s and has connected to it a parallel load resistor R . The current being supplied by the current source 50 thus produces an output voltage V_Q across the HTS material 18. If no magnetic field is applied to the HTS material 18, then R- _s is equal to 0, so that the output voltage V_Q is 0. If, however, a magnetic field is applied to the HTS material 18, then a resistance develops in the HTS material 18 so that R_jj-,- is no longer 0 and a voltage develops across the device. If the magnetic field is increased such that rrr_p is significantly greater than R_L, then the output voltage is essentially the current I 1- times the resistance RL_ri of the load resistor. This increase in the output voltage _Q can thus indicate a logic level change. The MET device of Fig. 6 is connected for voltage mode operation in which a pullup resistor _p is connected in series with the HTS material 18, with the pullup resistor R_p connected to one terminal of a battery 52 having a voltage V_β and the HTS material 18 being connected to the other terminal of the battery 52. Again, the output voltage V is measured across the HTS material 18, with the voltage being 0 when the magnetic field is not applied and being greater than 0 when the magnetic field is applied to the HTS material 18. Assuming that the resistance ^_g of the HTS material 18 is significantly greater than the resistance of the pullup resistor R_ for a magnetic field corresponding to a one or high logic level, then the output voltage V_ becomes a significant portion of V and thus a one or high logic level is developed. Various logic gates can be developed using the MET devices as shown in Fig. 7A, 7B, 7C, and 7D. Figure 7A shows an OR gate configuration in which an MET device 70 according to the present invention is connected with a second MET device 70 to form a series combination of the two MET devices, which MET devices 70 are then pulled up by a resistor 72 to a voltage source V. If no current is supplied to the coils A or B of the two MET devices 70, then the output voltage V_Q is low. However, if a current is supplied to either coil A or B to produce a magnetic field, then the resistance of the MET device 70 increases such that V becomes non-zero, and with proper selection of values and applied strengths of the fields, develops a voltage level at the output voltage V_Q which can be considered to be the high logic level. Therefore, if either MET device 70 receives a current in its coil A or B corresponding to an input logic level one signal, then a logic level one output signal is developed at the output voltage V_. An alternate embodiment (Fig. 7A) of the OR gate utilizes a single MET device 70 with two coils A and C being utilized around the magnet core or directly applying a magnetic field to the HTS material 18.

An AND gate (Fig. 7B) is constructed by the parallel connection of two MET devices 70, with the devices being pulled up by a resistor 74 to a voltage V. The output voltage V_Q is taken at the connection between the pullup resistor 74 and the MET devices 70. Therefore if either device does not have a current applied to the coil A or B, then that particular MET device has a 0 resistance and thus a low output level results on the output voltage V₀. However, if both coils A and B are receiving an amount of current designated as a logic high or one level, then the parallel resistance of the two MET devices 70 is such that the output voltage V_Q reaches a high level, thus showing AND gate operation.

An inverter circuit is shown in Fig. 7C. Two MET devices 70A and 70B are utilized to form the inverter. An output MET device 70B is connected in conventional voltage mode operation with the outputs of MET device 70B connected to ground and to a pullup resistor 76. The arrangement of the input MET device 70A is somewhat different in that while one output terminal of the input MET device 70A is connected to ground, the other output terminal is connected to one terminal of the input coil of the output MET device 70B, the second terminal of the coil being connected to a pullup -19-

resistor 78. I no current is supplied to the coil 71 of the input MET device 70A, current is flowing through the coil 73 of the output MET device 70B, thus resulting in a logic high voltage condition of the output voltage V_. If however, a current is supplied to the coil 71 of the input MET device 70A, then the current through the coil 73 of the output MET device 70B is dramatically reduced because of the increased resistance of the input MET device 70A. This results in a reduced current in the coil 73 and thus a reduced magnetic field effecting output MET device 70B, so that the output voltage V_Q is reduced to levels considered to be the low level for digital operation.

A flip-flop 310 is shown in Figure 7D. Two MET devices 70G and 70H are utilized to form the flip-flop 310. The two MET devices 70G and 70H are connected in a symmetrical cross-coupled configuration with one terminal of the coils of the MET devices 70G and 70H being connected to ground and the other coil terminal of each MET device 70G and 70H being connected to one output terminal of the other MET device 70H and 70G. The other output terminal of each MET device 70G and 70H is connected to a constant voltage source V . By this cross-coupled configuration whenever one MET device, for example 70G, is in a resistive state, insufficient current flows from the voltage source V through the MET device 70G to the coil of the second MET device 70H to cause the MET device 70H to enter the mixed state. Therefore, because there is insufficient current in the coil of the second MET device 70H this MET device 70H is in the superconducting state and therefore at a zero level. Because this MET device 70H is at a zero level, there is not appreciable resistance and thus sufficient current can flow from the voltage source V through the MET device 70H and through the coil of the first MET device 70G so that the MET device 70G stays turned on in the one or resistive state. If a current is supplied to the coil of the second MET device 70H, then that MET device 70H enters a one or resistive state, thus decreasing the current available to the coil of the first MET device 70G, thus causing that MET device 70G to enter the superconducting or zero state. Therefore the state of the flip-flop 310 is changed by driving a one level to the coil of the zero valued MET device 70G or 70H. In Figure 7D, the first MET device 70G is considered to be the noninverting output or noninverting device and the other MET device 70H is considered to be the inverting output.

The state of the particular output is determined as usual by measuring the resistance to ground of the particular output. In this case, the coil loops must be formed of HTS material so that the resistance of the coil loop does not interfere with the resistance level sensing which is used to determine the flip-flop state. The flip-flop 310 of Figure 7D is set to a one condition by driving a current to the preset input P, through a resistor 306 and thus through the coil of the first MET device 70G. The resistor 306 is preferably used in a coil input loop because of the difficulties involved in driving a superconducting zero resistance coil loop. Because of the very low resistance of the coil loop, any voltage source which must drive the loop would have an effective output of only picovolts or nanovolts, which is an extremely difficult level to develop. Therefore, by inserting a series resistor 306 in the circuit, more conventional voltage sources can be used "to drive the coil of the MET device 70. A similar resistor 308 is inserted in the control loop from the clear input C to the coil of the MET device 70H. Thus, an appropriate pulse of current on the P or C inputs to the flip-flop 310 appropriately causes the flip-flop 310 to enter the set or cleared condition as desired.

With a storage element thus defined by the flip-flop 310, a memory cell 198 can be developed utilizing the flip-flop 310 as the storage element (Fig. 12A). Assuming that the memory cell 198 will be in a matrix, two MET devices 70E and 70F are configured into an AND gate 204 to be used for addressing purposes. The coil input of the first MET device 70E is connected to the column line Y , while the coil of the second MET device 70F is connected to the row line Xm.

With the combination of the AND gate 204, whenever both the X and Y address lines are properly present, the output of the AND gate is a high levelsresistance. In other conditions, the output of the AND gate 204 is a low level resistance to ground.

Three MET devices 70C, 701, and 70J have their coils connected in series between a voltage supply and the output of the AND gate 204. Thus, whenever the AND gate 204 has a high resistance or one output, as when it is being addressed, then the three MET devices 70C, 701, and 70J are in a zero resistance state. Alternately, when the AND gate 204 has a zero resistance or zero value, then current is flowing through the coils of the three MET devices 70C, 701, and 70J and they are in a one or high resistance state. A data input one value line _IN- is connected to one of the output terminals of MET device 701, with the second output terminal being connected to the preset input P of the flip-flop 310. Thus, whenever a current is provided on the _IN1 line and the cell 198 is being addressed, a current is driven into the preset input P of the flip-flop 310 and the flip-flop 310 is set to a one state. A data input zero value line D_TN_ is connected to one of the output terminals of the MET device 70J, with the second output terminal being connected to the clear input C of the flip-flop 310. Therefore, whenever a current is driven on the D_INQ line, the flip-flop 310 is cleared. The state of the flip-flop 310 is read on the data output line _QUT which is connected to one output terminal of the MET device 70C. The second output terminal of the MET device 70C is connected to the noninverting output of the flip-flop 310. The cell 198 is read by addressing the cell 198 and then determining the resistance to ground of the data output line _QUT. If the cell 198 is not addressed, a high resistance is present, while if the cell is properly addressed, then the resistance to ground of the output line

^D _OUT ""'^{s the res}i^{stance of tile} flip-flop 310 and thus the state of the flip-flop 310. Thus a memory cell 198 has been defined which allows isolation of the various cells from each other and yet allows a storage state to be readily accessed by the system. -22-

A memory array of four identical memory cells 200 is shown in Fig. 12B. The four memory cells 200 are configured in a two by two matrix to form a four bit by one bit memory. Four MET devices 70C, 70D, 70E and 70F are utilized and one memory MET (MMET) device 202 is utilized to form a memory cell 200. The MMET device 202 is similar to an MET device 70, except that the magnet core of the MMET device 202 is formed of magnetic materials which are readily magnetized and have a remanent or residual state. An exemplary magnetic material is supermalloy, 79 N. , 5 Mo, 0.3 Mn. Preferably the magnetic material does not have a square hysteresis loop. When a sufficient magnetic field is applied to the material, in this case a magnet core, and the field is removed, a residual magnetic field remains. In the case of the MMET 202 the HTS material strip 115 is thus in a mixed state when no current is applied to the coil and the magnet core is in a residual state. If the MMET 202 is energized by a sufficient magnetic field of either polarity sufficient so that a residual field develops, a value of one is developed. When a magnetic field sufficient to cancel the residual field is applied to the MMET 202, a zero value develops because the HTS material strip 115 is no longer in mixed state. If a magnetic material having a square hysteresis loop was used, a proper current could not be applied to cause the residual field to be cancelled, any field sufficient to end the given state flipping the field to the opposite state. Therefore a memory effect is developed by using the magnetic materials to form the magnet core. This memory effect can be used to form the basis of a memory MET 202 and a memory cell 200. Addressing and data buffering logic is added to the MMET 202 forming the memory element of a memory cell 200. Two MET devices 70E and 70F are configured in an AND gate 204 arrangement and have their coils connected to the row X and column Y drive lines, which are also preferably formed of HTS material. This AND gate 204 thus serves to perform the addressing function of the cell. Whenever the output of the AND gate 204 is high, that is resistive, the memory cell 200 is being addressed. -23-

The coils of the buffering MET devices 70C and 70D are connected in series between the voltage or current source'"and the AND gate 204. The data input buffering MET device 70D has its HTS material strip 115, that is, its outputs, connected to the data input line D_IN and to one coil input of the MMET 202. The second coil input of the MMET 202 is grounded. Whenever the memory cell 200 is not addressed, current is flowing in the coil of data input buffering MET device 70D, so that the HTS material strip 115 is in a resistive state. This resistive state is sufficient to limit any current to the coil of the MMET 202 to levels which will not change the state of the MMET 202. If, however, the memory cell 200 is addressed, there is insufficient current in the coil of the data input buffering MET device 70D to produce a resistive state and the signal on the data input line D_IN is provided to the coil of the MMET 202, thus allowing a state change to develop, if appropriate based on the data input current value. It is noted that after a given state is set in the magnet core of the MMET 202, no further drive signals are necessary to maintain the state.

The data output buffering MET device 70C functions in a similar fashion, but has its HTS material strip 115 connected to the data output line _ouτ and to one terminal of the HTS material strip 115 of the MMET 202. The other terminal of the HTS material strip 115 of the MMET 202 is grounded. When the memory cell 200 is not addressed, the data output buffering MET 70C provides a resistive path to ground, thus forming a one value. If the MMET 202 state is a one, then an even higher resistance is formed between the data output line ^Dou ^and ground. When the memory cell 200 is addressed, the resistance of the data output buffering MET 70C is zero, so that the resistance between the data output line D_QUT and ground is the resistance of the MMET 202, which in turn is based on the state of its magnet core. The one value of a non-addressed data output buffering MET device 70C is adequate because when a plurality of memory cells 200 are formed into a matrix and the outputs paralleled in a wired-AND configuration, if any memory cell 200 provides a zero value, the resistance to ground of the data output line D_ouτ is zero, allowing a determination of the memory cell 200 value. If the addressed memory cell 200 has a one value, the resistance to ground of the data output line D-_™, is greater than zero, different from the zero value, thus allowing discrimination.

If a large number of memory cells 200 are configured into a matrix, the combined parallel one state resistance of the memory cells 200 on the data output line D_oχJT may approach zero sufficiently to be detected as a zero value. This can be remedied by limiting the number of parallel cells or improving the data output value sense circuitry.

In an alternative embodiment of the basic MET cell, instead of using magnetic material having a low residual field, all of the cells can be developed using a high residual field magnetic material as used in the MMET device 202. Logic elements can thus be formed using pulses instead of continuous drives as in the conventional MET device 70 previously described. Pulses of current would be transmitted through the various gates to properly set or clear the magnetic states of the magnet core of the MMET devices 202. This technique could reduce the total power consumption of an integrated circuit developed using MET devices because continuous current requirements of the various devices would not be present, only those devices actually being pulsed drawing current. The effect is in many ways similar to a CMOS type device which draws current only when switching action is occurring. This pulse mode of operation would also ease fabrication of a memory cell in that the memory cell 200 which has both MET devices 70 and MMET devices 202 would be relatively difficult to fabricate in that several different of ferromagnetic materials would be required, thus increasing the number of masks and processing steps required.

While the above description relates to digital operation of MET devices, analog operation can also be developed using analog techniques and designs utilized in semiconductor devices, by utilizing the effect of varying HTS material resistance based on coil current and HTS material current in feedback or gain circuit configurations without reaching the levels associated with digital operation. Designs similar to those using FET's can be developed. The thin film magnet cores formed of magnetic material as used in the MMET device 202 can also be used to form a core memory 300 (Fig. 13). This core memory 300 is similar to conventional core memory that is well known except that highly miniaturized thin film magnet cores produced using the previously described techniques are used and HTS materials of proportional size are used. The core memory 300 has row X and column Y lines, as well as a sense line 302 and an inhibit line 304, if one is desired. In the core memory 300 the magnetization state of the magnet core is changed from positive to negative or negative to positive when a state change is made. A zero magnetization state is not utilized, which is different from the MMET device 202.

A state or value is written to a particular core 301, of which four are shown in Fig. 13, in the core memory 300 by providing one-half the current needed to change the magnet core state to each of the appropriate row X and column Y lines, so that the full current is present at the intersection, the desired core 301 in the core memory 300. Reading a particular location is performed by doing a read/write cycle to allow effective nondestructive readout of the value. A predetermined value is written to the desired core 301. If no current is developed in the sense line 302 then the state of the core 301 was the same as the predetermined value. If a current is developed on the sense line 302, then the core 301 has changed state and the location was not at the predetermined value. The proper value is then written to the location so that the state of the core 301 is unchanged from the beginning of the cycle. Conventional core memory principles and techniques are quite applicable to the core memory 300 and such variations and fabrications as apparent to those skilled in the art are encompassed in this invention.

A cross-section of the core 301 is shown in Figure 14. A fabrication can proceed in the following steps. The substrate 310 has an appropriate insulator 312 developed over it. Preferable thickness of the insulator depends upon the final dimensions of the device, but thicknesses from 200 to 2 microns are satisfactory. On this insulator layer 312 is deposited a lower magnet bar 314. Preferably, the magnet bar 314 is of sufficient thickness that it will conduct a sufficient magnetic field to properly retain its state under the operating environment of the final device. For example, the magnetic material 314 can be from 1000 & to several microns thick. An insulating layer 316 is applied over the entire surface and then planarized so that a level surface results. A next insulating layer 318 is then deposited evenly over the entire surface of the device so that an insulating layer having a thickness of several hundred to several thousand ft is developed. Alternately, the planarization of layer 316 could be stopped at a level such that this amount of insulating material is present over the magnetic material 314. On top of the insulating layer 318 are deposited two strips of HTS material 320 and 322. For example, the HTS material 320 and 322 could be the row X line appropriate for that particular core 301 and could be the sense line 302 of the core memory 300. The HTS material 320 and 322 is preferably 1 micron wide and from 1000 X to 1-micron thick. An insulating layer 324 is applied over the entire device and then planarized. A second insulating layer 326 can also be applied so that there is electrical separation between the HTS material 320 and 322 and further layers of HTS material which are to be applied. Again, alternately, a single thick layer of insulating material 324 can be applied and planarization stopped such that a layer of insulator over the HTS material 320 and 322 was present equivalent to layer 326. On top of insulating layer 326 are deposited two more strips 328 and 330 of HTS material. These HTS material strips 328 and 330 correspond to the other two conductors utilized in the core 301, in this example the column Y conductor and the inhibit line. Insulating layers 332 and 334 are then formed over the HTS material strips 328 and 330 with the final result being a planar insulating layer 334. In the structure which has been developed, two holes or cavities are etched into the various insulating layers so that the holes reach down through the insulating layers 318, 324, 326, 332, and 334 to the lower magnet bar 314. These -27-

holes will form the sides or columns of the magnet core which is the basis of the core 301. After these holes have been etched, magnetic material is deposited in the holes to form vertical portions 336 and 338 of the magnet core. After these vertical portions 336 and 338 have been developed, an upper magnet bar 340 formed of magnetic material is deposited on the upper surface. This final deposition of magnetic material 340 results in the forming of a core comprised of the lower magnet bar 314, vertical portions 336 and 338 and the upper bar 340. It is to be noted that the four HTS material conductors 320, 322, 328, and 330 are all located within the periphery of the core thus formed. The conductors 320, 322, 328 and 330 are shown in a two by two arrangement, but otlier arrangements can be utilized by varying the geometry of the magnet core.

Therefore, a miniaturized core memory analogous to those previously constructed on a macroscale in the prior art has been developed. An insulating layer 342 is developed over the surface and planarized if desired, with a final insulating layer 344 being developed over the entire circuit for protection. Alternatively, insulating layer 342 can be developed to be quite thick and thus form the same function as layer 344. Therefore, the magnetic core 301 is easily developed and quite simply done with planarization techniques that have been previously described and as are known to those in the art.

The foregoing disclosure and description of the invention are illustrative and explanatory thereof, and various changes in the size, shape, materials, components, circuit elements, wiring connections and contacts, as well as in the details of the illustrated circuitry and construction may be made without departing from the spirit of the invention.

SUBSTITUTESHEET

Claims

CLAIMS :

1. An electric circuit device, comprising: an insulator; a first conductor element formed of thin film superconducting material overlaying a portion of said insulator; and means for varying the resistance of said first superconductor element.

2. The device of claim 1, wherein said resistance varying means includes means for producing a magnetic field substantially perpendicular to the plane containing the surface of said first thin film superconductor element.

3. The device of claim 2, wherein said magnetic field producing means includes means for producing a variable magnetic field, the magnetic field being less than the upper critical field strength of said thin film superconducting material.

4. The device of claim 2, wherein said magnetic field producing means includes a second superconductor element formed of thin film superconducting material located overlaying a portion of said insulator.

5. The device of claim 4, wherein said second superconductor element is formed in a loop positioned so that the magnetic field produced by said loop under current carrying conditions is focused within the boundaries of said first thin film superconducting element.

6. The device of claim 4, wherein said magnetic field producing means further includes a magnet core. -29-

7. The device of claim 6, wherein said second superconducting element forms a loop around a portion of said magnet core.

8. The device of claim 7, wherein said magnet core is formed having a first end and a second end, said first and second ends being positioned adjacent one another and forming a gap therebetween.

9, The device of claim 8, wherein a portion of said first thin film superconducting element is located in said gap.

10. The device of claim 9, wherein said thin film superconducting elements and said magnet core are formed having a thickness of from about 500 Angstroms to about two microns.

11. The device of claim 9, wherein said magnetic core is formed of magnetic material having a low residual field in the absence of an electrical current.

12. The device of claim 9, wherein said magnetic core is formed of magnetic material having a high residual field in the absence of an electrical current after an electrical current has been applied.

13. The device of claim 4, wherein said magnetic field producing means further includes a means for concentrating magnetic flux lines.

14. The device of claim 13, wherein a portion of said first thin film superconducting element is located in the area of said concentrated flux lines.

15. The device of claim 1, wherein said first thin film superconducting element is a high temperature superconductor. -30-

16. The device of claim 1, wherein said insulator comprises a material selected from the group consisting of Zr0₂, MgO, SrTi0₃, Si0₂, Al₂0₃, LiNb0₃, NdGa0₃, LaGa0₃, KTa0₃, BaTi0₃, MgAl₂0₄.

17. The device of claim 1, further comprising: a substrate underlying said insulator.

18. The device of claim 17, wherein said substrate comprises polycrystalline material.

19. The device of claim 17, wherein said substrate comprises a monocrystalline semiconductor material.

20. An electric circuit, comprising: a substrate comprising monocrystalline semiconductor material; at least one electric circuit device comprising: an insulator overlaying a portion of said substrate; a first thin film superconducting element overlaying a portion of said insulator; and means for producing a magnetic field substantially perpendicular to the surface of said first thin film superconducting element; and at least one semiconductor device, wherein at least one semiconductor device is coupled to at least one electric circuit device.

21. The circuit of claim 20, wherein said magnetic field producing means produces a variable magnetic field, the magnetic field being less than the upper critical field strength of said thin film superconducting elements.

22. The circuit of claim 20, wherein said magnetic field producing means in said electric circuit device includes a second thin film superconducting element overlaying a portion of said insulator and forming a loop. -31-

23. The circuit of claim 22, wherein said loop is located so that the center of the magnetic field produced by said loop under current carrying conditions is focused within the boundaries of said first thin film superconducting element.

24. The circuit of claim 23, wherein said magnetic field producing means in said electric circuit device further includes a magnet core.

25. The circuit of claim 24, wherein said loop is formed so as to surround a portion of said magnet core.

26. The circuit of claim 25, wherein said magnet core is formed having a first end and a second end, said first end being positioned adjacent to said second end so as to form a gap therebetween.

27. The circuit of claim 26, wherein a portion of said first thin film superconducting element is located in said gap.

28. The device of claim 27, wherein said magnetic core is formed of magnetic material having a low residual field in the absence of an electrical current.

29. The device of claim 27, wherein said magnetic core is formed of magnetic material having a high residual field in the absence of an electrical current after an electrical current has been applied.

30. The circuit of claim 22, wherein said magnetic field producing means in said electric circuit device further includes a means for concentrating magnetic flux lines.

31. The circuit of claim 30, wherein a portion of said first thin film superconducting element is located in the area of said concentrated flux lines.

32. The circuit of claim 20, wherein said first thin film superconducting element is formed of a high temperature superconductor.

33. The circuit of claim 20, wherein said insulator comprises a material selected from the group consisting of Zr0₂, MgO, SrTi0₃, Si0₂, Al₂0₃, LiNb0₃, NdGa0₃, LaGa0₃, KTa0₃, BaTi0₃, MgAl₂0 .

34. The circuit of claim 20, wherein said semiconductor device and said electric circuit device are incorporated into a single integrated circuit.

35. An electric circuit, comprising: at least two electric circuit devices coupled together, each electric circuit device comprising: an insulator; a first thin film superconducting element overlaying a portion of said insulator; and means for varying the resistance of said first thin film superconducting element.

36. The circuit of claim 35, wherein said resistance varying means of said electric circuit device includes means for producing a magnetic field substantially perpendicular to the surface of said first thin film superconducting element.

37. The circuit of claim 36, wherein said electric circuit devices are coupled to form an AND gate.

38. The circuit of claim 36, wherein said electric circuit devices are coupled to form an OR gate. -33-

39. The circuit of claim 36, wherein said electric circuit devices are coupled to form an inverter.

40. The circuit of claim 36, wherein said electric circuit devices are coupled to form a memory cell.

41. The circuit of claim 36, wherein said electric circuit devices are coupled to form a flip-flop.

42. A method for constructing an electric circuit device on a base insulating layer, comprising: depositing a base strip of magnetic material over a portion of the base insulating layer, said base of magnetic material having a first and second end portions and a central portion; depositing a first layer of insulating material over said base of magnetic material; forming a strip and a loop of superconducting material, said loop including a portion located over said central portion of said base of magnetic material and said strip located over said first end portion of said base of magnetic material; depositing a second layer of insulating material over said superconducting material; removing a portion of said insulating layers to form a hole over said second end portion of said base magnetic material; and depositing a top strip of magnetic material having a first end positioned to adjoin said second end of said magnetic base and a second end overlaying a portion of said strip of superconducting material.

43. The method of claim 42, wherein said step of depositing a base of magnetic material includes the steps of depositing a magnetic material in an even layer and of removing a central portion of said even layer to produce elevated end portions.

44. The method of claim 42, wherein said step of depositing base magnetic material includes the steps of depositing a magnetic material in an even layer and depositing a magnetic material over the end portions of said even layer to form two elevated end portions.

45. The method of claim 42, further comprising: removing a portion of said second insulator layer to form a hole exposing a portion of said said strip of superconducting material before depositing said top strip of magnetic material and wherein said top strip of magnetic material is formed to adjoin said second end of said base magnetic material and extend to a point overlaying a portion of said strip of superconducting material.

46. The method of claim 42, further comprising: annealing said superconducting material after forming said strip and loop.

47. A method for constructing an electric circuit device on a base insulating layer, comprising: depositing a base strip of magnetic material over a portion of the base insulating layer, said base strip of magnetic material having a first and second end portions and a central portion; depositing a first layer of insulating material over said base of magnetic material; forming a strip and a loop of superconducting material, said loop including a portion located over said central portion of said base strip of magnetic material and said strip located over said first end portion of said base strip of magnetic material; depositing a second layer of insulating material over said superconducting material; removing a portion of said insulating layers to form holes over said first and said second end portions of said base strip magnetic material, said hole over said second end extending to said magnetic material base strip and said -35-

hole over said first end extending to a depth allowing a portion of said second insulating material layer to remain over said superconducting material strip, thus forming a gap; depositing magnetic material in said holes; and depositing a top strip of magnetic material having a first end positioned to adjoin said second end of said magnetic base and a second end overlaying a portion of said strip of superconducting material.

48. The method of claim 47, further comprising: annealing said superconducting material after forming said strip and loop.

49. A method for constructing an electric circuit device on an insulator, comprising: depositing a strip of superconducting material over the insulator; " depositing an insulator over said strip of superconducting material; and depositing a loop of superconducting material so that the center of said loop is positioned over said strip of superconducting material.

50. The method of claim 49, further comprising: annealing said superconducting material.

51. A method for constructing a magnet core, comprising: depositing a thin film of base magnetic material; developing first and second raised end portions of said magnetic material relative to a central portion; depositing a thin film insulator over said base magnetic material; forming a hole in said insulator over said first end portion of said base magnetic material; and depositing a second thin film of magnetic material extending from a point overlaying and adjoining said first end portion to a point overlaying said second end portion. -36-

52. The method of claim 51, further comprising: forming a hole in said insulator over said second end portion of said'base magnetic material before depositing said top magnetic material, so that said top magnetic material connects said end portions forming a closed loop magnet core.

53. A method of constructing a core memory, comprising: depositing a thin film of base magnetic material forming the bases of a plurality of. magnet cores; depositing a thin film insulator over said base magnetic material; depositing and annealing thin films of superconducting material forming row, column and sense lines of the core memory with one row, one column and one sense line being positioned in said central portion of each base; depositing a thin film insulator over each of said superconducting material thin films; forming holes in said insulators over said first and said second end portions of said base magnetic material of each base and extending to said base magnetic material; depositing magnetic material in said holes; and depositing a second thin film of magnetic material extending from a point overlaying and adjoining said first end portion to a point overlaying and adjoining said second portion.

54. A core memory, comprising: a plurality of thin film magnet cores having a substantially central opening and a closed magnetic flux path; a plurality of row lines, one row line associated with each magnet core and passing through said opening; a plurality of column lines, one column line associated with each magnet core and passing through said opening; and a sense line associated with each magnet core and passing through said opening, wherein said row lines, said column lines and said sense line are formed of high temperature superconducting • materials.

55. The core memory of claim 54, further comprising: an inhibit line associated with each magnet core and passing through said opening, said inhibit line being formed of high temperature superconducting material.