WO1990012389A1

WO1990012389A1 - Converter for raster-image data from single-segment to multi-segment streams

Info

Publication number: WO1990012389A1
Application number: PCT/US1990/001808
Authority: WO
Inventors: Suhas S. Patil
Original assignee: Cirrus Logic, Inc.
Priority date: 1989-04-04
Filing date: 1990-04-04
Publication date: 1990-10-18

Abstract

A system for converting raster-image data in sequential frames from a single stream to a plurality K of streams suitable for controlling images on a raster imaging surface having said plurality K of different segments (Upper segment, Lower segment) includes the generation of a stream of raster data SO (Single Stream Data) representing information to be on a portion of one of the segments, the plurality K including the raster data stream SO; the generation of an additional plurality K-1 of streams of raster data; the delaying (Δn/2 + Δn/2 + Δr) of each of said plurality K-1 of streams of raster data relative to the stream of raster data SO by different amounts which are functions of K and the number of lines (n) in a frame, and simultaneously supplying (gates 0, 1) one of the plurality of streams of raster data to each of the different segments of the imaging surface in the sequential order required to produce an image corresponding to SO on the imaging surface.

Description

CONVERTER FOR RASTER-IMAGE DATA FROM SINGLE-SEGMENT TO MULTI-SEGMENT STREAMS

BACKGROUND OF THE INVENTION Field of the Invention

This invention pertains to the field of raster image systems and relates more particularly to the field of raster image systems for driving display, hardcopy or other graphical output devices such as used for displaying photographs, printing, imaging or otherwise outputting as a two-dimensional image text, diagrams, graphs and pictures.

Prior Art

Many imaging devices, such as television or computer monitors that include cathode ray tubes (CRT's), receive as their input a single stream of raster data and display this raster-image data in a series of lines, which constitute a frame. On the other hand, some flat-panel displays, such as liquid crystal displays (LCD's), particularly the larger ones, are made of two segments, an upper segment and a lower segment, that operate in parallel and that require two parallel streams of data, one for each segment.

In the prior art, the task of generating two streams of data for use in flat-panel displays from the single stream of raster image data typically produced by controllers for CRT displays has been achieved using a frame buffer large enough to store the entire contents of one frame of data which was then read out as two streams of data. Examples of such prior art are chips for video- to-LCD conversion such as the SED 1341 F_QE and the SED 1345 F_0A, both from SMOS Systems, Inc. (Technical Manual SED 1341 F_0E, 1988 and Technical Manual SED 1345 F_QA, SMOS Systems, Inc., 2460 North First Street, San Jose, CA 95131). Both of these chips require a minimum of one bit of data for each pixel in the frame. For example, the chip SED 1341 F_QE requires 40K bytes of memory to work with 640 times 480 display (Page 38, the Technical Reference Manual SED 1341 F_QE) . An example of a suitable LCD for use in the invention is the model LM640487Z sold by the Elecom Group of the Sharp Corporation.

SUMMARY OF THE INVENTION

In the present invention for controlling a multiple- segment imaging device of K segments, at any given time one of the multiple segments receives the data to generate a raster image directly from a single-stream input, while the other one or more segments receive data from a partial frame buffer memory, whose contents are updated as the data in the memory is read out.

For example, in a two-segment case, during the period when the single-stream input is providing data for the first n/2 lines of an n-line image (constituting the top half of the image), the single stream of raster data directly drives the top half or top segment of the two-segment imaging device, while the lower half or lower segment of the raster imaging device receives its data from the half-frame buffer. During the second half of a frame period, the single-stream input provides raster data directly for the lower half or lower segment, while the top half or top segment receives its raster data from the half-frame buffer memory. The memory required is thus cut to a half frame of data, since at no time is it necessary to save more than a half frame of data, thereby reducing system cost. Furthermore, since new raster data replaces old raster data in an orderly sequence, it is possible to use a read-modify-write cycle of a dynamic random access memory, thereby enabling higher speeds of operation.

In the present invention, when driving a two-segment display, during each frame period of the single-stream input, the two-segment display goes through two frames of operation. Thus, the frame frequency for the two-segment display is twice that of the single-segment display. Frame frequency is an important display parameter: a higher frame frequency typically produces a higher quality display. The present invention thus provides twice the frame-frequency performance for a given data or clock rate.

Looked at from another point of view, for a given frame rate for the two-segment case of this invention, the single stream of raster data needs to be generated only at half the frame rate. Thus, the raster imaging device control subsystem generating the single stream of data can operate at half the clock rate of the imaging device. In some technologies such as CMOS, power consumption is a function of the frequency of operation. In such technologies, this invention results in a significant savings in the power consumption as most of the system can be operated at half the clock rate otherwise required. This is an important advantage in battery powered operations such as lap-top computers.

It is therefore an object of this invention to provide an improved converter for translating raster-image data to be imaged from a single-stream form to a multiple- stream form for use with imaging devices of two or more segments so as to cut down the memory requirement to less than the amount needed to store one frame of data (half the memory needed in the case K=2).

It is yet another object of this invention to take advantage of two or more segments of a raster imaging device in such a manner as to realize higher frame rates of operation and to reduce the requirement for electrical power of the system for a given frame rate of operation.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 illustrates the operation of the raster imaging system of the present invention;

Fig. 2 shows the flow of data in the present invention;

Fig. 3 illustrates the data flow time sequence of the raster imaging system in this invention;

10 Fig. 4 shows the present invention applied to an imaging system having four segments therein;

Fig. 5 illustrates one embodiment of the invention employing shift registers to provide the required delays;

Fig. 6 shows an alternate embodiment of the invention l*-* utilizing a static random access memory (SRAM) to implement the required delay;

Fig. 7 illustrates a further alternate embodiment of the present invention employing a dynamic random access memory (DRAM) to provide the requisite delay; and 20 Fig. 8 is a timing diagram illustrating the DRAM embodiment operating in a read modify write control operation in page mode.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Fig. 1 is a diagram showing, at an abstract level,

25 the basic operation of the invention. Fig. 1 depicts the operation during the ith frame of a single-segment image (such as a CRT display) and the operation of the two corresponding frames of a two-segment display. The operation of the i-l frame is also shown as it relates to

30 the ith frame of operation.

Fig. 1 shows at the top thereof a single-segment raster data for frame i, as well as for the previous frame i-l. The single-segment frames i and i-l are similar to those employed in controlling a CRT. Assume that each single-segment frame has n lines in it, and let the data associated with the first or top n/2 lines be identified as ϋi (for upper), and let the data that drives the lower n/2 lines be identified as Li (for lower). Further, as shown in the lower portion of Fig. 1, let the two corresponding frames of the two-segment display be called 2i, and 2i+l, respectively.

In the 2ith frame of operation, the upper segment thereof receives the Ui raster data directly from the single-stream input without being stored, as indicated by the line from the upper half Ui of the single-segment frame i to the upper segment of the double-segment frame 2i. During the same time period, the lower segment of double-segment frame 2i receives raster data (in parallel with the upper segment) from the previous single segment frame i-l, after being suitably delayed. This delay is half the frame time (^Δ _n/2) Pl^us» -ⁿ general, an additional delay Δ_r (which may be zero) for vertical retrace time. Thus, the first n/2 lines are fed directly by Ui, and the lower n/2 lines are fed in parallel therewith through the delay Δ_n/₂ ^{+ Δ} _r-

For the next double-segment frame, 2i+ 1, the lower segment thereof is fed directly from the single-stream raster data represented by the lower half Li of single frame segment i, as indicated by the directional line connecting the two, while the upper segment of frame 2i + 1 is supplied through the delay Δ_n 2* ^Tne invention continues to alternately supply the first n/2 lines of raster to the top half of a double segment frame and supply the second set of n/2 lines of raster to the lower half of the double segment frame, and vice versa.

The diagram of Fig. 2 shows the flow of raster data in the invention at an abstract level, illustrating the division of the single-stream raster data so that one half of this stream is alternately supplied to one half of the double-segment frame directly, while the other half is supplied to the lower half through delays Δ_n /₂ + ^Δ _r or ^Δn/2^{r as} appropriate. Fig. 3 shows another view of the operation of the invention where the flow of data is shown in a time sequence.

This invention can be used with an image rendering device of any number of segments. When used with a K- segment device, the invention provides K times speed up in frame rate compared to a single-segment device driven by the single-stream data. Fig. 4 shows the application of this inrvention with a multiple-segment raster imaging device involving four segments S0-S3. The delaying of I»_i_₁ by Δ_n/2 + Δ_r to feed the lower segment in frame 2i and the delaying of U^ by Δ_n/2 to feed the upper segment in frame 2i+l can be done using various forms of memory such as a shift register, a static RAM (SRAM) or a dynamic RAM (DRAM). Fig. 5 shows one embodiment of the invention using a shift register for the delay element. In this illustration the single stream of raster data is one bit wide and corresponds to a format for a digital monochrome monitor. The desired output is for a two-segment display that requires: (i) 4-bit wide raster data for each segment, (ii) a shift clock to indicate when the raster data is to be picked up, (iii) a line clock to indicate the end of a line and (iv) a frame start pulse to indicate the beginning of a frame. The Pixel Clock signal marks the time when the raster data on input line Display Data is to be read. The data on the the Display Data line is to be used for display purposes only when Display Enable signal is true, thus implementing the delay Δ_r. V Sync is a synchronizing signal having a duration of one or more lines and marks the beginning of a frame. H Sync is a synchronizing signal that marks the end of a line.

Shift Register SRdelay acts as a delay device. It has n/2 times m stages, where m is the number of pixels in one line (as defined by the Display Enable signal) . AND gate gl allows the Pixel Clock signal to go through only when the input Display Enable is true. Counter Cl counts the number of lines starting from the end of V Sync. The Arithmetic Comparator produces a signal Lower Half that is true when the value of the counter Cl is equal to or greater than n/2, indicating that the lines correspond to the lower half of the display, and a signal c=n/2 which is true when the value of the counter Cl is equal to n/2.

The Lower Half signal is a control signal to the two selectors SL and SU. When Lower Half signal is a 0, SU sends Display Data signal directly to shift register SRU which is associated with the upper segment, and SL sends delayed data to the shift register SRL which is associated with the lower segment. When Lower Half signal is a 1, the selection is reversed and SRU gets the delayed data and SRL gets data directly from Display Data.

SRL and SRU are 4-bit shift registers each and are used to assemble 4 pixels of data for transfer to output registers RU and RL, both of which are 4-bit registers. C2 is a 2-bit counter that divides the clock by 4 to provide a clock signal to RU and RL and to the two-segment display unit.

The Line Clock signal is the same as the H Sync signal. Because two frames of double-segment display are generated in one frame period of the single frame display, two frame start pulses are produced in the period from one V Sync to the next V Sync. The first pulse is generated using flip-flops Dl and D2 and an AND gate g2 which produces a pulse during the first line after the V Sync. The second pulse is produced during the line when the counter Cl equals n/2 designating the first line of the second frame of the two-segment display.

Although the embodiment of Fig. 5 was described as embodying 4-bit-wide raster data for the segments, it will be obvious to those skilled in the art that numbers of bits other than 4 may be employed in the invention.

Fig. 6 shows an embodiment using a static RAM for the delay device. A SRAM of 4X160X240 is shown in Fig. 6, but larger configurations may be employed if desired. The input and output configurations for static RAM come in many forms. The static RAM used in the embodiment of Fig. 6 has separate input and output ports.

In this embodiment, the RAM performs the function of a first-in-first-out delay device such as was performed by the shift register SRdelay in Fig. 5. To compensate for the fact that RAM's are generally slower than shift registers, a RAM that is 4 bits wide is used so that 4- pixels of raster data can be handled in one cycle of RAM operation. The task of providing the RAM with 4-bit data is performed by shift register SR which takes in 4 bits of raster data serially from the SERIAL DATA input and sends out 4 bits in parallel. This 4-bit parallel raster data is stored in register Rl to serve as input data to the SRAM memory. The Address Counter and Control Logic block Bl is very similar to the control logic of Fig. 5. It contains two counters; one counts the lines and the other counts the position of the pixels in multiples of 4. The line counter output functions as the Row Address and the pixel position counter output provides the Column Address.

Lower Half and other control signals are generated in the same manner as they are generated in Fig. 5. Because the data path is 4-bits wide, the selectors Su and SI are 4- bits wide and there is no need for the shift registers SRu and SRI of Fig. 5. Fig. 7 shows an embodiment using dynamic RAM (DRAM). The interface to the DRAM is different compared to the static RAM of Fig. 6 in two respects. The first difference is that the input and output data flows on the same set of wires with the control signal oe determining the direction of the data flow. The second difference is that the row and column addresses are supplied on the same set of wires. The RAS and CAS control line indicate which address is provided. The function of the control block Bl in Fig. 7 is modified to meet the requirements of the DRAM. A timing diagram of the signals that the control block Bl must generate is shown in Fig. 8. For best performance the fast page mode of DRAM operation is used. As such, Row Address (representing the line count) is presented at the beginning as indicated by RAS going low which is held low to indicate page mode operation. Col Address (representing pixel position within a line divided by 4) is presented once every 4 pixels and is latched into the DRAM by the falling edge of CAS . Data Out controls a 4- side tristate buffer internal to block Bl that determines when data is to be fed to the memory, oe determines when the data is received and sent out by the DRAM memory. The operation of the DRAM corresponds to what is commonly called page mode read modify write operation.

Claims

CLAIMSI claim:

1. A system for converting raster-image data in sequential frames from a single stream to a plurality K of streams suitable for controlling images on a raster imaging surface having said plurality K of different segments therein; said imaging surface being responsive to signals representing characteristics such as color or

10 intensity of pixels to produce raster images in the portions of said segments receiving said signals, said images in said segments within a frame being produced by a raster image-producing means in a plurality n of sequentially produced lines in said -¹-⁵ imaging surface, each said imaging surface having a vertical retrace time r, which may be equal to zero; said retrace time r representing the time for said image- producing means to return from the end of one of said ²⁰ frames to the beginning of the next one of said frames; said system comprising: means for generating a stream of raster data SO representing information to be imaged on a portion of one of said segments of said imaging surface; said ²⁵ plurality of streams K including said raster data stream SO; means for generating an additional plurality K-l of streams of raster data; means for delaying each of said plurality K-l of 30 streams of raster data relative to said stream of raster data SO by different amounts which are a function of the delay Δ_n/_K; and means for simultaneously supplying one of said plurality of streams of raster data to each of said different segments of said imaging surface in the sequential order required to produce an image corresponding to SO on said imaging surface.

2. A conversion system in accordance with Claim 1 including means for delaying some of said K-l streams of data by an amount which is a function of Δ_r of said vertical retrace time r.

3. A conversion system in accordance with Claim 2 including gating means connected to receive different combinations of said K streams of raster data; and means for supplying the outputs of said gating means to different segments of said image-producing means.

4. A conversion system in accordance with Claim 1 in which K is two.

5. A conversion system in accordance with Claim 1, 2 or 3 in which said segments are of equal size.

6. A display system in accordance with Claims 1, 2 or 3 in which said delaying means includes dynamic random access memory means.

7. A display system in accordance with Claim 1, 2 or 3 in which said delaying means includes shift register means.

8. A display system in accordance with Claims 1, 2 or 3 in which said delaying means includes static random access memory means.

9. A system for converting raster-image data in sequential frames from a single stream to two streams suitable for controlling a display or other raster imaging surface or surfaces having first and second segments, said segments appearing in two frames for each frame of said single stream; said imaging surface being responsive to signals representing characteristics, such as color or intensity of pixels, to produce images in the portions of said segments receiving said signals, said images in each of said segments within a frame being produced by an image-producing meanns in a plurality n of sequentially produced lines on said imaging surface, each said raster imaging surface having a vertical retrace time r which may be equal to zero or greater; said retrace time representing the time for said image-producing means to return from the end of one of said frames to the beginning of the next of said frames; said system comprising: means for generating a stream of raster data SO representing information to be imaged on said imaging surface; means for generating a second stream of raster data SI; means for delaying some of said second stream of bits SI stream relative to said stream SO by an amount which is a function of _n 2; and means for simultaneously supplying said streams SO and SI to each of said pair of segments of each of said two frames of said imaging surface during said single stream frame as required to produce an image on said imaging surface.

10. A conversion system in accordance with Claim 9 including means for delaying some of said second stream of data SI relative to said data stream SO by an amount which is a function of Δ_r.

11. A conversion system in accordance with Claim 9 including means for delaying said second stream of data SI relative to said data stream SO by an amount which is a function Δ_{n 2} and ^Δr-

12. A conversion system in accordance with Claim 9 including means for supplying said data streams SO and SI to said first and said second segments, respectively, in a first one of said two frames during said single frame of said single stream; and means for supplying said data streams SO and SI to said second and said first segments, respectively, during in the second one of said frames during said single frame of said single stream.

13. A conversion system in accordance with Claim 1 including means for delaying some of said K-l streams of data by an amount which is a function of Δ_{n κ}.