WO1990009634A1

WO1990009634A1 - Fault masking in semiconductor memories

Info

Publication number: WO1990009634A1
Application number: PCT/GB1990/000228
Authority: WO
Inventors: Stephen Charles Olday; Gordon Blair Neish
Original assignee: Anamartic Limited
Priority date: 1989-02-13
Filing date: 1990-02-13
Publication date: 1990-08-23
Also published as: GB8903180D0; EP0457819A1

Abstract

A random access memory device with a memory addressable by row and column is addressed by a source of binary addresses defining a linear address space via row and column decoders responsive to respective groups of bits from the address source to address individual rows and columns respectively of the memory. The bits are permuted between the address source and the decoders so that at least the higher order bits from the address source are applied to row and column decoders alternately. The memory is thus accessed in rectangular blocks, called tiles, which, by virtue of the interleaving of bits are arranged in a tiling pattern shifting alternately in the row direction and the column direction.

Description

FAULT MASKING IN SEMICONDUCTOR MEMORIES

This invention relates generally to semiconductor random access memory arrays and particularly to a novel technique and circuitry that enable the use of memory devices which have defective bit locations.

In years gone by, a chip with a few or even only one, defective bit locations was unusable. Techniques have been developed to enable at least part of the non-defective areas on these defective chips or "partials" to be used but these have resulted in longer access times to the chips and/or there being non-defective areas of the chips which can still not be used. Moreover, the known techniques very often rely upon testing to locate faulty locations and then processing the chip to replace these locations by hardwired spare locations. This requires every chip to go through an individual manufacturing step involving laser cutting fusible links, for example, and is therefore costly to implement.

In GB-A 2184268 a technique is described which enables faulty bits in a serially accessed RAM to be masked out, without any need for hardware processing of the RAM. The circuitry embodying this technique is shown in Figure 1 of the accompanying drawings.

The RAM 2 is addressed by a free-running address counter 4 clocked by clock pulses WCK. A fault masking circuit 6 enables faulty cells in the RAM to be masked out. Data specific to the RAM 2 causes the clock pulses WCK to be selectively gated for providing bit rate clock pulses GCK to a serial-parallel convertor 8. These pulses are divided down to produce pulses BCK at word rate. GCK pulses are masked out by the circuit 6 at times when the counter 4 is addressing faulty cells. This enables a computer 10 to read/write data from the RAM 2 via the serial/parallel convertor when enabled by the outputs GCK and BCK provided by the fault masking circuit 6.

The above arrangement has been found to be particularly useful in a wafer scale integrated (WSI) circuit comprising a large number of undiced RAM chips, some of which inevitably have defective areas. Only one fault masking circuit is needed, with tabulated data, to mask out the faulty areas on all the chips.

The main problem with the above technique is the fact that, even when faulty areas of the memory are encountered in read/write operations, the address counter continues to be incremented at a uniform rate and, until it reaches the next usable area of the memory, no data transfer will take place. This increases the time needed for a data transfer to take place and requires careful management of the read and write data streams to skip over the "holes" which occur in the read data stream or which must be left in the write data stream when the counter is clocking past faulty areas.

In EP-A 0108578 an arrangement for addressing a memory array in square blocks is described. This is achieved by interchanging the most significant column addresses with the least significant row addresses. This causes the memory to be addressed in square blocks of N bits (e.g. I k bits ) such that a free running address counter could address a row of square blocks, block by block and traversing all the columns of the memory before addressing the succeeding row of square blocks. If larger blocks of memory were to be required the blocks would have to be addressed in groups but successive addresses from the address counter would address long, thin rectangular blocks of the memory. Faulty memory locations in the blocks are substituted with a location from a smaller memory block used only when a fault is detected, which is a technique essentially the same as the hardwiring technique discussed above.

One object of the present invention is to provide a technique for configuring and accessing a memory such that faulty areas of the memory are never addressed when the memory is accessed.

Another object is to allow the memory to be addressed in blocks of varying block sizes, namely a basic, minimum block size and larger block sizes which are multiples by a power of two of the basic size but which all present a block-like aspect ratio.

The invention is defined in the appended claims to which reference should now be made. It should however be noted that, in accordance with the invention at least the higher order bits from an address source are applied to row and column address decoders alternately, which is in no way suggested in EP-A 108578. Moreover the present invention utilizes a totally different technique for avoiding defective memory, as will be fully explained below.

In the preferred embodiment only the higher order bits are alternated. These alternated bits cause the memory to be accessed in a series of rectangular blocks referred to as "tiles". The un-permuted lower order bits access the locations within a tile row by row as in conventionally accessed memory chips. However the alternation of the higher order bits leads to a different pattern of accessing the tiles.

The basic unit of this pattern is a block of four tiles lying in two rows, designated row A and row B and two columns designated column C and column D. The four tiles may be arrayed in the following basic pattern unit: TILE 0 Row A Column C

TILE 1 Row B Column C

TILE 2 Row A Column D

TILE 3 Row B Column D or in the following basic pattern unit:

TILE 0 Row A Column C

TILE 1 Row A Column D

TILE 2 Row B Column C

TILE 3 Row B Column D

What is more the basic pattern unit repeats at larger scales. Thus the first sixteen tiles are composed of four super-tiles. Each super-tile is a basic, four tile unit as above. The four super-tiles are arrayed in the same way as the four tiles of the one super-tile.

The tiles may be identified by physical addresses which are most conveniently the addresses of the first memory location within the tile - the "top left-hand corner" address. In accordance with an important aspect of the invention all accesses to the memory are made on a tile basis and a look-up table converts logical tile addresses to physical tile addresses. What is more physical addresses of defective tiles are not used in this table so that defective tiles are simply not accessed. The address source sees a linear tile address space and is completely unaware that the physical tile addresses occur in a different order; the association may indeed be entirely arbitrary. For convenience in defining the invention, specific reference is made to "rows" and columns" to designate the two coordinate directions of a memory array. However, these two terms may equally well be interchanged.

The invention will now be described in more detail by way of example, with reference to the drawings in which:

Figure 1 is the prior art arrangement of GB-A 2184268 described above;

Figure 2 shows schematically the known addressing system for a typical 1M bit Dynamic random access memory (DRAM) ;

Figure 3 shows a portion of a conventional memory map addressed by the system of Figure 2.

Figure 4 shows schematically the modification to the

addressing used in an embodiment of the present invention;

Figure 4a shows some of the conventions of Figure 4 in more detail;

Figure 5 shows a map of a portion of a DRAM addressed by the system of Figure 4;

Figure 5a shows the same map for the case of 8-bit tiles;

Figure 6 is a block diagram of a wafer scale integrated circuit which uses the invention; and

Figure 7 shows schematically one particular type of addressing sequence embodying the invention. The addressing system of Figure 2 is used in a 1M bit DRAM organised as a 1024 × 1024 bit array having a total of 1,048,576 addressable bits. A linear counter 12 supplies 20-bit words (B₀-B₁₉) to an address register 14 which is coupled to the inputs of a column decode register 16 and a row decode register 18. Bits B₀-B₉ load addresses A₀-A₉ and bits B₁₀-B₁₉ load addresses A₁₀-A₁₉.

The column and row decode registers 16,18 provide the row and column addresses for every bit on the chip via outputs

C₀-C₁₀₂₃ and R₀-R₁₀₂₃ respectively. Thus, when the linear counter 2 is clocked from the all O's state through to the all 1's state incrementing by the LSB, the bit addressed on the chip will be scanned from address (C₀,R₀) to address (C₁₀₂₃ R₁₀₂₃) sequentially, with the row address R_n incrementing to R_n+1 after every column address C₁₀₂₃ on row R_n has been scanned.

Figure 3 shows a portion of the memory map of the DRAM addressed as described above. Each square represents 1 memory bit and the numbers in each square correspond to the position of that bit in the scanning sequence. Thus it can be seen that the bits on the chip are addressed row by row. This type of adressing of the DRAM is used in the prior art arrangement of Figure 1 (GB-A 2 184268).

An addressing system embodying the present invention is shown in Figure 4. The addresses are still supplied serially by the linear counter 12 to the system address register 14. However, the bits B₀-B₁₉, of which bits B₀-B₉ usually define a column address and B₁₀-B₁₉ define a row address, are interleaved in the system address register by virtue of a pattern of crossing connections 13 between the counter 12 and the address register 14. In the example shown the interleaving takes the following form.

The linear counter supplies bits B₀-B₁₉ as in Figure 2 but the bits are loaded into the address register 12 as alternate column and row addresses. Thus all the even bits from B₀ to B₁₈ define the column addresses and all the odd bits from B₁ to B₁₉ define the row addresses.

It will be appreciated that this interleaving of addresses does not lead to the row by row scanning achieved with the arrangement of Figure 2 when the counter is clocked through from all 0's to all 1's by incrementing the LSB.

To explain what does in fact occur, Bits B₀-B₉ should first be considered. In the Figure 2 arrangement clocking B₀-B₉ from all O's to all 1's with B₁₀-B₁₉ in the O's state, scans along the first row of the memory. Then 1 bit is added to the LSB of B₁₀-B₁₉ and the next row is scanned.

Now consider what happens when we use the same linear counting sequence with the Figure 4 arrangement. B₀, B₂, B₄, B₆ and B₈ are the first five column address inputs (A₀-A₉) whilst B₁, B₃, B₅, B₇ and B₉ are the first five row address inputs (A₁₀-A₁₄). Incrementing the LSB (B₀) will result in the column and row addresses skipping between rows and columns in terms of the physical position of an addressed bit on the DRAM.

A portion of the DRAM showing the order in which the bits are addressed is shown in Figure 5. It can be seen that the position of the addressed bit starts at (C₀,R₀) for the all O's state of the input address B₀-B₁₉. The sequence of the bits addressed for the following 16 input words is shown below reading down the two columns in turn.

SUBSTITUTE SHEET C₁, R₀ C₁, R₂

C₀, R₁ C₀, R₃

C1, R₁ C₁, R₃

C₂, R₀ C_2, R₂

C₃, R₀ C_3, R₂

C₂, R₁ C₂, R₃

C₃, R₁ C₃, R4

C₀, R₂ C₄, R₀

Thus it can be seen that a sequence of addresses from the counter of length 2ⁿ will define a rectangular patch or block of addressed bits on the DRAM. This basic patch or block is referred to as a tile. The basic tile size is 1 bit. The second tile size consists of pairs of adjacent bits in the same row. The third tile size consists of squares of four bits lying in two adjacent columns and two adjacent rows. The fourth tile size consists of rectangles of eight bits lying in four adjacent bits of each of two adjacent rows. It can be seen that from a small basic tile size larger tiles can be grown through a sequence of reasonably square tiles. In this particular arrangement, all the tiles have aspect ratios of 1:1 or 1:2. As will become apparent below, it can be convenient to consider the RAM as formed of larger tiles and to alter, the way in which the address bits are permuted so as to make the basic the size much larger that 1 bit.

In any event the input address, as supplied by the counter 12 can be treated as partitioned into a first plurality P of most significant bits representing a tile address and a second plurality Q of bits, namely the remaining bits, which represent the address within a tile. Regardless of the sizes of P and Q (which must of course add up to whatever is the total number of address bits furnished by the counter 12) the following results are obtained:

(1) Within a tile, sequential input addresses scan locations within the tile.

(2) Tiles are scanned in the order of Fig. 5, taking the numbers in the squares in Fig 5 to represent physical tile numbers.

(3) The aspect ratios of all possible tile sizes alternate between the aspect ratios of the basic tile, e.g. the aspect ratio of tile 0, and the aspect ratio of two side-by-side basic tiles, e.g. a tile composed of basic tile O plus basic tile 1.

When the DRAM is tested tile-by-tile using the interleaved addresses the location of all the faulty tiles in the chip can be determined. Either the number or the start address of. each perfect tile can be stored as a look-up table in an EPROM along with the tile size for that chip. Tiles are numbered physically in the order in which they are addressed by the linear counter 12.

As an example of tiles larger than 1 bit, Figure 5a corresponds to Figure 5 but shows 8-bit (byte) tiles instead of individual bits. In this example Q = 3, i.e. two column bits plus one row bit per tile giving a tile size of 2² × 2¹ bits = 4×2 = 8 bits. P = 12 - Q where R is the total number of input address bits.

Thus when the chip is addressed by a computer the linear counter 12 is pre-loaded with the start address of the first usable tile which is derived' from the data stored in the EPROM and the counter is linearly incremented to address all the bits in that tile as determined by the tile size. When that tile has been addressed the start address of the next usable tile is provided and that tile addressed. This continues until the data transfer is complete. For the purposes of the present invention it is sufficient to know that the counter 12 (Figure 4) is preloaded with the tile start address; accordingly Figure 4 shows a load address circuit 11 for performing this function. Preloading counters is already well known in the art.

The tile numbering employed in Figs. 5 and 5a is the physical numbering arising from the way in which the input address bits are permuted. It should be appreciated however that, if physical tile start addresses are stored in an EPROM (or in any form of look up table) the assignment of physical tile addresses can be completely arbitrary. Three examples can be given. It is assumed for simplicity that there are only eight physical tiles arrayed as are TILE O to TILE 7 in Fig. 5a.

Assume firstly that all tiles are perfect. It would then be possible for logical tile addresses to be identical to the physical tile addresses, TILE O(L) = TILE O(P), etc. where (L) and (P) symbolise logical and physical respectively.

Assume secondly that. TILE 1 (P) and THE 5 (P) are defective. The only logical tiles which can exist are TILE 0 (L) to TILE 5 (L), i.e. six perfect tiles. It would be possible to assign the physical tiles sequentially to the logical tiles but skip over the defective physical tiles. This leads to the following:

TILE O (L) = TILE O (P)

TILE 1 (L) = TILE 2 (P) TILE 2 (L) = TILE 3 (P)

TILE 3 (L) = TILE 4 (P)

TILE 4 (L) = TILE 6 (P)

TILE 5 (L) = TILE 7 (P)

The look up table is addressed by the logical tile addresses and outputs the physical tile addresses.

Finally in both the above cases an arbitrary association rather than an ordered association may be adopted. For example, with the same assumption as in case two above, it would be perfectly possible to set up say the following:-

TILE 0 (L) = TILE 3 (P)

TILE 1 (L) = TI1E 2 (P)

TILE 2 (L) = TILE 7 (P)

TILE 3 (L) = TILE 0 (P)

TILE 4 (L) = TILE 6 (P)

TILE 5 (L) = TILE 4 (P)

The host making use of the memory does not have to know anything about this association. It simply addresses perfect tiles by their logical addresses and the system goes to the correct physical tiles via the look up table. The look up table may be referred to as a memory tile map.

Since data relating to defective physical tiles is not stored in the look up table these are never addressed and there is no time wasted clocking through these addresses, as would be the case using the addressing system of GB-A 2,184,268. Any combination of defective tiles on a chip can be masked out by this method.

The computer provides the same sequence of logical addresses as it would to a normal DRAM but the physical location on the DRAM of the addressed bits does not follow the same sequence. Thus, to the user, the DRAM appears to be the same as a normal DRAM save that, if it has defective areas, it will be smaller than a perfect DRAM. Regardless of RAM size (chip scale, wafer scale, sub-wafer scale) the physical RAM will be made large enough to permit it to function as a RAM of a standard logical size, so long as the incidence of defects lies within an acceptable range.

If all address bits are interleaved in accordance with Fig. 4a, the smallest usable tile size is a function of the amount of memory allocated to the memory tile map. The fault mask resolution is by definition the same size as the tile size and thus subject to the same limits regarding its size.

As already explained, a memory address is composed of a P-bit tile address and a Q-bit address within the tile. If all address bits are interleaved, Q can be made as small as described, e.g. Q = 3 in the example of Fig. 5a. However it is possible to interleave only the more significant bits, in which case the non-interleaved bits set an absolute minimum limit on Q. An example will be fully described below with reference to Fig. 7. For the moment it will merely be pointed out that, if the Q in-tile address bits are not interleaved, locations within a tile are sequentially addressed row by row whereas, if the Q in-tile address bits are interleaved, locations within a tile are sequentially addressed in a tiling pattern order like that illustrated in Fig 5.

The described fault masking technique is particularly useful in wafer scale integrated (WSI) curcuits having a plurality of undiced chip areas. Preferably the wafer is manufactured with an EPROM on it which can be used to store the memory tile map. and a tile size for the wafer, along with other data needed to access the wafer. A wafer control circuit uses the EPROM when accessing the wafer. A block diagram of such a circuit is shown in Figure 6.

The circuit comprises a wafer module 20 with a plurality of undiced memory chip areas 22 on it. The wafer also has an EPROM 24 in which is stored data needed to operate the wafer 20 - the Wafer Data Table (WDT) - including the memory tile map and the tile size for the wafer. The memory tile map stored in the EPROM 24 will contain data relating to a chip address and a tile address for each usable tile on the wafer. These are used to determine the position of the chip in the wafer using a spiral path list also stored in the EPROM and this gives the displacement in clock cycles of the chip from the bondsite on the wafer. The start address of the tile can then be used to allow access to that tile.

The way in which the spiral path is determined and specific chips 22 are accessed are as decribed in GB-A 2,177,825 as are the treatment of the signals shown. These are XMIT, which is the serial data path into the module 20; RECV, which is the serial data path out of the module; WCK, which is the wafer clock signal distributed to every chip; and CMND, which is a global command line applied to every chip. A chip 22 is addressed by launching a "token" bit on XMIT, clocking it through the chips (1-bit latency per chip), and asserting CMND when the token is in the target chip. The nature of the command then carried out is determined by the duration of CMND.

In use, the memory tile map portion of the WDT will be downloaded to a RAM 26 via an interface unit 28. From this RAM it can be readily accessed by a wafer control unit 30 which is instructed by a host computer via an interface bus 32 to perform read or write accesses to the wafer, or to page the memory on the wafer. The RAM 26 is connected to the wafer control unit 30 via bus 34. The wafer control unit 30 effects the low level control over the passage of signals to and from the module 20 and includes a serial-parallel converter for converting between the bit-serial format on XMIT and RECV and the bit-parallel format on the bus 32, as in GB-A 2184268. The unit 30 has an associated buffer 36 to allow it to perform speed buffering between the module 20 and the host computer in a well known manner. High level control, specifically management of the addresses which are accessed, is performed by a control CPU 38 connected to the bus 34, with an associated program ROM 40 and working memory 42.

The linear address counter 12 (Fig.4)of a chip 22 is the source of addresses to that chip on the wafer and can be preloaded to start: data transfers from a particular address. This preloading is achieved by configuring the counter 12 as a shift register and serially loading the required start address into the counter in accordance with data provided by the memory tile map. The details of how this is done do not form part of the subject matter of the present invention; rather they are the subject of a co-pending British Patent Application 89 03181.9 filed on the priority date of the present application, i.e. 13 February 1989, and of other patent applications claiming priority from the cited British Application. Briefly the technique is as follows.

The command set of GB-A 2 177 825 is extended to include commands ACLOAD, ACONE, ACZERO and STSP. ACLOAD, (address counter load) sets the counter 12 into its shift register mode. Thereafter a succession of ACONE (address conter one) and ACZERO (address counter zero) commands shift 1 and 0 bits respectively into the counter 12 until it has been filled with the required start address. ACLOAD can then be cleared with another command CLR-FUN (clear function), and either the READ or WRITE command asserted to allow data to be read from the RAM via RECV or written to the RAM via ZMIT, essentially as in GB-A 2 177 825. However the counter 12 can be started and stopped by STSP, which is a toggle cammand, to control the read or write operation. The counter 12 is separate from a refresh counter which runs continuously.

When the counter 12 is toggled on by STSP it is clocked by WCK and supplies the required addresses. The outputs of the counter are connected to the inputs of the address register 14 in an arrangement which gives the required interleaving. By way of example Figure 4a shows the counter 12 with all its stages X₀ - X₁₉ and selected connections from these stages to the stages of the register 14. The required pattern of connections 13 can be provided by two metal layers in the integrated circuit structure of the chip 22.

RAM chips are typically supplied by manufacturers with a degree of scrambling of the physical order of the columns and/or rows addressed in sequence by the column and/or row decode registers 18. This is done for manufacturing convenience and has no effect on the conventional linear sequence of addresses supplied by the address register. However, when the fault masking technique described here is used, the manufacturer's scrambling has to be known and descrambled before a tile structure can be imposed on the RAM by further scrambling between the address counter 12 and the address register 14.

This is desirable since defects on chips normally affect a group of physically adjacent bits on the RAM. Therefore, if a tile structure were imposed without knowledge of the manufacturer's scrambling, a linear sequence of addresses would access bits jumping between different areas of the RAM and a defect could affect a large number of tiles.

If the manufacturers scrambling is known and taken account of when the tile structure is imposed, tiles can be arranged to consist of physically contiguous areas of the RAM. This will reduce the number of tiles that are unusable when a defect occurs since the defect may fall wholly within a tile or at worst will cross a few tile boundaries making those tiles unusuable. The required permutation of address bit is accordingly the convolution of a de-scrambling permutation (if needed) and a tiling permutation. Only the tiling permutation is described herein. The de-scrambling permutation can readily be derived from the manufacturer's data on the chip structure.

The aspect ratios of tiles are preferably kept reasonably square to minimise the number of tiles affected by faults. In the embodiment described above the aspect ratios of tiles are either 1:1 or 1:2.

For memory managment purposes, the complete memory can be accessed in blocks, the size of which is determined by the user, each block consisting of a number of data frames. A data frame is the smallest unit of data which can be transferred to or from a chip and a tile will typically consist of a plurality of data frames.

Thus, when a block of memory is addressed, the address must first be generated as an absolute logical frame address within the memory system. This is then converted to provide an absolute logical tile address within the memory system along with a physical frame address. Using data from the memory tile map this then provides a physical tile address on a chip, and a logical chip address. The logical chip address is used as a pointer into a spiral path list which holds the addresses of all the chips in use in a wafer or a wafer stock and uses this to provide a physical wafer address and a physical chip address, as in GB-A 2,177,825. The physical wafer address, physical chip address, physical tile address, and physical frame address then define the exact location from which a memory transfer must commence. The address counter 12 on the addressed chip is preloaded with the address of the location at which data transfer is to commence using the physical tile address and the physical frame address.

For example, a 1024 × 1024 bit DRAM on a single wafer memory 20 may be configured as 128 tiles, each having a size of 64 columns by 128 rows (8192 bits) and a data frame comprises one row of a tile i.e. 64 bits. The interleaving of addresses is so arranged that each tile is scanned one row at a time (one frame at a time).

Thus, the 7 MSB's loaded into the address counter 12 define the tile address, the next 7 bits the frame address in that tile, and the 5 LSB's the column addresses of the frame. Linearly incrementing the LSB of the address counter will then scan the addressed tile row by row until the end of the tile is encountered. If the required data transfer is not complete then the next logical tile address derived from the memory tile map must be used to provide a fresh physical chip address on the wafer and the next physical tile address and frame address to preload the address counter on the addressed chip. The interleaving which would achieve this particular addressing sequence is shown in Figure 7. In Fig. 7 X₀ to X₁₂ are not interleaved. Rather X₀ to X₅ provide the six least significant bits of the column address and X₆ to X₁₂ provide the seven least significant bits of the row address. However, X₁₃ to X₁₉ are assigned alternately to the column address and the row address. In this example P = 7 and Q = 13 and the basic tile size is 8192 bits (2¹³ = 8192). Q cannot be made smaller than 13 but it would be possible, merely by altering the data in the WDT EPROM 24 to make Q larger and P correspondingly smaller. If Q = 14 the tile size becomes 16384 bits. P reduces to 6, so there are only 64 large tiles.

Since the irdnimum unit of data transfer is the frame (one row) it will be appreciated that, in the example of Fig. 7, only the 14 MSB's X₁₉ to X₆ have to be preloaded into the address counter 12 on a chip if a data frame is the same size as a tile row. X₅ to X₀ are all initially zero. The counter 12 can be reset to all zeros by ACLOAD before preloading the start address.

Transferring the memory tile map from the WDT EPROM 24 to the RAM 26 means that, if a tile on the wafer develops a hard fault, it can be taken out of the memory tile map currently in use, i.e. the computer 38 can effectively update the map taken from the EPROM 24. Also, access to the RAM 26 will be more rapid than to the EPROM 24.

The choice of tile size is a trade-off between having available the largest amount of usable memory on each chip on the one hand and on the other hand minimising both the size of the memory tile map and the number of occasions on which it is necessary to load the counter 12 with a new tile address.

The fault masking technique has been described here for a RAM with a depth of 1 bit and thus the tiles are all of depth 1 bit. If a RAM with a depth of say 4 bits (one address accesses 4 data bits) is used then each tile will also have a depth of 4 bits. This could be regarded as accessing 4 tiles in parallel. The disadvantage of using a RAM with a depth greater than 1 bit is that a defect on one of the memory planes renders the tiles covering the corresponding areas of the other memory planes unusuable. The trade-off in this is, of course, the reduced memory access times per bit which result from the parallel read/write addressing of the memory planes.

In a practical example, each access may access 4 bits in 4 tiles disposed in the 4 quadrants respectively of the physical array of bit cells.

The fault masking technique described may be referred to as 'implicit fault masking' since, to a user, access to memory is not affected by the masking technique - in contrast to the prior art of Figure 1 in which there are "holes" in the read or write data stream while the on-chip address counter clocks through masked-out areas and the user has to manage these "holes". It can be used on wafer scale integrated circuits, arrays of chips, or even on individual chips. Access times to the memory are extremely fast with virtually no idle time because faulty areas of memory are never accessed. The exact type of interleaving used when addressing a chip will depend on the tile size and frame size selected and the order in which bits on a tile are chosen to be addressed.

Claims

1. A random access memory device comprising a memory (2) addressable by row and column, a source of binary addresses (12) defining a linear address space, row and column decoders (16, 18) responsive to respective groups of bits from the address source (12) to address individual rows and columns respectively of the memory (2), and means (13) for permuting the bits between the address source (12) and the decoders (16, 18) characterised in that at least the higher order bits from the address source (12) are applied to the row and column decoders (16, 18) alternately.

2. A random access memory device according to Claim 1 characterised the bits applied to one decoder (18) are all the odd address bits and the bits applied to the other decoder (16) are all the even address bits.

3. A random access memory device according to Claim 1 characterised in that the bits applied to one decoder comprise a first set of consecutive source address bits (X₀ - X₅) and first further bits (X₁₃, X₁₅, X₁₇, X₁₉), and the bits applied to the other decoder. (18) comprise a second set of consecutive source address bits and (X₆ - X₁₂) and second further bits (X₁₄, X₁₆, X₁₈), the first and- second further bits comprising alternating bits of the highest significance source address bits (X₁₃ -X₁₉).

4. A random access memory device according to any of Claims 1 to 3 characterised in that the permuting of the bits is such that successive counts of N addresses, where N is a power of 2 greater than unity, correspond to rectangular tiles of N physically adjacent address locations in the memory.

5. A random access memory device according to Claim 4 characterised in that each tile extends over a plurality of columns of the memory.

6. A random access memory device according to Claim 4 or 5 characterised by a supplementary memory device (24) storing a sequence of addresses identifying a plurality of the tiles, excluding tiles having defective address locations.

7. A random access memory device according to Claim 6 characterised in that the memory is an integrated circuit memory (22) on a substrate (20) and the supplementary memory device (24) is in a read only integrated circuit memory.

8. A random access memory device according to Claim 7 characterised in that the substrate (20) carries a plurality of the integrated circuit memories (22) and a single read only supplementary memory device (24) storing the said sequences of tile addresses for all the memories (22).

9. A random access memory device according to any of the preceding claims, characterised in that the address source (12) is a binary counter operative to count address locations linearly within the source address space.

10. A random access memory device according to Claim 9, characterised by means (11) for loading the counter (12) with the start address within a tile.

11. A random access memory device according to Claims 6 and 10, characterised by a source (32) of a logical tile address identifying a tile to be accessed for a read or write operation and means (38) responsive to the logical tile address and to the stored sequence of addresses to provide the start address for loading into the counter (12).

12. A random access memory device, comprising a memory (2) addressable by row and column, row and column address decoders (18, 16) for accessing the memory, means (12, 13, 14) responsive to source addresses (X₀ - X₁₉) to apply column and row addresses (A₀ - A₉ and A₁₀ - A₁₉) to the column and row address decoders (16, 18) respectively, with transposition of selected bits between the decoders so as to cause the memory (2) to be partitioned into an array of rectangular tiles which are addressed by more significant bits (X₁₃ - X₁₉) of the source addresses, the less significant bits (X₀ - X₁₂) of which address locations within the tiles, characterised by a look-up table (24 or 26) responsive to logical input addresses to provide the source addresses (X₀ - X₁₉), excluding from the source addresses those which would access faulty tiles.

13. A random access memory device according to claim 12, characterised in that first least significant bits (X₀ - X₅) of the source address are applied to one of the decoders (16) as the less significant bits (A₀ - A₅) input thereto, second next significant bits (X₆ - X₁₂) of the source address are applied to the other. decoder (18) as the less significant bits (A₁₀ - A₁₆) input thereto, and the remaining bits of the source address (X₁₃ - X₁₉) are applied alternately to the two decoders (16, 18)