WO1990001834A1

WO1990001834A1 - Phase-locked loop circuit

Info

Publication number: WO1990001834A1
Application number: PCT/FI1988/000124
Authority: WO
Inventors: Mika Erik NIEMIÖ
Original assignee: Nokia-Mobira Oy
Priority date: 1988-08-04
Filing date: 1988-08-04
Publication date: 1990-02-22
Also published as: EP0427717B1; DE3854722D1; CA1327064C; EP0427717A1; DE3854722T2; JPH04503433A

Abstract

The object of the description is a phase-locked loop circuit comprising e.g. in the form of an integrated circuit (IC) in sequential connection a digital phase comparator, to the input of which are supplied a reference frequency (fref), a loop filter and a voltage-controlled oscillator, from which a feedback branch is fed to the second input of the phase comparator. The voltage (ØV; ØR) of the pulses obtained from the digital phase comparator is disposed so as to be adjustable, thus enabling to modify the limiting frequency and rate of the loop. The adjustment of the voltage of the pulses can be carried out e.g. by adjusting the supply voltage of the phase comparator or by means of an exterior diode or transistor cutter (Q2, Q3). The circuit is usable e.g. in radiotelephone applications, in which a rapid loop is connected during channel switch.

Description

Phase-locked loop circuit

The present invention relates to a phase-locked loop circuit comprising in sequential connection a digital phase comparator; to one input of which a reference frequency is supplied, a loop filter and a voltage-controlled oscillator, from which a feedback branch is connected to the second input of the phase comparator.

Such a phase-locked loop is presented as a block diagram in figure 1. In the figure, the reference frequency fref is taken to

the input of the phase comparator. The output of the phase comparator is connected to the loop filter 2 and this output further to the voltage-controlled oscillator 3. The output of the oscillator 3 is fed back to the phase comparator 1 so as to provide a loop that is set according to the reference frequency fref at a certain rate.

It is well known to use such a phase-locked loop for instance in frequency synthesizers. When a phase-locked loop is used in a frequency synthesis, the voltage-controlled oscillator ( VCO) of which is frequency modulated, contradictory requirements arise as to the loop rate. When a rapid set time is desired when switching from one channel to another, the limiting frequency of the loop should be as high as possible. On the other hand, for the loop not to accentuate nor to damp the modulation, its limiting frequency should be low, more precisely, the limiting frequency should be far lower than the lowest modulation frequency. A low limiting frequency has the additional advantage of reducing the residual modulation and of increasing the damping of the phase reference frequency.

The US patent specifications 4 482 869 and 4 516 083, for instance, and the EP patent application 85615 disclose an acceleration (if the loop filter by changing the resistance value of the integrator stage of the filter either by removing resistors or by short circuiting. Correspondingly, the retardation is based on a removal of the short-circuits or an addition of resistors.

In the US patent specification 4 156 855 the loop is additionally accelerated by increasing the current feeding the capacitor of the integrator stage by means of a current pump.

Controlling the resistors by means of connectors, however, disturbs the operation of the loop. Thus, at the moment- of connecting a slow loop, a momentary twitch usually appears in the adjusting voltage obtained from the VCO, which is inadmissible for instance in radiotelephone applications. The same happens in the case of a sudden change of the current charging the integrator.

Consequently, a frequency synthesis formed by a phase-locked loop has been impossible to use without disturbances in cases where, on the one hand, a rapid setting time, and on the other hand, a linear modulation frequency response are required. In cases, where a modulated frequency synthesis formed by a phase-locked loop has been implemented, these have been compromises between the setting time, the linearity of the modulation frequency response and the reference frequency damping.

For example, in radiotelephone applications requiring a short setting time and a linear modulation frequncy response. has been necessary to use a so-called transfer oscillator system, in which a modulated fixed transfer oscillator frequency is mixed with the recevier injection frequency. On the other hand. a transfer oscillator has the drawback of producing a great number of mixing results, which are difficult to damp. Another drawback is a complicated and expensive circuit.

The object of the present invention is to reduce the above problems and to provide a circuit that enables to use a modulated frequency synthesis also when both a rapid setting time and a Iow limiting frequency of the loop are required. The invention is based on a solution involving a modification of the gain of a phase-locked loop by adjusting the voltage of the pulses obtained from the digital phase comparator, which enables the use of a high limiting frequency, i.e. a rapid loop during the settings and a low limiting frequency after the settings. Since the transfer oscillator system is not used, no detrimental mixing results are produced.

When modifying the gain of the phase-locked loop in this manner by changing the voltage of the pulses obtained from the digital phase comparator, the change of the gain does not disturb the operation of the loop.

Moreover, the circuit is simple and is appropriate for a

commonly used two-output digital phase comparator and an integrator of the operation amplifier type. The circuit according to the invention allows a stepless adjustment when desired, and the adjustment functions flawlessly even with small phase differences.

The main characteristics of the invention appear from the enclosed claim 1 and its preferred embodiments from the independent claims 2 to 10.

According to the invention, the voltage of the pulses obtained from a digital phase comparator can consequently be changed in the phase comparator or outside the phase comparator for instance by a diode, transistor, FET or some other circuit limiting the voltage. The pulse voltage limitation can be provided for instance either at the output of the phase comparator or by means of the circuit set up m the loop filter as described above. In the phase comparator, the adjustment is feasible e.g. by changing the supply voltage of the phase comparator itself, or of its output stage.

It is essential that by changing the pulse voltage in the circuit, the gain of the phase-locked loop can be influenced, and thus the limiting frequency and rate of the loop, among others, can be modified.

It is also essential that when chancing the loop gain in this manner by modifying the voltage of the pulses obtained from the phase comparator, the change of the gain does not disturb the operation of the loop. In addition, the gain is steplessly adjustable.

Thus, it is possible to employ a high limiting frequency i.e. a rapid loop during the setting and to reduce the limit frequency after the setting without disturbing the operation of the loop.

In this way, a rapid setting time and a linear modulation frequency response, a small residual modulation and a great damping of the reference frequency are achieved.

The circuit of the invention for adjusting the gain of a phase-locked loop is applicable m several phase-lock applications, such as frequency-synthesis, modulator or demodulator applications (e.g. AM, FM , PM), a tracking filter, the regeneration of a clock signal, etc.

The adjustment of a phase-locked loop gain is usahle in various applications, e.g. adjustment of the limiting frequency of a loop, acceleration and retardation of the loop, linearization of the modulation frequency response, increasing the reference frequency damping, or e.g. compensating the change of the loop gain as the divisor changes.

The circuit has the additional advantage of being simple and economical, of providing a controllable adjustment, a stepless adjustment and that the gain adjustment does net disturb the operation of the loop.

Moreover, the circuit is applicable to digital phase detectors various types, for instance one- or two-output pnase detectors. The application of the invention to a FM modulated frequency- syntheziser is described in detail below as an example and with reference to the enclosed drawings, in which figure 1 represents a block diagram of the phase-locked loop described above,

figure 2 represents a block diagram of a frequency synthesizer comprising a phase-locked loop,

figure 3 represents an embodiment of the circuit according to the invention,

figure 4 represents pulse figures relating to figure 3,

figure 5 represents frequency responses relating to figure 3.

figure 6 represents figures relating to claims 7 and 8,

figure 7 represents figures relating to claims 8 and 9.

In the frequency syntheziser of figure 2 the reference frequency is provided by a stable crystal oscillator 4 (TCXO) the frequency of which is divided by the dividing element 2 (by number R) order to generate an appropriate phase comparative frequency.

The phase comparative frequency obtained is directed to the phase comparator 1, and the signal supplied by its output is fed into the loop filter 2. This loop filter is a filter of the low pass type, in which the change components are filtered from the stgna of the phase comparator and a direct-current voltage is obtained at the control of the voltage-controlled oscillator 3 ( VCO).

From the output of the voltage-controlled oscillator 3 the feedback is taken through the prescaler 6 and the division element 7 to the second input of the phase comparator 1. When the frequency divider 7 of the feedback loop (divisor N) is made programable, a plurality o f frequencies can be synthezised by chancing the divisor N. The prescaIer 6 is used to reduce the frequency of the voltage-controlled oscillator 3 to the operation range of the programmable divisor 7, the frequency range of which usually is relativeiy narrow. The output of the voltage-controlled oscillator 3 simultaneously forms the f_out of the syntheziser output.

Since this connection is well known in principle to a personskilled in the art, it will not be described in detail here. Finished integrated circuits are available today, which comprise e.g. the dividing elements 5, the phase comparator 1 and the programmable divider 7, such a circuit being marked by the reference IC in the figure.

Figure 3 represents a circuit according to the invention, in which the above integrated circuit IC is of the type MC145156 (manufacturer Motorola).

This is consequently a two-output phase comparator, the outputs which are marked by∅V and∅R in figure 3. These outputs are taken through the resistors R5 and R6 to the integrator, which in the case of the figure is carried out by means of the differential amplifier A.

The natural oscillation frequency fn of the phase-locked loop is

in which Kp' is the gain of the phase comparator

Kvco is

N is the total divisor (fout/fref)

C is approx. C2=C3 in the figure 3 and

R is approx. R7=R8 in the figure 3.

By changing K∅

is obtained. In other words, the natural oscillation frequency of the loop is directly proportional to the square root of the gain of the phase comparator. In the described case the voltage of the pulses obtained from the outputs ∅V and ∅R of the phase comparator is influenced as follows:

In both outputs, subsequent to the resistor R5 vs. P6

the emitters of the cutting transistors Q3 vs. Q2 are connected and the collectors of the transistors ere connected to the supply voltage Vdd (5V). In a normal situation, a low limiting frequency, i.e. a slow loop is switched on, the capacitor C1 having then been charged through the resistor R4 to + 5V and the transistors Q2 and Q3 cut the 5V voltage pulses of the outputs ∅V and ∅R into pulses of approx. 0.5V, as presented in point a of figure 4 .

At the moment of switching channel, as the divisor information fed into the programmable divider of the circuit in use is activated, the activating pulse (TSEN) fed into the terminal 13 of the microcircuit also provides a control through the resistor R2 to the base of the switch transistor Q1. Q1 then becomes momentarily conductive and the charge of the capacitor C1 is discharge through the resistor R3. Under these circumstances, the base voltage of the transistors Q2 and Q3 decreases to oa. OV and the height of the pulses on the emitters of the transistors rises momentarily to 5V, as illustrated in point b of figure 4.

Owing to the increased loop gain the limiting frequency and rate of the loop also increase. Sustaining the rapid loop. i.e. the high qam. depends on the time constant determined by the capacitor C1. In the described case the rapid loop remains switched on for oa. 50ms, which is enough for the loop to settle.

The natural oscillation frequency of the described phase-locked loop with the described circuit being oa. 80 Hz with a rapid loop, (fn1), the natural oscillation frequency (fn2) of a slow loop is approx. 0.5/5 × 80 Hz, i.e. oa. 25 Hz. ( K∅1 . Kvco/N = 2300 Hz). The set of curves of figure 5 illustrates the response of the loc-ked loop of a sample circuit with a rapid loop as well as

with a slow one. From the response both the natural oscillation frequency fn and the limit frequency of the locked loop -3 dB are readable. Moreover, the modulation frequency response of this loop has been drawn in figure 5 both with a rapid and with a slow loop. The modulation frequency response remains direct within the desired range 300 Hz to 10 kHz.

Claims

1. A phase-locked loop circuit comprising m sequential connection a digital phase comparator (1), to one input of which a reference frequency (fref) is supplied, a loop filter (2) and a voltage-controlled oscillator (3), from which a feedback branch is connected to the second input of the phase comparator,

characterized in that the voltage of the pulses obtained from the digital phase comparator (1) is disposed so as to be adjustable, whereby the limiting frequency and rate of the phase-locked loop are modifiable,

2. A circuit according to claim 1, characterized in that

the voltage of the pulses obtained from the digital phase comparator (1) is disposed so as to be adjustable in the phase comparator itself or at its output stage for example by regulating the supply voltage,

3. A circuit according to claim 1, charscterized in that

the voltage of the pulses obtained from the digital phase comparator (1) is disposed so as to be adjustable by a diode or transistor circuit set up outside the phase comparator, or by some other circuit limiting the pulse voltage.

4. A circuit according to claim 2 and 3, characterized in that the voltage of the pulses obtained from the digital phase comparator is adjusted so as to use a larger limiting frequency of the loop during the setting (looking) and a smaller limiting freqυency after the setting.

5. A circuit according to claim 2 and 3, characterized in that the voltage of the pulses obtained from the digital phase comparator (1) is adjusted while the loop is locked so as to modify the gain and the limiting frequency of the loop.

6. A. circuit according to claim 4 and 5, characterized in that the voltage of the pulses obtained from the digital phase comparator (1) is disposed to be adjustable by regulating the supply voltage of a circuit connected between the phase comparator output and the loop filter, which modifies the pulse voltage (amplifies or damps), whereby the voltage of the pulses obtained from the circuit output and thus the gain and limiting frequency of the loop are adjustable.

7, A circuit according to claim 4 and 5, characterized in that the voltage of the pulses obtained from a two-output digital phase comparator is disposed so as to be adjustable by a transistor cutter (Q4. Q5) set up outside the phase comparator, in which the emitters of the transistors are connected through the resistors (R11, R12) to the outputs (∅R, ∅V) of the phase comparator, and the collectors to the supply voltage ( +Vdd ), thus enabling, by regulating the base voltage (Us), to regulate the pulse height on the emitters of the transistors and thus the gain and limiting frequency of the loop.

8. A circuit according to claim 4 and 5, characterized in that the voltage of the pulses obtained from the two-output digital ohase comparator is disposed so as to be adjustable by a diode cutter (D1, D2) set up outside the phase comparator, in which the cathodes of the diodes are connected through the resistors (R13, R14) to the outputs (∅R, ∅V) of the phase comparator, thus enabling, by regulating the anode voltage of the diodes (Us) to regulate the pulse height on the cathodes or the diodes and thus the gain and the limiting frequency of the loop.

9. A circuit according to claim 4 and 5, characterized in that the voltage of the pulses obtained from a one-output digital phase comparator is disposed so as to be adjustable by a transistor cutter (Q6, Q7) set up outside the phase comparator, in which the emitters of the transistors are connected through the resistor

(R15) to the ouput (Pd) of the phase comparator and the collector of the WPN transistor (Q6) to the supply voltage (+Vdd) and the collector of the PNP transistor (Q7) is earth connected, thus enabling, by regulating the base voltage (Ua, Ub) of the transistors (Q6, Q7) to adjust the pulse height on the emitters of the transistors and thus the gain and the limiting frequency of the loop.

10. A circuit according to claim 4 and 5, characterized in that the voltage of the pulses obtained from a one-output digital phase comparator is disposed soas to be adjustable by a diode cutter (D3, D4) set up outside the phase comparator, in which the cathode of one diode (D3) and the anode of the other diode (D4) are connected through the resistor (R16) to the output of the phase comparator (Pd), thus enabling, by regulating the anode voltage (Ua)) of one diode (D3) and the cathode voltage (Ub) of the other diode (D4) to adjust the pulse height obtained from the output of the circuit and thus the gain and the limiting frequency of the loop.