WO1989012364A1

WO1989012364A1 - Improvements relating to fading simulators

Info

Publication number: WO1989012364A1
Application number: PCT/AU1989/000254
Authority: WO
Inventors: Andrew Louis Martin; Paul Ainsworth Grant
Original assignee: Martin Communications Pty. Ltd.
Priority date: 1988-06-10
Filing date: 1989-06-09
Publication date: 1989-12-14

Abstract

Multipath fading simulator and method for use in the testing of microwave transmission and reception equipment. In the preferred method, the simulator is first independently calibrated for increments of notch position and notch depth using a variable frequency calibration tone. Then, with a modulated test signal input instead of the calibration tone, an appropriate sequence of notch positions and depths is played back under stored program control to generate the desired dynamically faded test signal. The simulator has two parallel signal paths (A, B) which include a phase-shifter (120) and a compensating attenuator (136). A feedback circuit (100, 122, 102, 126, 110, 132) is used to balance the signals in the two paths by adjusting the setting of the compensating attenuator (136) when calibrating for notch position; at which time such adjustments are recorded. In operation mode (when the test signal is input), the feedback circuit is disabled and the desired sets of compensating attenuator and phase-shifter adjustments are played back to generate the desired notch position. The desired notch depth can be generated by using series/parallel attenuator sets (804, 806; 814, 818) to vary the signal level contributed to the combined output by each path, or by coupling the signal in one or the other path to the combined output by a variable attenuator (200).

Description

IMPROVEMENTS RELATING TO FADING SIMULATORS

_SU_BSTITUTESHEET This invention relates to methods for simulating multi-path fading in radio signals and to multipath simulators for use in testing the response of radio receiving equipment. It is concerned, more particularly, with the simulation of 5_. multipath fading in digital microwave radio systems, though it is by no means limited thereto.

Multipath fading is the frequency-selective fading of a modulated radio signal caused by the interference at the 0 receiver of signal components which have travelled over paths of different lengths from the transmitter. This may cause attenuation notches of various depths to appear and disappear in the frequency band, to grow, diminish and/or to sweep slowly or rapidly across portions of the band. 5

Receiver response to multipath fading is becoming increasingly important as ever-more complex modes of modulation are used to maximize the data transmission capacity of a link. This is particularly evident in 0 quadrature amplitude modulated (QAM) microwave systems employed for the transmission of digital radio signals. While manufacturers of such systems design their receiving equipment to be tolerant of, or to dynamically compensate for, multipath fading, it is most difficult and expensive 5 for manufacturers or users to test the response of the equipment to multipath fading without the use of a multipath fading simulator which can be interposed between the source of an unfaded test signal and a receiver under evaluation to determine its response to any realistic 0 fading pattern imposed on the original signal.

Fading simulators comprising two parallel circuit paths of differentially adjustable electrical length and attenuation are known. They typically employ a variable vector- 35 modulated complex attenuator/phase-shifter, together with a switched delay line, to effect the differential adjustments of path length and attenuation. However, such

TESHEET attenuators have been found to be impractical for a number of reasons:

* Extremely accurate components are required to reliably reproduce the precise matching of the signal levels in the two paths needed to generate deep notches (say, at 99% attenuation) or to reliably reproduce the location and movement of a notch in the signal band. * Because notch depth (amplitude-wise) and notch position (frequency-wise) are interdependent, calibration of the simulator preparatory to generating a desired test fading pattern (or test signal) is extremely laborious. * Component and thermal drifts in the long interval between the start of calibration and the end of operation seriously impair accuracy of notch position and notch depth.

* As transition from minimum to non-minimum phase conditions must be switched, it cannot be effected smoothly.

US patent No 4,679,248 to British Telecommunications PLC (herein called the BT patent) offers a significant improvement over the above described art through the use of a pilot tone (added to the input test signal before the two paths separate) and a feedback circuit which adjusts the complex attenuator to minimise the pilot tone (ie, to centre the notch position on the pilot tone). This nominally yields a maximum depth notch at the frequency of the pilot tone which can be moved simply by varying the frequency of the pilot tone. The use of feedback control to position the notch also compensates for much of the component drift in the parallel paths. The depth of the notch can then be adjusted, according to the BT patent, independently of the notch position by coupling a controllable amount of the signal in one or the other of

_BSTIT_UTESHEET the parallel paths to the output via a variable attenuator. To isolate the pilot tone from the combined output of the two parallel paths for use in the feedback circuit, and to remove the pilot tone from the simulator output, complex correlators are employed.

Though the facility to independently adjust the notch depth and position is an important advance, the use of the pilot tone and the associated correlators carries serious disadvantages.

* Use of a feedback circuits for notch position (and for pilot tone cancellation) makes hardware calibration essential, which is laborious and subject to drift.

* The necessarily imperfect operation of the correlators and feedback controls means that the pilot tone cannot be eliminated (it being significant where deep notches are employed) and undesirable intermodulation distortion is introduced into the faded test signal.

* The correlators remove any significant components of the signal having the same frequency as the pilot tone and, therefore, inherently distort the faded test signal.

* Moreover, the use of such correlators make the simulator complex, costly and difficult to adjust and maintain.

* The speed of response of the simulator to control signals (eg. the speed at which the notch can be swept) is limited by the use of the correlators and there is danger of instability. * Switched transition from minimum to non-minimum phase conditions is still employed.

* Finally, much of the inherent drift compensation gained by the use of feedback is lost through greatly increased circuit complexity. The overall result is that simulators of this design are difficult to construct and use even in low-capacity 16 QAM systems.

TESHEET It is therefore the object of the present invention to provide an improved multipath simulation method and multipath simulator. More particularly, it is desired to provide forms of the invention which will allow rapid and simple computer-based calibration without the need to resort to pilot tones and correlators, where smooth transition between minimum and non-minimum phase conditions is possible, and/or where there is a high degree of inherent stability even where deep and fast-moving notches are being simulated.

The method of this invention is characterised by the use of a preliminary calibration stage comprising the steps of adjusting first electronically-controllable parameters of the circuit to vary notch depth without substantially changing notch position and recording a first set of such adjustments corresponding to increments of notch depth; adjusting second electronically-controlled parameters of the circuit to vary notch position without substantially changing notch depth while recording sets of such adjustments corresponding to increments of notch position; and using said recorded sets of adjustments to adjust said parameters to impose a desired fading pattern on a modulated test signal input to the circuit means.

It is preferred to employ a variable frequency and/or variable amplitude calibration tone during the calibration stage and to use a programmed microprocessor to effect both the frequency (notch position) and amplitude (notch depth) incrementation, the recording of the sets of parameter settings and, during operation of the simulator with the desired modulated signal input, to recall or compute the parameter settings needed to effect a predetermined fading pattern. It is also preferred to use a feedback circuit to hold the signal levels in the two paths equal when incrementing the frequency of the calibration tone by adjusting a compensation attenuator in one of the paths.

_STIT_UTESHEET This ensures that the notch depth is held at a fixeα maximum for every increment of notch position. The setting of the compensation attenuator for each increment forms part of the second set of-recorded parameters which can be selectively 'replayed' when generating the desired faded signal.

Notch depth can be calibrated by using a fixed frequency calibration tone, detecting the level of the output signal (preferably with a complex detector) and incrementing the level of the calibration tone, attenuators in either path, and/or an attenuator connected to adds the signal from one path to the output. Depending on the position of the attenuators employed for this purpose, it may also be desirable to balance the signals in the two paths by means of a compensating attenuator while incrementation is in progress. Again, this incrementation, the settings of the attenuators concerned and the 'play-back' of desired settings during the operation stage is preferably placed under microprocessor control.

Having generally portrayed the nature of the present invention and indicated the way in which the stated objectives can be achieved, two particular embodiments of the invention will now be described by way of example and illustration only. In the following description, reference will be made to the accompanying drawings, in which:

Figure 1 is a block circuit diagram of the simulator of the first chosen embodiment;

Figure 2 is a block circuit diagram showing how the linear attenuator in the circuit of Figure 1 may be implemented;

Figure 3 is a circuit diagram showing how the variable delay line of Figure 1 may be implemented;

SHEET Figure 4 is a block diagram showing the arrangement of the microprocessor and memory of Figure 1;

Figure 5 is a block circuit diagram showing how the variable phase-shifter employed in the simulator of Figure 1 may be implemented;

Figure 6 is a detailed circuit diagram of the amplitude detector of Figure 1;

Figure 7 is a detailed circuit diagram of the amplitude comparator and feedback element of Figure 1;

Figure 8 is a logic flow diagram illustrating the routine for the calibration of notch position for the system described in Figure 1;

Figure 9 is a logic flow diagram illustrating the routine for the calibration of notch depth for the system described in Figure 1;

Figure 10 is a logic flow diagram illustrating the routine for the operational mode of the system described in Figure 1; and

Figure 11 is a block circuit diagram of the simulator of the second chosen embodiment.

Referring to Figure 1, the two parallel paths of the simulator are shown generally at A and B and are fed, via splitter 104, from a common input line 106 which can be connected by two-position switch 108 to either the unfaded test signal on input line 110 or to the output of a frequency synthesizer 112 on input line 114. The synthesizer 112 provides the calibration signal for the simulator and is controlled by a voltage signal j from a microprocessor-based control unit 116.

TESHEET Differential variation of the effective length of paths A and B is achieved by the combination of a switched variable delay unit 118 in path A which acts as a coarse control and a variable complex attenuator or phase-shifter 120 in path B which acts as a fine control. Delay unit 118 (connected by line 105 to splitter 104) is controlled by signals f, g & h, and phase-shifter 120 (connected by line 107 to splitter 104) is controlled by signals x and y, derived from control unit 116. In common with all practical phase shift devices, delay 118 and shifter 120 will change their attenuation with phase-shift setting - usually in a non¬ linear fashion.

To balance the levels of signals in paths A and B irrespective of the settings of delay 118 and phase-shifter 120, a fixed proportion of the signal in path A is taken from line 100 via coupler 122 and line 124, together with the same proportion of the signal on line 102 in path B taken via coupler 126 and line 128, to a comparator circuit 110. The error signal from this comparison is taken via line 130, two-position switch 132 and line 134 to suitably adjust a compensating variable voltage-controlled attenuator 136 (which is connected by line 119 to delay 118) to equalise the signals in the two paths. This error signal is also fed as input signal m to control unit 116.

The signals from the two paths A and B are re-combined by a combiner 138 and fed via line 140 to another combiner 142 from which the output of the simulator is taken on output line 144. The second input to the latter combiner (142) is received on line 146 via a linear variable attenuator 148 from a three-position selector switch 150 via line 151. Switch 150 can (i) select portion of the signal in line 100 of path A via line 152 and coupler 154, (ii) select portion of the signal in path B via line 156 and coupler 158, or

_ITUTESHEET (iii) select neither input when in its central or intermediate position 160. Attenuator 148 controls the amount of the signal from path A or path B that is added to the output via combiner 142 and is controlled by control unit 116 via control signals p, q and r.

Finally, portion of the output signal from the simulator on line 144 is coupled via coupler 162 to amplitude detector 164, the output signal z of which is, in turn fed via line 166 to the microprocessor control unit 116.

The voltage-controlled notch-depth adjusting attenuator 148 is shown in more detail in Figure 2 and consists of a voltage-controlled in-line attenuator 200 which, though not a precision attenuator, can be adjusted over the full range of attenuation required without the need for series/parallel switching (which causes undesirable signal disturbances). The control voltage for this attenuator is selected by two-position switch 202 from either control signal r on line 201 from the control unit 116 or the control signal on line 203 from the output of a comparator circuit 204. This control signal is also directed via line 205 to the microprocessor control unit 116 as signal p. Comparator 204 compares the amplitude of the signal on input line 151 (via coupler 206, a precision switched reference attenuator 208 and line 210) with the amplitude of the signal on output line 146 (via coupler 212 and line 214). It therefore has the effect of setting non-switched attenuator 200 to the same value as the more precise switched attenuator 208 which is controlled via control signal q from the control unit 116 (when switch 202 is connected to line 203 from comparator 204).

Referring to Figure 3, the details of the switched delay (or coarse phase-shifter) 118 are shown. In this example, variable delay 118 provides a delay of 0 - 7 nana seconds

(ns) in one nε increments by the use of three coaxial-cable

_SUB_STITUTESHEET delay-lines of 1, 2 and 4 ns respectively (shown at 300, 302 and 304) . Each delay line can be εhorted-out by a two- pole, two-position relay-operated switch (respectively shown at 301, 303 and 305). The relay 306 associated with the 1 ns delay line 300 is operated by signal f from microprocessor 116, relay 308 associated with the 2 ns delay line 302 is operated by signal g and relay 310 associated with the 4 ns delay line 304 is operated by signal h.

The microprocessor-based control unit 116 is shown in somewhat more detail in Figure 4. The microprocessor itself (400) is associated with a random access and/or disc memory 402 and a programable user interface adaptor 404. Input signal voltages p, m and z are fed via an A/D converter 406 onto the data bus by means of corresponding bus drivers 408 and address decoder 410; output control voltage signals n, r, x & y, and f, g & h are derived from a D/A converter 412 and its associated bus receivers 414 and address decoders 416. Signals (unlabelled) to operate switches 108, 150, 132, and 202 are similarly interfaced to the microprocessor 400 through switch driver circuit 418 via bus receiver 420 and address decoder 422.

Referring to Figure 5, it can be seen that phase-shifter 120 comprises a simple network of four commercially available complex attenuator devices. A quadrature hybrid device 500 receives the incoming signal ^"on path B and generates two outputs, one (on line 502) at 0° and the other (on line 504) at 90°. Line 502 is connected to a voltage-controlled 0-180° complex phase-shifter device 508 controlled by input signal y from control unit 116, signal is variable in amplitude with a phase of 0° or 180°, while line 504 is connected to another 0-180° device 510 controlled by input signal x, the outputs of both devices being connected to a combiner device 512 which adds the two signals output by devices 508 and 510 to furnish the

TESHEET phase-shifted output of the whole phase-shifter 120 on line 102. As previously noted, operation of phase-shifter 120 will incidentally vary the attenuation of the signal in path B.

Conveniently, the devices shown in Figure 5 are selected from the catalogue of Minicircuits of Brooklyn, New York, USA. Hybrid device 500 is selected for the frequency range of interest, as follows: Minicircuit No. Frequency Range MHz

PSCQ-2-50 25 - 50

PSCQ-2-70 40 - 70

PSCQ-2-90 55 - 90

PSCQ-2-180 120 - 180 Devices 508 and 510 are PAS-1 and device 512 is PSC-2-1 also from Minicircuits.

The detector 164 is shown in more detail in Figure 6.

Signal on input line 161 from coupler 162 (Figure 1) is fed via buffering amplifier 600 to an isolating transformer

602. The resultant signal, impressed across load resistor

603, is then rectified by diode 604 to charge capacitor 606 which is discharged via resistors 608 and 614, the voltage across capacitor 606 and resistor 614 being fed via series resistor 616 and buffer amplifier 618 (together with its by-pass resistor 620) to the output line 166 as signal z.

Figure 7 illustrates an amplitude comparator which may be used for both circuit elements 110 and (204). The comparator compares the levels of signals on lines 124 (210) and 128 (214), the difference being converted to an output signal m (p) to drive the attenuators 136 (200).

The signal on input line 124 (210) is passed via switch 702 (which is driven with a 10kHz 0° signal via clock line 704) to adder 706, the signal on line 128 (214) also being

U_BSTITUTESHEET passed via switch 708 (driven with a 10kHz 180° signal on clock line 710) to adder 706. Any difference in the amplitudes of the signals on lines 704 and 710 thus appears as an amplitude modulated 10kHz signal on line 716, the level of amplitude modulation being equal to the difference in the input levels as 124 (210) and 128 (214).

This amplitude modulated signal is amplified by buffer amplifier 718 and impedance matched to the detector 722 by transformer 720. The detector 722 half wave rectifies the signal from transformer 720 and the resultant rectified signal is filtered by capacitor 724 to remove high frequency components. The signal on line 723 is a square wave of 10kHz with a DC offset which is removed by capacitor 725, and the resulting 10kHz signal is applied to a zero crossing detector 726, the output of which is passed via line 728 to a phase detector 732 where the phase of the signal on line 728 is compared with the phase of the 10kHz reference signal on line 730. When the signals on lines 728 and 730 are out of phase the output of phase comparator 732 is a high signal on line 734 while when the signals 728 and 730 are in phase the output of phase comparator 732 is a low signal on line 734.

The mean value of the signal on line 734 is obtained by passing it via a low pass filter 736 with a variable DC offset obtained at the output of 736 using offset control potentiometer 740, the output of filter 736 being applied via line 737 to the input of output amplifier 738. The output of amplifier 738 comprises signal m (p) used to control attenuators 136 (200). As already noted, signal m is controlled to minimise the difference between signals on lines 124 (210) and 128 (214).

In operation, the simulator is alternately run in the calibrate mode and in the operation mode, switching between the two modes being program-controlled via the control

_ITUTESHEET unit 116, the operation of switches 108, 160 and 132 preferably being controlled by the microprocessor by signals which are not identified in Figure 1.

There are two basic calibrations to be performed - one for the combination of delay 118 and phase-shifter 120, and the other for variable attenuator 148 - corresponding, respectively, to notch position and notch depth. A flow diagram for the notch depth routine is shown in Figure 8, while that for the notch position is shown in Figure 9. Two different sets of calibrations may, however, be made and recorded for notch depth if both the minimum and non- minimum phase conditions are desired (one set being recorded when switch 150 connects line 151 to input 152 and the other when it connects line 156 to 151). In any event, at the commencement of the calibration mode, switch 108 is set to select the output of the frequency synthesizer 112.

To calibrate notch position, switch 150 is set to its mid position where neither input line 152 or 156 is selected so that no signal flows through attenuator 148 to contribute to the output on line 144. Also, switch 132 is set to select the error signal m on line 130 from the comparator 110. The control unit then controls synthesizer 112 to increase the frequency of its output from the minimum frequency (corresponding to the lowest notch position in the signal band) to the maximum frequency (corresponding to the highest notch position in the signal band) in a series of increments or steps. At each step, phase-shifter 120 (and if necessary) delay 118 are controlled by control signals x and y and - progressively - f, g & h) to minimise the amplitude of the test signal on output 144 as indicated to the control unit by detector 164 via control signal z on line 166.

The minimization of the output signal at each increment of the calibration signal frequency is achieved as follows.

S_TITUTESHEET Delay line 118 is switched to the length appropriate for the frequency range and phase-shifter 120 is first set to the nominal value expected from the circuit design to provide signals on inputs to combiner 138 which are 180° out of phase, given the frequency of the calibration signal. Equalization of the signal levels in paths A and B is then automatically effected by comparator 110 and associated attenuator 136. The control voltage on line 130 to attenuator 136 is read into the control unit 116 via control signal ra and recorded. Switch 132 is then set to select the output signal n from the microprocessor, this signal being set and held to the level of control voltage m just read so that the voltage-controlled attenuator 136 is held at a constant attenuation. Next, signals x and y from the control unit 116 are varied (according to a gradient search algorithm) to adjust both the phase shift and the attenuation of complex phase-shifter 120 to achieve substantial complete cancellation of the calibration signal on the output line 144, as sensed by the detector 164. The values for x, y and m at each calibration signal increment are then recorded in the micro-processor memory.

To calibrate notch depth, switch 108 remains set to select the calibration signal on line 114 and switch 132 is set to select the error signal m from the comparator on line 130, but switch 150 is set to select either the input 152 or input 156 (depending on whether the minimum phase or non- minimum phase signal mode is desired). The calibration signal is then set to an arbitrary or predetermined intermediate frequency and the signals in the two paths are balanced automatically, by comparator 110 and its associated feedback circuit, to produce substantially complete cancellation at the combiner 138 (ie, substantially no output on line 140) as before. Attenuator 148 is then incremented from a minimum setting (where a maximum signal level is coupled from path A or B to output line 144) to a maximum setting (where

ET substantially no signal is present on output 144) while the output level (in dB) is sensed by detector 164 and signalled to the control unit 116.

In this way, the attenuator control signals p, q & r corresponding to many increments (each, say, one half dB) of output level (notch depth) can be recorded by the microprocessor. If it is desired to simulate both the minimum and non-minimum phase conditions, the procedure is repeated with switch 150 set to select the alternate input line (152 or 156) and a second series of attenuator control settings is recorded.

In operation mode, switch 108 is set to select the unfaded test signal on input line 110, switch 150 is set to select input 152 or 156 as required, switch 132 is set to select control line n from control unit 116 and output line 144 (bearing the test signal with the desired fading pattern) is connected to the receiver circuit to be tested. The signal z from detector 164 is ignored by the control unit 116. Control unit 116 then runs a stored program of phase- shift (circuits 118/120) settings via control signals x & y and f, g & h, balancing attenuator (148) settings via control signal n and notch-depth attenuator (142) settings via control signals p, q & r to generate the desired multipath fading pattern of notch sweep and depth. A flow diagram for the operation mode is illustrated in Figure 10.

Because any desired multipath fading pattern can be accurately generated in this way without the need for complex correlators or feedback loops, the response of the system and method of the present invention is fast enough to simulate most if not all of the sweep rates experienced in the field. For example sweep rates of 100 MHz/s and 100 dB/s with an accuracy of 1% on any setting can be readily achieved with modern 16 and 32 bit micro¬ processors. Such rates and accuracies (and the implicitly

U_BSTITUTESHEET low levels of inter odulation distortion and output noise) are greatly superior to those achievable by the prior art systems known to the applicant. However, transition between minimum and non-minimum phase conditions during operation still cannot be achieved rapidly and smoothly with this embodiment.

The second embodiment of a multipath fading simulator formed in accordance with this invention, illustrates how the notch depth can be set at the desired level in one step, thereby avoiding the need to first create a maximum depth notch and then fill it in by the desired amount. Such an arrangement also allows smooth transition between the minimum and non-minimum phase conditions during operation. This embodiment is shown in Figure 11 where the same reference numerals are used to indicate the parts and signals which are the same as in Figure 1.

As will be seen from a comparison of Figures 1 and 11, the principal difference lies in the elimination of the switch 150, linear attenuator 148 and combiner 142 of Figure 1, and the insertion of attenuator sets in paths A and B together with an attenuator in the output of frequency synthesizer 112. The latter attenuator (800) is preferably a precision linear attenuator of the type shown in Figure 2, except that there is no need for switch 202 or associated control signals p and r. Signal q' from control unit 116 on line 801 serves to effect control of the attenuator 800.

The attenuator sets added to the downstream ends of path A and B simply comprise shunted and series linear attenuators which are differentially adjusted to achieve notch depth control and smooth transmission from minimum to non-minimum phase conditions. The attenuator set included in path A comprises a low-range attenuator 804 and a high range attenuator 806, the low range attenuator being

TESHEET connected in parallel with a shunt 808 (by the use of a splitter 810 and a combiner 812), high range attenuator 806 being connected in series with the path. Similarly, the attenuator set included in path B comprises a low range attenuator 814 connected in parallel with a shunt 816, and a series-connected high range attenuator 818. The signal on path B is divided by splitter 820 between shunt 816 and attenuator 814 before being recombined by combiner 822 and fed to attenuator 818. Settings of attenuators 804, 806, 814 and 816 are controlled by signals a, b, c and d (respectively) from microprocessor control unit 116.

To calibrate the variable delay 118 and phase-εhifter 120 for notch position, switch 108 is set to select the output of the frequency synthesizer 112 and switch 132 is set to select the error signal m on line 130 from the comparator 110. Under program control, control unit 116 sets the output frequency of synthesizer 112 at an arbitrary level in the band concerned, attenuator 800 being set to its minimum value, shunted attenuators 804 and 814 being set to their maximum values and series attenuators 806 and 818 being set to their minimum values. The feed-back circuit including comparator 110 then adjusts compensating attenuator 136 to compensate for any differential drift in the components in the two paths.

Once the circuit has stabilised, the error signal m generated by comparator 110 is read and recorded by control unit 116. That signal is then held and output as signal n to be selected by the operation of switch 132, thus disconnecting the feedback control of compensating attenuator 136.

Frequency synthesizer 112 is then set (by signal q' on line 802 from control unit 116) at one end of the range corresponding to the test signal frequency band, the switch delay line 118 is set (by control signals f, g and h) to

_ITUTESHEET the corresponding setting, and the test signal is incremented in successive steps toward the other end of the range. At each step, using a simple gradient search algorithm, control unit 116 adjusts phase-shifter 120 (and when appropriate delay line 118) so that the output signal on line 144 is at a minimum - ie, the notch depth is at a maximum for the particular frequency at which synthesizer 112 is set. As each successive minimum is detected, the setting of synthesizer 112 and phase shifter 120 are recorded, together with the level of error signal m from comparator 110, in a notch-position calibration table in memory. The setting of switched delay 118 can also be recorded if desired, but it can be readily derived from the frequency of the calibration tone.

To calibrate detector 164 for notch depth, frequency synthesizer 112 is first returned to the original arbitrary setting and series attenuator 806 in path A is set to its maximum value thereby eliminating the notch from the output by effectively removing the contribution made by path A to the output. Then, attenuator 800 in the calibration tone line 114 is incremented in known dB steps and the output of the detector 164 on line 166 is read and recorded for each step or increment to create a detector calibration table in memory which covers the whole range of possible notch depths. A second detector calibration table can then be made, if desired, by repeating the procedure for path B; that for path A corresponding to, say, the minimum phase condition and that for path B corresponding to the non- minimum phase condition.

To calibrate the attenuator sets for notch depth in the non-minimum phase, shunted attenuators 804 and 814 and series attenuators 806 and 818 are set to the (previously recorded) values necessary to achieve the maximum notch depth (ie, shunted attenuators 804 and 814 will be set to near-maximum attenuation and series attenuators 806 and 818

TITUTESHEET will be set to near-minimum attenuation). Then, to undertake the calibration, shunted attenuator 804 in path A is adjusted from its near-maximum setting to gradually fill-in notch so that the depth is around 15 dB (about mid- point in the range). While this is being done, the level of control signal a to attenuator 804 needed to achieve each increment of intermediate dB values of notch depth between minimum and 15 dB (as determined by control unit 116 using the detector calibration table) is recorded to form the first half of a non-minimum-phase notch-depth calibration table.

When the 15 dB level is reached, shunted attenuator 804 is not adjusted further but series attenuator 818 in path B is incrementally increased in value from its near-minimum setting until a notch of zero depth is achieved, the level of control signal d needed to achieve each dB increment being recorded. This completes the second half of the minimum-phase calibration table.

A minimum phase notch-depth calibration table is then built up in the same way by successively varying attenuators 814 and 806, while holding attenuator 804 at its near-maximum setting and attenuator 818 at its near-minimum setting and while recording the levels of control signals c and b for each group of increments.

In operation, switch 108 is set to select the unfaded test signal on input line 110, switch 132 is set to select control signal n and the output line 144 is connected to direct the test signal with the desired fading pattern superimposed thereon to the receiver circuit to be tested. Signal z from detector 164 is ignored by the control unit 116.

Control unit 116 then runs a stored program of phase-shift and delay settings (ie, a sets of signals a, b, c, d, f, g,

_SUBSTITUTESHEET h, x, y and n) to effect the desired simulation of notch depth and movement, recalling sets of these values from memory or interpolating between recorded values to generate new sets at appropriate (program-determined) intervals. By differentially adjusting the series and shunted attenuators in the two paths, a smooth transition between minimum and non-minimum phase conditions can be achieved at any notch depth and position.

It will be seen that the substitution of the precision attenuator 800 (Figure 11) for precision attenuator 148 (Figure 1) has important advantages. It not only allows ready and automatic calibration of the detector 164 but, as attenuator 800 is not in the test signal path and not used during the operation stage, it can be of a switched design allowing for simplicity and precision.

While fading simulator methods and circuits have been disclosed which provide substantial advantages over the art, it will be appreciated by those skilled in the art that many variations and modifications to the system and the circuits described can be made without departing from the spirit and scope of the present invention as set out in the following claims.

TUTESHEET

Claims

CLAIMS :

1. A method of simulating multipath radio signal fading whereby an attenuation notch of controllable depth and position is produced in a modulated test signal, said method comprising the steps of:

* passing a modulated signal of desired bandwidth through circuit means having a pair of parallel signal paths between the input and output thereof, and

* running a stored program to control circuit parameters to independently generate the desired notch positions and depths by reference to a first pre-recorded calibration table of notch position vs parameter values and by reference to a second pre-recorded calibration table of notch depth vs. parameter values, to thereby generate a modulated test signal having a predetermined, fading pattern imposed thereon.

2. A method according to claim 1 comprising the step of generating at least portion of said notch position calibration table by:-

* passing a calibration tone through the circuit means,

* incrementing the frequency of said tone within the band,

* adjusting a first set of electronically-controlled circuit parameters to reduce the combined tone output of said paths to a minimum for each increment, and

* recording a first set of such adjustments against increments of frequency.

3. A method according to claim 2 wherein said combined tone output from the paths is reduced to a minimum for each increment of calibration tone frequency by:- * detecting the level of the combined output of the signal paths,

_STITUTESHEET * adjusting the setting of phase-shift means within the signal paths,

* sensing the level of the tone in each signal path,

* generating a control signal corresponding to the difference in level between the signals in the signal paths, and

* employing said control signal to adjust the setting of compensating attenuator means within one of said paths, the set of said phase-shift means adjustments and the set of said compensating attenuator means adjustments corresponding to said frequency increments of the calibration tone comprising said first set of parameters.

4. A method according to any preceding claim wherein said notch depth calibration table is generated by:-

* passing a fixed-frequency calibration tone through the circuit means,

* adjusting said first set of circuit parameters to minimise the level of the tone output from the

* adjusting a second set of electronically-controllable circuit parameters to vary the level of the tone output from the circuit means, and

* recording a second set of such adjustments of said second circuit parameters corresponding to increments of output level.

5. A method according to claims 2 or 3 wherein said notch depth calibration table is generated by:- * passing a ixed-frequency calibration tone through the circuit means,

* adjusting said first set of circuit parameters to minimise the level of the tone output from the circuit means, * adjusting a second set of electronically-controllable circuit parameters to vary the level of the tone output from the circuit means, and

UTESHEET * recording a second set of such adjustments of said second circuit parameters corresponding to increments of output level.

6. A method according to claim 4 or 5 including the steps of:-

* incrementing the level of said fixed-frequency calibration tone by predetermined amplitude steps, and

* adjusting said second set of electronically- controllable circuit parameters to vary the level of the tone output from the circuit means by the same said predetermined amplitude steps to vary the level of the tone output from the circuit means so as to return it to a predetermined level.

7. A method according to claim 4, 5 or 6 including the steps of:-

* detecting the level of said fixed-frequency tone output from said circuit means, * adjusting the setting of phase-shift means within said signal paths to reduce the combined output tone from the paths to a minimum, and then

* adjusting the setting of notch-fill attenuator means to increment the level of said combined output by incrementally increasing the proportion of the signal in one of the paths coupled to the combined output tone of both paths, the set of said notch-fill attenuator adjustments corresponding to said increments of combined output level comprising said second set of parameters.

8. A method according to claim 4, 5 or 6 including the steps of:-

* detecting the level of said fixed-frequency tone output from said circuit means,

_SUB_STITUTESHEET * adjusting the setting of phase-shift means within said signal paths to reduce the combined output tone from the paths to a minimum, and then

* adjusting the setting of notch-fill attenuator means to increment the level of said combined output by incrementally increasing the relative proportions of the signals in the parallel paths, the set of said notch-fill attenuator adjustments corresponding to said increments of combined output level comprising said second set of parameters.

9. A method according to claim 8 wherein said notch-fill attenuator means comprises a series attenuator series- connected in each path and a shunt attenuator shunt- connected in each path, and wherein:-

* the series attenuator in one path and the shunt attenuator in the other path are adjusted to increment the combined outputs of each path for one phase condition, and * the alternate series and shunt attenuators are adjusted to increment the combined outputs of each path for the other phase condition, the set of said series of series and shunt-connected attenuator adjustments corresponding to said increments of combined output level comprising said second set of parameters.

10. A method according to claim 6, 7 or 8 including the steps, during calibration, of:- * comparing the setting of the notch-fill attenuator with the setting of a reference attenuator, and * generating a second feedback signal to adjust the setting of said notch-fill attenuator according to the setting of the reference attenuator for each increment of signal output,

TESHEET the set of second feedback signals corresponding to the incremented signal output comprising the second set of parameters.

11. A method of imposing a predetermined multipath fading pattern upon a modulated test signal of known bandwidth substantially as hereinbefore described.

12. A fading simulator for generating multipath-faded test signals, having attenuation notches of controllable frequency position and/or attenuation depth, from a modulated input signal of known bandwidth, comprising:

* two parallel signal paths extending between a point of path divergence and a point of path convergence, * signal input means connectable to said divergence point and a signal output means connectable to said convergence point,

* electronically variable phase-shifter means in at least one of the paths for adjusting the relative electrical length of the paths,

* signal level detector means connected to said signal output means,

* feedback circuit means for substantially equalising the levels of the signals in the paths by adjusting the setting of an electronically variable compensating attenuator means in one of the paths, and

* switch means connected within said feedback circuit operable to disable the adjustment said first attenuator by said feedback means and to enable its adjustment by an alternative control signal, whereby said phase-shifter and said compensating attenuator can be first calibrated for notch position by incrementing the frequency of a calibration tone fed to said input means while adjusting said phase shifter and said compensating attenuator to minimise the output signal for each tone increment with said feedback circuit enabled, and then, with said feedback circuit disabled and using the input

SHEET modulated signal, to generate attenuation notches in the output test signal at desired positions by controlling the phase-shifter and the compensating attenuator under programmed control.

13. Apparatus according to claim 12 having -

* electronically variable notch-fill attenuator means connected between one of the paths and the signal output to augment the signal at the convergence point with a controllable proportion of the signal in said one path, whereby notches of variable depth can be produced in the output test signal by adjusting the setting of said notch- fill attenuator.

14. Apparatus according to claim 12 having -

* electronically variable notch-fill attenuator means connected in at least one path, whereby, when said feedback circuit is disabled, the relative levels of the signals in the two paths - and, therefore, the depth of the attenuation notch in the output test signal - can be placed under the control of a stored progra .

15. Apparatus according to claim 13 or 14 wherein said notch-fill attenuator means comprises -

* a first electronically adjustable attenuator connected in the signal path,

* a reference attenuator, * second feedback circuit means for generating an error signal to effect the adjustment of said first attenuator to correspond with that of said reference attenuator, and

* second switch means connected within said second feedback circuit to disable the adjustment of said first attenuator and to enable its adjustment by a second alternative control signal,

UTESHEET whereby said first feedback attenuator can be calibrated against said reference attenuator and, then, with the second feed back circuit disabled said first attenuator can be adjusted under program control to set the desired notch depth.

16. Apparatus according to claim 14 wherein -

* said notch-depth attenuator means comprises a shunted attenuator and a series attenuator in each path, whereby the series attenuator in one path and the shunted attenuator in the other path can be adjusted together to vary the notch depth at the convergence point from a desired minimum to a desired maximum for one phase condition of the output signal, and the alternate series and shunted attenuators can be adjusted together to vary the notch depth for the other phase condition.

17. Apparatus according to any preceding claim having:-

* an electronically controllable frequency synthesizer for generating the calibration tone and having an output therefor, and

* microprocessor-based control means connected to effect the control of said frequency synthesizer and said phase-shifter means and/or said notch-fill attenuator means.

18. Apparatus according to claim 17 having:

* third switch means operable to connect either said signal input means for the modulated test signal, or the said output of said frequency synthesizer, to the divergence point of the paths.

19 Apparatus according to claim 17 or 18 wherein the microprocessor control unit is connected to operate said first and said second switch means to enable said feedback circuits when said third switch means is operated to connect the output of the frequency synthesizer to the path

ST_ITUTESHEET divergence point, and wherein the microprocessor control unit is connected to operate said first and said second switch means to disable said feedback circuits when said third switch means is operated to connect the signal input means to the path divergence point.

19. A fading simulator for generatingmultipath-faded test signals, having attenuation notches of controllable frequency position and/or attenuation depth, from a modulated input signal of known bandwidth, substantially as hereinbefore described with reference to the accompanying drawings.

TESHEET