WO1989012272A1 - Procede de controle d'erreurs dans des donnees - Google Patents

Procede de controle d'erreurs dans des donnees Download PDF

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Publication number
WO1989012272A1
WO1989012272A1 PCT/EP1988/000501 EP8800501W WO8912272A1 WO 1989012272 A1 WO1989012272 A1 WO 1989012272A1 EP 8800501 W EP8800501 W EP 8800501W WO 8912272 A1 WO8912272 A1 WO 8912272A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
error
free
errors
counter
Prior art date
Application number
PCT/EP1988/000501
Other languages
English (en)
Inventor
Wolfgang Drobny
Werner Nitschke
Peter Taufer
Hugo Weller
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to PCT/EP1988/000501 priority Critical patent/WO1989012272A1/fr
Publication of WO1989012272A1 publication Critical patent/WO1989012272A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit

Definitions

  • the present invention relates to a method of monitoring errors in data transmitted between serially coupled microcomputers.
  • Errors detected by the check can be dealt with in a number of ways. In motor vehicle electro magnetic interference is high and so the risk of data errors is also high. It is therefore necessary to distinguish between occasional errors which are assumed to be due to interference and more regularly occurring errors which could be due to equipment or software malfunction or an unacceptably high level of interference.
  • the present inventions provides a method of monitoring the frequency of occurrence of errors in a system, the method comprising checking each piece of data as it is received, detecting a piece of data in error, counting the number of error-free pieces of data received after detection of a piece of data in error, comparing the count with a threshold value, and placing the system in a predetermined condition as a result of the comparison.
  • the system is reset if n error- free transmissions do not follow an error in transmis- sion. It is, however, possible for an error correction routine to be followed.
  • the pieces of data can be data words or even individual bits.
  • Data is transferred between CPU's and between peripherals and a CPU in a computer system in the form of digital words of K data bits, typically 8 bits. It is customary to also include with each word a parity bit or other error checking code to enable transmission errors to be detected when the data is received.
  • incom- ing data words are received one after an other and each is firstly checked for transmission errors. If an error is detected, a counter is reset and then n error free transmissions must occur and be recorded by the counter otherwise the computer system is reset. This will be explained in more detail with reference to the flow chart shown in the accompanying drawing.
  • Incoming data words are checked for errors at stage 1 and the result of the error check is determined at stage 2. If the data word is error free the system looks at the state of the counter at stage 3. If the counter is at its maximum value as determined at stage 4, this indicates that at least ri error free loads have been received and the system can continue. A fault flag is set to zero at stage 5 and the data accepted. If, however, the counter is not at its maximum value, this indicates that care must be exercised as an error may have occurred or the system is still in the initial stages of accepting its first n data words. The count ⁇ er is incremented at stage 6, the data word is accepted and the monitoring system goes back to the beginning ready to check the next data word.
  • the counter is reset to zero and the fault flag is interrogated as indicated at stage 8. If the fault flag is zero as determined at stage 9, it is set to "1" at stage 10, the data word in error is rejected and the monitoring system goes back to stage 1 ready to check the next data word. If the fault flag is not zero as determined at stage 9 this indicates that less than n error-free data words have been received immediately preceding the data word in error. This results in the computer system of which the monitoring system is part being placed in a predetermined condition e.g. reset or commencing an error correction routine if this is appropriate.
  • a predetermined condition e.g. reset or commencing an error correction routine if this is appropriate.
  • the minimum number of error-free words re ⁇ ceived by the monitoring system can depend on the importance of the data. Thus important data may re ⁇ quire a larger number of error free words between errors than less important data. In other words, for important data the error frequency must be less. It is possible to modify the monitoring system in a number of ways. The above description assumes that the counter will be reset to zero when a word in error is detected and will then be incremented by each subsequent error-free word. It is possible to reverse this so that the counter will be set to a predetermined value e.g. n when a word in error is detected and the decremented to another value e.g. zero by each subsequent error-free word.
  • serial communications systems can be utilized in safety systems e.g. an airbag control unit, with a high immunity from random errors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

Dans un système de communications sériel, on contrôle les données entrées afin de détecter des erreurs. Une fois l'erreur détectée, au moins n transmissions sans erreur doivent être reçues, sans quoi le système est remis à zéro. Le nombre n est élevé pour des données importantes, faible pour des données moins importante et modifiable, si nécessaire selon le nombre d'erreurs détectées. Les données peuvent se présenter sous la forme de mots ou de bits individuels.
PCT/EP1988/000501 1988-06-06 1988-06-06 Procede de controle d'erreurs dans des donnees WO1989012272A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/EP1988/000501 WO1989012272A1 (fr) 1988-06-06 1988-06-06 Procede de controle d'erreurs dans des donnees

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP1988/000501 WO1989012272A1 (fr) 1988-06-06 1988-06-06 Procede de controle d'erreurs dans des donnees

Publications (1)

Publication Number Publication Date
WO1989012272A1 true WO1989012272A1 (fr) 1989-12-14

Family

ID=8165285

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1988/000501 WO1989012272A1 (fr) 1988-06-06 1988-06-06 Procede de controle d'erreurs dans des donnees

Country Status (1)

Country Link
WO (1) WO1989012272A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0575854A2 (fr) * 1992-06-17 1993-12-29 Sumitomo Electric Industries, Ltd. Circuit de surveillance mutuelle pour ordinateurs

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2019622A (en) * 1978-04-14 1979-10-31 Lucas Industries Ltd Digital computing apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2019622A (en) * 1978-04-14 1979-10-31 Lucas Industries Ltd Digital computing apparatus

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, volume 27, no. 5, October 1984, (New York, US), R.S. Crouse et al.: "Self-healing RAM management algorithm", pages 2762-2763 *
IBM Technical Disclosure Bulletin, volume 28, no. 11, April 1986, (New York, US), "Good/bad counter handling", pages 4741-4742 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0575854A2 (fr) * 1992-06-17 1993-12-29 Sumitomo Electric Industries, Ltd. Circuit de surveillance mutuelle pour ordinateurs
EP0575854A3 (fr) * 1992-06-17 1994-04-13 Sumitomo Electric Industries

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