WO1989004029A1

WO1989004029A1 - Intrusion detector

Info

Publication number: WO1989004029A1
Application number: PCT/GB1988/000899
Authority: WO
Inventors: John Michael Greasley
Original assignee: Greasley Electronics Limited
Priority date: 1987-10-27
Filing date: 1988-10-26
Publication date: 1989-05-05
Also published as: GB8725101D0

Abstract

An intrusion detector (2) has a sensor (4) which is responsive to the vibration and tilting of an accessway, such as a door or window, brought about by the attempts of an intruder to gain entry to a premises. An alarm sounder (170) is activated when a sounder activation means (160) is triggered by trigger circuitry (6). The trigger circuitry (6) triggers on the detection of an intruder. A buffer (8) prevents spurious stimulation of the sensor (4) by wind buffeting, passing vehicular traffic etc. from causing the trigger circuitry (6) to trigger.

Description

TITLE

Intrusion Detector

DESCRIPTION

Field of the Invention

The invention relates to alarm system intrusion detectors.

Background Art

An alarm system may be provided with a series of detectors which are distributed throughout a protected premises to detect the presence of an intruder and consequently trigger an alarm sounder. The alarm sounder may be integral with the detector and operate as an independent unit, or the detector may.be linked by an appropriate means to a central alarm system. In either case the detector usually guards a potential point of entry such as a door or window. Entry points have in the past been guarded by detectors which utilise tilt and/or vibration sensitive switches to detect interference with an access way. Mercury tilt switches are a prime example, and may be used to prevent intruders from entering, for example, upwardly pivoting doors such as those commonly found on domestic garages. When the door is pivoted upwards the mercury contained within the switch switch form a contact and complete an alarm trigger circuit, thereby warning of intrusion. Similar devices may be adopted for the protection of windows. However, switches of this type rely upon the displacement of mercury to form a contact, and they would consequently suffer from the disadvantage that in order to be sufficiently sensitive to the presence of an intruder, they may also be sensitive to spurious vibrations due, for instance, to wind buffeting and resonance. Spurious vibrations of this nature can often result in the accidental triggering of the sounder. The Invention

The invention provides an alarm system intrusion detector comprising a sensor capable of emitting a signal when stimulated by vibration or tilting, buffering circuitry for producing a triggering output only in response to stimulation of the sensor for more than a predetermined duration, trigger circuitry for producing an alarm enabling output in response to the triggering output of the buffering circuitry, for communicating the alarm enabling output of the trigger circuitry to a sounder.

A vibration and tilt stimulated sensor, switches and generates a signal in response to vibrations when the sensor is level or at an angle less than a threshold tilt angle, and permanently closes at angles in excess of that threshold angle.

The buffering means prevents spurious vibrations from accidentally triggering the alarm. Spurious vibrations, which in the case of a door could be the buffeting that the closed door would receive from the wind, and in the case of a window could be the reasonant vibrations caused by passing vehiclar traffic, last for only a limited duration. The vibrations or tilting of a door or window caused by an intruder tend on the other hand to be of a sustained devation. So by isolating the sensor from the trigger circuitry for a predetermined duration after the initial stimulation of the sensor, which duration is dictated by the minimum possible time required by an intruder to gain entry,it is possible effectively to filter out and differentiate spurious vibrations from intruder generated vibrations.

The buffering means which achieves the above filtering preferably comprises a resistive/capacitive network. By adjusting the resistance and capacitance values of the network it is possible to vary the duration of isolation.

The means for communicating the alarm enabling output to the sounder may include a sweep frequency oscillator capable of driving a loud speaker, or the sounder may incorporate an integral oscillator.

The detector is preferably armed by means of a key switch, and equipped with means for disabling the trigger circuitry for a predetermined period following the arming of the detector.

The detector preferably further comprises means for holding the sounder 'on' by holding the output of the trigger circuitry at the alarm enabling level for a predetermined duration, after termination of the triggering output of the buffering circuitry, the detector may also include means for testing the power supply to the detector as it is being armed.

The Drawings

Figure 1 is a block schematic of an intrusion detector according to the invention;

Figure 2 is a block schematic of the circuit layout of an intrusion detector according to the invention;

Figure 3 is a diagram of the arming, sensing, buffering, triggering and holding circuitry of an intrusion detector according to the invention;

Figure 4 is a circuit diagram of a means for communicating an alarm enabling output to a sounder, in a detector according to the invention; and

Figure 5 is a circuit diagram of an alternative means for communicating an alarm enabling output to a sounder, in a detector according to the invention. Best Mode

With reference to Figures l and 2, an intrusion detector indicated generally at 2 has a sensor 4, trigger circuitry 6 , a buffer 8, means 10 for communicating an alarm enabling output to a sounder, and a sounder 16. The trigger circuitry 6 has an arming delay 60 , a trigger 70, and a trigger hold 80. power is supplied to the detector 2 through an arming device 200. The buffer 8 interconnects the sensor 4 and the trigger 70. The arming delay 60 is disposed between the arming device 200 and the trigger 70. The trigger hold 80 is disposed between the trigger 70 and the sounder communicating means 10, which drives the sounder 16. Disposed between the arming device 200 and the communication means 10 is a power supply tester 210.

With reference to Figure 3, the detector 2 is armed by means of an arming device 200, which is preferably a key switch, placing the positive rail at +V volts. The trigger 70 consists of a NAND gate Nl, a resistor R3 and a pfi transistor Tl. Immediately after arming, the first input to the NAND gate Nl is at zero volts, as dictated by the voltage across the capacitor C2. As time progresses the capacitor C2 charges up and the voltage across the capacitor C2 gradually increases until the first input to the NAND gate Nl is effectively at logic 1. In order to switch on the transistor Tl, the output from NAND gate Nl must drop to logic 0, but because of the characteristics of a NAND gate, this is not possible while either input is at logic 0. The resistor R2 and the capacitor C2 therefore act as an arming delay, the arming delay 60 , and delay the trigger from operating for a time determined by the charge time of the capacitor C2, usually of the order of twenty seconds.

The sensor 4 is preferably a steel cased tilt/jilter switch manufactured by Saunders-Roe Developments Limited, who offer a range of switches having a range of sensitivities and tilt angles. When stimulated by vibration the sensor 4 switches to produce an alternating current signal of a resonant frequency. When tilted beyond the threshold angle the sensor produces a DC output.

When the detector is used to detect intruder entry through windows and doors, spurious stimulation of the sensor is caused by for example, the vibrations produced by wind buffeting or passing vehicular traffic. Spurious vibrations tend to be of a limited duration, whereas the vibrations originating from an intruder attempting to gain entry tend relatively to be sustained; for example, repeated impacts upon a double glazed window. The buffer 8 allows only sustained stimulations of the sensor 4 to cause the trigger 70 to trigger, and therefore filters out and differentiates between spurious and genuine stimulation of the sensor 4.

The buffer 8 consists of a resistive/capacitive network made up from the resistor Rl, the capacitor Cl, the potentiometer PI, and the diode Dl. The relative values of the resistor Rl, the capacitor Cl and the potentiometer PI are chosen such that during the time the sensor 4 is stimulated, charge accumulates on the capacitor Cl. Such a configuration is commonly known as a residual charge pump.

The positive portion of the alternating current signal produced by the sensor 4 charges the capacitor Cl through the potentiometer Pi. During the negative cycle of the signal, the capacitor discharges through the diode Dl and the resistor Rl to ground. The values of the capacitor Cl, the resistor Rl and the potentometer Pi are chosen such that the capacitor Cl never fully discharges during the time the sensor 4 is being stimulated. Hence, over a period of stimulation of the sensor 4, the capacitor Cl accumulates charge and the voltage across the capacitor Cl increases. If the sensor is stimulated for a sufficient period, the voltage across the capacitor Cl will eventually reach a voltage equivalent to a logic 1 voltage This voltage is inputted to the second input of NAND gate Nl. Until that time the trigger 70 is isolated from the sensor 4 by the buffer 8. The first input to the NAND gate Nl is held at a logic 1 voltage by the capacitor C2, so that when the voltage across the capacitor Cl also reaches a logic l voltage, the output of the NAND gate Nl will switch to a logic state 0 and the transistor Tl will turn on i.e. the trigger 70 (N1,R3,T1) triggers. If on the other hand the sensor is not stimulated for a sufficient period, the capacitor will never accumulate a voltage equivalent to a logic 1 voltage and the trigger 70 will not trigger. It can be seen therefore that the buffer 8 (Rl.Pl.Cl.Dl) prevents spurious stimulation of the sensor 4 from triggering the trigger 70 (Nl,R3,Tl).

When used to protect windwos, the detector has to be considerably more sensitive than when used to protect doors, and particularly upwardly pivoting doors. Vibrations established within a pane of glass tend to be dampened more rapidly than those established in a sheet metal door for example. In order therefore for the window detector to be sensitive to intruder originating vibrations, the time permitted for an accumulation of charge on the capacitor Cl sufficient to trigger the trigger 70, has to be relatively quicker than the permitted charge accumulation time upon which the door detector operates, i.e. the duration of isolation of the buffer 8 is relatively shorter. This is achieved by choosing appropriate values for the capacitor Cl, the resistor Rl and the potentometer Pi. When used as a window entry detector the capacitor Cl is of the order of 50pF, Pi is of the order of lOOfl, and Rl is of the order of LOMQ. When used as a door entry detector Cl is of the order of 3μF, Pi is of the order IMO, and Rl is of the order of lOOKfl. The charge time may be further critically adjusted by manually varying the potentiometer PI.

When the trigger 70 triggers and the transistor Tl switches on, the capacitor C3 charges up to +V volts through the resistor R4. A diode D2 electrically connects the positive electrode of the capacitor C3 and a point A. The point A assumes the voltage on the positive plate of the capacitor C3, dropped across a resistor R5. It is the voltage at the point A which switches the communicating means 10 and dictates whether the sounder 16 is enabled. In order to enable the sounder 16 the voltage at A must be a voltage equivalent to a logic 1.

The power supply tester 210 consists of a capacitor C4 and a resistor R5. When the detector 2 is initially armed and the positive rail is placed at +V volts, all of the positive rail voltage falls across the resistor R5 and the point A assumes a voltage of +V volts. Gradually the capacitor C4 will charge up and the voltage across the resistor R5, and hence that at point A, will decrease to zero volts. During the time for which the voltage across the resistor R5 is greater than a logic l voltage, usually a matter of seconds, the communicating means will turn on arid the sounder 16 will be activated proving that the power supply is of sufficient strength. If the power supply is defective, the sounder 16 will warn of a defect by failing the sound.

It is obviously desireable to have the sounder 16 continue to sound for a considerable period once it has been triggered. It may be possible for an intruder to gain entry to a premises in say twenty seconds and he may produce sufficient stimulation to cause triggering of the trigger 70 for only a portion of this time, unless the sensor 4 is permanently tilted in which case the triggering is continual. An alarm of only twenty seconds duration may not rapidly be identifiable as an intrusion. It is therefore essential to hold the sounder 16 enabled for a lengthy duration once it has been triggered.

The capacitor C3, the diode D2 and the resistor R5 acts as the trigger hold 80. When the trigger 70 triggers, and the voltage across the capacitor C3 reaches a voltage equivalent to a logic 1 voltage, the sounder 16 will sound. The voltage across the capacitor C3 will remain stable at +V volts for as long as the transistor Tl remains switched on. Once the triggering of the trigger 70 ceases and the transistor Tl switches off, the capacitor C3 will start to discharge through the diode D2 and the resistor R5 to ground.

Despite the fact that the transistor Tl has switched off, the sounder 16 will be enabled for as long as the voltage on the positive electrode of the capacitor C3 , and hence at the point A across the resistor R5, is greater than a logic 1 voltage. Capacitance and resistance values are chosen so that the point A is preferably held at a logic 1 voltage for 200 seconds.

The interconnections which are made between the communicating means 10 of figures 4 and 5 and the trigger circuitry 6 of figure 3 are marked X,Y and A.

Figure 4 depicts a first embodiment of the sounder and means means for communicating an alarm enabling signal 10. The communicating means 10 consists of a NAND gate N2, a current limiting resistor R6, and a pnp transistor T2. Both inputs to the NAND gate N2 are connected to the point A, so the gate N2 effectively acts as a NOT gate. When the voltage at point A reaches a logic l voltage, the output from the NAND gate N2 drops to zero volts, and the transistor T2 switches on thereby connecting the sounder Si to the positive voltage rail. The sounder SI contains its own oscillator and associated circuitry which drives a loud speaker.

An alternative embodiment of the enabling signal communicating means 10 is depicted in Figure 5. The communication means 10 consists of a pair of oscillators and a pnp transistor T3. Each oscillator has respectively a NAND gate N20; N21, a negative feedback loop consisting of resistor R5, capacitor C5; potentiometer P2, resistor R , capacitor C7. The first in the series of the oscillators is a low frequency oscillator operating at about 1Hz, and the second in the series is a high frequency oscillator operating at about 3KHz. The operating frequency of each oscillator is dependent upon the charge time of the relevant capacitor C5; C7 in each feedback loop. Each oscillator produces a square wave output.

The sounder 16 is enabled when the voltage at the point A reaches a logic 1 voltage. This voltage is inputted to each of the second inputs to the NAND gates N20, N21 respectively, and the oscillators are set into motion. The 1Hz square wave output from the first NAND gate N20 is rounded by and charges up through a resistor R7, a capacitor C6, intermediate the two NAND gates N20, N21. The rounded voltage waveform across the capacitor C6 is superimposed through a resistor R8 upon the negative feedback loop voltage applied to the second input of the seocnd NAND gate N21, so as to sweep the 3KHz frequency of the NAND gate N21 and produce an output frequency from the NAND gate N21 varying between 2.7KHz and 3.3 KHz. A diode D3 prevents any reverse flow of current from the NAND gate N2l to the NAND gate N20. The transistor T3 is alternately switched on and off by the NAND gate N21 whose output is fed to the transistor T3 through a current limiting resistor Rio. The alternating action of the transistor T3 supplies an alternating driving voltage from the positive rail to a sounder S2 which is a loud speaker. The loud speaker S2 is connected in series with an inductor Ll to produce a large driving EMF as the driving current alternates. A diode D4 protects the transistor T3 from any damaging back EMF.

It is feasible in either embodiment of the communicating means 10 described above for the sounder 16 to be remote from the detector 2. in such a case the detector 2 would also contain some form of remote transmitting device, such as a radio transmitter.

Claims

1. An alarm system intrusion detector comprising a sensor capable of emitting a signal when stimulated by vibration or tilting, buffering circuitry for producing a triggering output only in response to stimulation of the sensor for more than a predetermined duration, trigger circuitry for producing an alarm enabling output in response to the triggering output of the buffering circuitry, for communicating the alarm enabling output of the trigger circuitry to a sounder.

2. An intrusion detector according to claim l, wherein the buffering means consists of a resistive/capacitive network configured to accumulate residual charge during the time the sensor is stimulated.

3. An intrusion detector according to claim l or claim 2, wherein the means for communicating the alarm enabling output to the sounder includes a sweep frequency oscillator.

4. An intrusion detector according to claim l or claim 2, wherein the sounder includes an oscillator.

5. An intrusion detector according to claim 3 or claim 5, wherein the sounder is remote from the intrusion detector.

6. An intrusion detector according to any preceding claim, further comprising means for arming the detector, and means for disabling the trigger circuitry for a predetermined period immediately following the arming of the detector.

7. An intrusion detector according to any preceding claim, wherein the trigger circuitry further comprises means for holding the alarm enabling output at an alarm enabling level for a predetermined duration after termination of the triggering output of the buffering circuitry.

8. An intrusion detector according to any preceding claim, further comprising means for testing the power supply to the detector as the detector is being armed.