GB2231696A - Intrusion detector - Google Patents

Abstract

An intrusion detector 2 has a mercury switch 4 which is responsive to the vibration and tilting of an accessway, such as a door or window, brought about by the attempts of an intruder to gain entry to a premises. An alarm sounder 16 is activated when a sounder activation means is triggered by trigger circuitry 6. The trigger circuitry 6 triggers on the detection of an intruder. Buffering circuitry 8 prevents spurious stimulation of the switch 4, by wind buffeting, passing vehicular traffic etc. from causing the trigger circuitry 6 to trigger, by producing an output in excess of a triggering level only in response to a closure of the mercury switch for a time in excess of a predetermined duration. <IMAGE>

Description

TITLE Intrusion Detector DESCRIPTION Field of the Invention The invention relates to alarm system intrusion detectors.

Background Art An alarm system may be provided with a series of detectors which are distributed throughout a protected premises to detect the presence of an intruder and consequently trigger an alarm sounder. The alarm sounder may be integral with the detector and operate as an independent unit, or linked by an appropriate means, such as a radio transmitter, to a central alarm system. In either case the detector usually guards against forced entry through, for example, a door or window.

In the past, tilt and/or vibration sensitive switches have been used to detect forced entry into premises. For example, mercury tilt switches may be used to prevent intruders from entering through upwardly pivoting doors such as those commonly found on domestic garages. A globule of mercury contained within the switch is displaced by the pivotting action of the door and completes an alarm trigger circuit, which in turn operates an alarm sounder. Similar devices may be adopted for the protection of windows.

Conventional mercury switches suffer from the disadvantage that they may be sensitive, in addition to the presence of an intruder, to spurious stimuli due, for instance, to wind buffeting and resonance.

The Invention The invention provides an alarm system intrusion detector comprising a mercury switch stimulated by vibration or tilting to close for a duration determined by the magnitude of the stimulus to which the switch is subjected, buffering circuitry for producing an output in excess of a triggering level only in response to a closure of the mercury switch for a time in excess of a predetermined duration, trigger circuitry for producing an alarm enabling output in response to an output of the buffering circuitry in excess of the triggering level, and means for communicating the alarm enabling output of the trigger circuitry to a sounder.

A vibration or tilt stimulated mercury switch closes repeatedly in response to impact or vibration when the switch is level or at an angle less than a threshold tilt angle, and permanently closes whilst tilted at angles in excess of that threshold angle. The duration of each successive closure gradually diminishes with time. The duration of the initial closure is directly proportional to the magnitude of the impact or vibration stimulus to which the switch is subjected.

The buffering circuitry prevents spurious stimuli from accidentally triggering the alarm. Spurious stimului, which in the case of a door could be the buffeting that the closed door would receive from the wind, and in the case of a window could be the resonant vibrations caused by passing vehicular traffic, are generally smaller in magnitude than the vibration or tilting of a door or window caused by an intruder. The duration of each closure of the mercury switch is proportional to the magnitude of the stimulus to which the sensor is subjected, and so by isolating the switch from the trigger circuitry for a predetermined duration, which is dictated by the minimum possible duration of closure of the mercury switch in response to an intruder stimulus, it is possible effectively to filter out and differentiate spurious stimului from intruder generated stimului.

The buffering means which achieves the above filtering and differentiation preferably comprises a resistive/capacitive network. By adjusting the resistance and capacitance values of the network it is possible to vary the duration of isolation.

The means for communicating the alarm enabling output to the sounder may include a sweep frequency oscillator capable of driving a loud speaker, or the sounder may incorporate an integral oscillator.

The detector is preferably armed by means of a key switch, and equipped with means for disabling the trigger circuitry for a predetermined period following the arming of the detector.

The detector preferably further comprises means for holding the sounder 'on' by holding the output of the trigger circuitry at the alarm enabling level for a predetermined duration after termination of the triggering output of the buffering circuitry. The detector may also include means for testing the power supply to the detector when it is being armed.

The Drawings Figure 1 is a block schematic of an intrusion detector according to the invention; Figure 2 is a block schematic of the circuit layout of an intrusion detector according to the invention; Figure 3 is a diagram of the arming, sensing, buffering, triggering and holding circuitry of an intrusion detector according to the invention; Figure 4 is a waveform diagram of the voltage forms appearing at the buffering circuitry in an intrusion detector according to the invention; Figure 5 is a circuit diagram of a means for communicating an alarm enabling output to a sounder a in a detector according to the invention; and Figure 6 is a circuit diagram of an alternative means for communicating an alarm enabling output to a sounder, in a detector according to the invention.

Best Mode With reference to Figures 1 and 2, an intrusion detector indicated generally at 2 has a mercury switch 4, trigger circuitry 6, buffering circuitry 8, means 10 for communicating an alarm enabling output to a sounder, and a sounder 16. The trigger circuitry 6 has an arming delay 60, a trigger 70, and a trigger hold 80. Power is supplied to the detector 2 through an arming device 200. The buffer 8 interconnects the switch 4 and the trigger 70. The arming delay 60 is disposed between the arming device 200 and the trigger 70. The trigger hold 80 is disposed between the trigger 70 and the sounder communicating means 10, which drives the sounder 16. Disposed between the arming device 200 and the communication means 10 is a power supply tester 210.

With reference to Figure 3, the detector 2 is armed by means of an arming device 200, which is preferably a key switch, placing the positive rail at +V volts. The trigger 70 consists of a NAND gate N1, a resistor R3 and a pnp transistor T1. Immediately after arming, the first input to the NAND gate N1 is at zero volts, as dictated by the voltage across the capacitor C2. As time progresses the capacitor C2 charges up and the voltage across the capacitor C2 gradually increases until the first input to the NAND gate N1 is effectively at logic 1. In order to switch the transistor T1 the output from NAND gate N1 must drop to logic 0, but because of the characteristics of a NAND gate, this is not possible while either input is at logic 0.The resistor R2 and the capacitor C2 therefore act as an arming delay, the arming delay 60, and delay the trigger 70 from operating for a time determined by the charge time of the capacitor C2, usually of the order of twenty seconds.

The mercury switch 4 is preferably a steel cased tilt/jitter switch manufactured by Saunders-Roe Developments Limited, who offer a range of switches having a range of sensitivities and tilt angles. When stimulated by vibration the switch 4 closes and opens repeatedly, and a series of square voltage pulses appear at the output of the switch 4. The duration of the initial closure of the switch 4, and the number of successive closures, is directly proportional to the magnitude of the vibration to which the switch 4 is subjected. The duration of each successive closure subsides with time until the switch eventually returns to the stable open position. The switch 4 closes permanently when tilted beyond a threshold tilt angle.

Spurious stimului, such as the vibrations produced by wind buffeting or passing vehicular traffic, tend, in compassion to the stimului originating from an intruder attempting to force an entry, to be of a considerably smaller magnitude.

Consider, for example, repeated impacts upon a double glazed window. The duration of the initial closure of the switch 4 in response to a spurious stimulus is therefore considerably smaller than the duration of a closure in response to a legitimate stimulus. The buffering circuitry 8 filters out and differentiates between spurious and legitimate stimulation of the switch 4. The buffering circuitry 8 allows only closures of the switch 4 in excess of a predetermined duration, to trigger the trigger 70.

The buffering circuitry 8 consists of a resistive/capacitive network made up from the resistor Ria the capacitor C1, the potentiometer P1, and the diode D1.

During any duration of closure of the switch 4, capacitor C1 is charged up through the potentiometer P1. As soon as the switch 4 opens, the capacitor C1 begins to discharge through the diode D1 and the resistor R1 to ground. The value of the resistor R1 is chosen so that the capacitor C1 discharges very rapidly, and virtually instantaneously.

The triggering level of the trigger 70 is dictated by the value of a logic 1 voltage to the NAND gate Nl. The trigger 70 will switch the transistor T1 if the switch 4 is closed for a sufficient duration and the capacitor C1 is permitted to charge up to a logic 1 voltage. The charging rate of the capacitor C1 is determined by the value of the potentiometer P1, which is manually adjustable. The charging rate can vary from a few milliseconds to several seconds, depending upon the application to which the detector is to be put.

Figure 4 exemplifies the operation of the buffering circuitry 8. Each of the waveforms (a) to (c) consists of a number of square pulses representing the voltage applied to the potentiometer P1 as a result of a closure of the switch 4, and the subsequent voltage Vc on the capacitor C1, in response to vibrations of differing magnitude.

Waveform 4(a) shows the response of the switch 4 to a single low impact vibration. The impact stimulates the switch 4 into seven successive closures of the order of 5-10 milliseconds each, and spanning 100 milliseconds in total. The potentiometer P1 is set such that for the duration of the closure of the switch 4, the capacitor C1 charges up to only a small fraction of the triggering level VT.

Waveform 4(b) shows the response of the switch 4 to a medium impact vibration. The impact stimulates the switch 4 into six successive closures each of the order of 10-50 milliseconds and spanning 500 milliseconds in total. Each successive closure is slightly shorter than the predecessor. For the duration of the closure of the switch 4 the capacitor C1 has nearly sufficient time to charge up to the triggering level VT.

Waveform 4(c) shows the response of the switch 4 to a large impact vibration. The impact stimulates the switch into nine successive closures each of the order of 50-200 milliseconds, and spanning 1 second in total. The capacitor C1 has sufficient time during the initial closure and several successive closures to charge up to and beyond the triggering level VT.

The sensitivity of the buffering circuitry 8 can be altered by setting the potentiometer P1 at a different value. At a certain maximum value of the potentiometer P1 there is a possibility of the capacitor C1 undergoing a pumping effect. Waveform 4(c) shows that the potentiometer P1 may be set to a value which does not allow the capacitor C1 sufficient time to charge up to the triggering level VT, even in response to a large impact, but the intervals between successive closures of the switch 4 are so short that despite the virtually instantaneous discharge time the capacitor may never fully discharge and the voltage Vcm on the capacitor C1 gradually rises to the triggering level over a number of closures.

When the switch 4 is tilted beyond the threshold tilt angle and closes permanently, the capacitor will charge up to the rail voltage of +V volts, which is in excess of the triggering voltage VT. Again, the time of charging will be dictated by the value of the potentiometer P1.

The potentiometer P1 can therefore be set to enable the buffering circuitry 8 to differentiate between spurious and legitimate stimulation of the switch 4 by the duration of closure of the switch 4. The potentiometer P1 would normally be set so that a closure of the switch 4 in response to the minimum possible magnitude of intruder originating vibration would provide sufficient time for the capacitor C1 to charge up to the triggering level.

The first input to the NAND gate N1 is held at a logic 1 voltage by the capacitor C2, so that when the voltage across the capacitor C1 also reaches a logic 1 voltage, the output of the NAND gate N1 will switch to a logic state 0 and the transistor T1 will turn on i.e. the trigger 70 (N1, R3, T1) triggers.

When the trigger 70 triggers and the transistor T1 switches on, the capacitor C3 charges up to +V volts through the resistor R4. A diode D2 electrically connects the positive electrode of the capacitor C3 and a point A. The point A assumes the voltage on the positive plate of the capacitor C3, dropped across a resistor R5. It is the voltage at the point A which switches the communicating means 10 and dictates whether the sounder 16 is enabled. In order to enable the sounder 16 the voltage at A must be a voltage equivalent to a logic 1.

The power supply tester 210 consists of a capacitor C4 and a resistor RS. When the detector 2 is initially armed and the positive rail is placed at +V volts, all of the positive rail voltage falls across the resistor R5 and the point A assumes a voltage of +V volts. Gradually the capacitor C4 will charge up and the voltage across the resistor R5, and hence that at point A, will decrease to zero volts. During the time for which the voltage across the resistor RS is greater than a logic 1 voltage, usually a matter of seconds, the communicating means will turn on It is obviously desireable to have the sounder 16 continue to sound for a considerable period once it has been triggered.It may be possible for an intruder to gain entry to a premises in say twenty seconds and he may produce sufficient stimulation to cause triggering of the trigger 70 for only a portion of this time, unless the sensor 4 is permanently tilted in which case the triggering is continual. An alarm of only twenty seconds duration may not rapidly be identifiable as an intrusion. It is therefore essential to hold the sounder 16 enabled for a lengthy duration once it has been triggered.

The capacitor C3, the diode D2 and the resistor R5 acts as the trigger hold 80. When the trigger 70 triggers9 and the voltage across the capacitor C3 reaches a voltage equivalent to a logic 1 voltage, the sounder 16 will sound.

The voltage across the capacitor C3 will remain stable at +V volts for as long as the transistor T1 remains switched on. Once the triggering ot the trigger 70 ceases and the transistor T1 switches off, the capacitor C3 will start to discharge through the diode D2 and the resistor R5 to ground.

Despite the fact that the transistor T1 has switched off, the sounder 16 will be enabled for as long as the voltage on the positive electrode of the capacitor C3, and hence at the point A across the resistor R5, is greater than a logic 1 voltage. Capacitance and resistance values are chosen so that the point A is preferably held at a logic 1 voltage for 200 seconds.

The interconnections which are made between the communicating means 10 of figures 5 and 6 and the trigger circuitry 6 of figure 3 are marked X,Y and A.

Figure 5 depicts a first embodiment of the sounder and means means for communicating an alarm enabling signal 1D.

The communicating means lo consists of a NAND gate N2, a current limiting resistor R6, and a pnp transistor T2. Both inputs to the NAND gate N2 are connected to the point A, so the gate N2 effectively acts as a NOT gate. When the voltage at point A reaches a logic 1 voltage, the output from the NAND gate N2 drops to zero volts, and the transistor T2 switches on thereby connecting the sounder S1 to the positive voltage rail. The sounder S1 contains its own oscillator and associated circuitry which drives a loud speaker.

An alternative embodiment of the enabling signal communicating means lo is depicted in Figure 6. The communication means 10 consists of a pair of oscillators and a pnp transistor T3. Each oscillator has respectively a NAND gate N20; N21, a negative feedback loop consisting of resistor R5, capacitor C5; potentiometer P2, resistor R9, capacitor C7. The first in the series of the oscillators is a low frequency oscillator operating at about 1Hz, and the second in the series is a high frequency oscillator operating at about 3KHz. The operating frequency of each oscillator is dependent upon the charge time of the relevant capacitor C5; C7 in each feedback loop. Each oscillator produces a square wave output.

The sounder 16 is enabled when the voltage at the point A reaches a logic 1 voltage. This voltage is inputted to each of the second inputs to the NAND gates N20, N21 respectively, and the oscillators are set into motion. The 1Hz square wave output from the first NAND gate N20 is rounded by and charges up through a resistor R7, a capacitor C6, intermediate the two NAND gates N20, N21. The rounded voltage waveform across the capacitor C6 is superimposed through a resistor R8 upon the negative feedback loop voltage applied to the second input of the seocnd NAND gate N21, so as to sweep the 3KHz frequency of the NAND gate N21 and produce an output frequency from the NAND gate N21 varying between 2.7KHz and 3.3 KHz. A diode D3 prevents any reverse flow of current from the NAND gate N21 to the NAND gate N20.

The transistor T3 is alternately switched on and off by the NAND gate N21 whose output is fed to the transistor T3 through a current limiting resistor Rlo. The alternating action of the transistor T3 supplies an alternating driving voltage from the positive rail to a sounder S2 which is a loud speaker. The loud speaker S2 is connected in series with an inductor L1 to produce a large driving EMF as the driving current alternates. A diode D4 protects the transistor T3 from any damaging back EMF.

It is feasible in either embodiment of the communicating means 10 described above for the sounder 16 to be remote from the detector 2. In such a case the detector 2 would also contain some form of remote transmitting device, such as a radio transmitter.

Claims (8)

1. An alarm system intrusion detector comprising a mercury switch stimulated by vibration or tilting to close for a duration determined by the magnitude of the stimulus to which the switch is subjected, buffering circuitry for producing an output in excess of a triggering level only in response to a closure of the mercury switch for a time in excess of a predetermined duration, trigger circuitry for producing an alarm enabling output in response to an output of the buffering circuitry in excess of the triggering level, and means for communicating the alarm enabling output of the trigger circuitry to a sounder.

2. An intrusion detector according to claim 1, wherein the buffering circuitry consists of a resistive/capacitive network having a virtually instantaneous discharge time.

3. An intrusion detector according to claim 1 or claim 2, wherein the means for communicating the alarm enabling output to a sounder includes a sweep frequency oscillator.

4. An intrusion detector according to claim 1 or claim 2, wherein the sounder includes an oscillator.

5. An intrusion detector according to claim 3 or claim 5,' wherein the sounder is remote from the intrusion detector.

6. An intrusion detector according to any preceding claim, further comprising means for arming the detector, and means for disabling the trigger circuitry for a predetermined period immediately following the arming of the detector.

7. An intrusion detector according to any preceding claim, wherein the trigger circuitry further comprises means for holding the alarm enabling output at the alarm enabling level for a predetermined time after the termination of the triggering output of the buffering circuitry.

8. An intrusion detector according to any preceding claim, further comprising means for testing the power supply to the detector whilst the detector is being armed.