WO1989002678A1

WO1989002678A1 - Logic circuits

Info

Publication number: WO1989002678A1
Application number: PCT/GB1987/000631
Authority: WO
Inventors: Peter Henry Saul
Original assignee: Plessey Overseas Limited
Priority date: 1986-07-02
Filing date: 1987-09-09
Publication date: 1989-03-23

Abstract

An integrated logic circuit comprising bipolar transistors (16, 18) and junction field-effect transistors (12, 14). The junction field-effect transistors (12, 14) are arranged in the circuit to serve as switching elements, the gates being connected to the bases of the respective bipolar transistors (16, 18). The channels of the junction field-effect transistors are formed in the integrated structure design as ''pinch'' resistors defined by a P or N doped region of the same or similar type to that used to define the sub-emitter base resistance in the bipolar transistors (16, 18).

Description

LOGIC CTRCUITS

The present invention relates to integrated logic circuits.

Integrated circuit technology employs a variety of well known processing techniques. The techniques are usually based on either bipolar or CMOS processing technology and strive to provide an optimum balance between conflicting operational design requirements for the chips. The conflicting requirements usually include maximising operational speed and packing density of the logic gates whilst also minimising the power required for chip operation.

An objective of the present invention is to provide an integrated logic circuit structure which lends itself to bipolar processing technology and which provides chips having fast operational speed, high packing density of logic gates and low power operation.

According to the present invention there is provided an integrated logic circuit comprising bipolar transistors and junction field-effect transistors; wherein the junction field-effect transistors are arranged in the circuit to serve as switching elements, the gates of the junction field-effect transistors being connected to the bases of the bipolar transistors.

In a preferred embodiment the junction field-effect transistors each have a P-channel and the bipolar transistors are each of the NPN type. In another embodiment the junction field-effect transistors each have an N-channel and the bipolar transistors are each of the PNP type. In one embodiment there is provided an integrated logic array comprising a plurality of logic circuits each of which comprises bipolar transistors and junction field-effect transistors, wherein the junction field-effect transistors are arranged in series relationship to one another and the bipolar transistors are arranged in parallel relationship to one another, the gate of each junction field-effect transistor being connected to the base of a respective one of the bipolar transistors.

In a further embodiment there is provided an integrated logic array comprising a plurality of logic circuits each of which comprises bipolar transistors and junction field-effect transistors, wherein the junction field-effect transistors are arranged in parallel relationship to one another and the bipolar transistors are arranged in series relationship to one another, the gate of each junction field-effect transistor being connected to the base of a respective one of the bipolar transistors.

In a preferred embodiment the channel of each of the junction field-effect transistors is formed in the integrated structure design as a "pinch" resistor.

In one embodiment the "pinch" resistor defining the channel is in the form of a P or N doped region of the same or similar type to that used to define the sub-emitter base resistance in the integrated NPN or PNP bipolar transistors.

Advantageously the "emitter" region is extended to separate two "base" regions normally defined in a bipolar transistor whereby the "base" regions become the source and drain, and the "emitter" the gate of the junction field-effect transistor. In one embodiment the channel of each of the junction field-effect transistors in the integrated chip structure has a thickness substantially within the range of 0.5 microns to 0.05 microns.

In a preferred embodiment the thickness of the channel of the junction field-effect transistor is 0.2 microns or less.

The present invention also provides a method of manufacturing an integrated logic device comprising the use of bipolar processing steps to form a bipolar transistor and a junction field-effect transistor within the integrated structure of the device, the channel of the junction field-effect transistor having a thickness less than 0.5 microns and being formed to function when in operation in a manner similar to that of a "pinch" resistor.

The present invention will be described further, by way of example, with reference to the accompanying drawings in which:-

Figure 1 is a circuit diagram of an integrated two input NOR gate according to an embodiment of the present invention;

Figure 2 is a circuit diagram of an integrated two input NAND gate according to an embodiment of the present invention;

Figure 3 is a cross sectional view through an integrated NPN transistor;

Figure 4 is a cross sectional view through a P-channel junction field-effect transistor according to an embodiment of the present invention;

Figure 5 is a cross secitonal view through pan of an integrated gate device of the type illustrated in Figure 1 ;

Figure 6A is a layout, in plan view, of pan of an integrated gate device of Figure 5; Figure 6B is a circuit diagram illustrating the interconnections corresponding to the layout of Figure 6 A;

Figure 7 is a circuit diagram of a static memory cell employing JFET-Bipolar logic configurations according to an embodiment of the present invention; and

Figure 8 is a circuit diagram of a CMOS-like random access memory cell employing JFET-Bipolar logic configurations according to an embodiment of the present invention.

Referring to the circuit diagram of Figure 1 there is illustrated a two input NOR gate comprising two NPN transistors 16 and 18, and two P-channel junction field-effect transistors (J-FET) 12 and 14. The gate of the J-FET 12 is connected to the base of the NPN transistor 16 and the gate of the J-FET 14 is connected to the base of the NPN transistor 18. The P-channels of the J-FETs 12 and 14 are connected between a power supply line 6 and the collectors of the NPN transistors 16 and 18. The emitter of the NPN transistors is grounded to a line 8, the collector being connected to an output line 20.

The gate of the J-FET 12 and the base of the NPN transistor 16 are arranged to receive simultaneously either high or low input signals applied along an input line 10. Similarly, the gate of the J-FET 14 and the base of the NPN transistor 18 receive simultaneously either a high or low input signal applied along an input line 11. By appropriate choice of voltage (V_BW + Δ) on the power supply line 6, the choice being dependent on the characteristics of the transistors 16 and 18 and 12 and 14 and on the desired speed of operation, the J-FETs 12 and 14 behave in operation as active switching elements of the gate circuit.

The circuit of Figure 1 has some similarities to CMOS devices in that both polarities of active device are available, and in each of the output logic states, there is no net current through the switch, i.e. as for CMOS the primary current term is in the charge and discharge of nodal capacitances.

As shown in the diagram, the power rail should be incrementally greater than one VBE, and should track VBE with temperature. This requirement is as for PL. Unlike PL, active drive is available in both high and low states, while standby current is very small, thus, like CMOS, the circuit will demand power for switching but save power in the static state. Again as for CMOS, it is possible to produce faster versions of a gate by powering up; either by device scaling or, as for PL, this might be conveniently carried out by increasing the power supply voltage.

The sink for static current is the base current of the NPN transistor and the gate current in the P-JFET when forward biassed. Both of these currents will be controlled by the power supply voltage, although it is emphasised that this control is no more difficult than for PL, and will probably be carried out in the same way. Where operation from a single battery cell is required, a series resistor may be used. Alternatively, logic could be stacked across a high voltage supply to further improve efficiency, as is often the case with PL.

In another embodiment (not shown) the integrated two input NOR gate may be designed by employing two n-channel junction field-effect transistors to replace the two P-channel junction field-effect transistors 12 and 14, and by replacing the two NPN transistors 16 and 18 by two PNP transistors.

Referring to the circuit diagram of Figure 2 there is illustrated an integrated two input NAND gate. The NAND gate includes two P-channel junction field-effect transistors 22, 24 the gate of each of which is connected to the base of a respective one of a pair of NPN transistors 26, 28. The transistors 22, 24 are arranged in parallel relationship having their P-channels connected in parallel between the supply line 6 and the collector of the NPN transistor 26. The NPN transistors 26, 28 are arranged in series relationship between an output line 30, which is connected to the collector of the NPN transistor 26, and the ground line 8.

In another embodiment (not shown) the integrated two input NAND gate may be designed by employing two N-channel junction field-effect transistors to replace the two P-channel junction field- effect transistors 22, 24 and by replacing the two NPN transistors 26, 28 by PNP transistors.

In order to realize the NOR gate and NAND gate circuit designs described above within a chip having a high packing density of gates and a relatively low power of operation use is made of "pinch" resistors within the chip design in a novel manner.

Fundamentally, all conceivable bipolar processes contain, without additional process stages, a pinch type resistor, of sheet resistivity typically between 5kohms and 30k ohms per square. Although usually this is measured, it is normally only used as a reference point for the estimation of base resistance. Since the current gain, hfe, is a controlled process parameter in virtually all bipolar processes, and the pinch resistance and transistor hfe are very closely linked, it may be argued that pinch resistance is in principle fairly well controlled. In addition, the temperature coefficient of pinch resistors is positive and usually similar to conventional base resistors (although not normally close enough for inter-type tracking).

The above considerations led us to the development of pinch resistors in low power logic circuits and to the realization that the pinch resistor structure, if the "emitter" region is used as a gate, is a P-channel JFET which is a device rarely used. However, we found that with small geometry processes, the characteristics are far superior to previous versions and it was possible to use the JFET as' an active switching element.

This in turn led to the integrated circuit designs referred to in Figures 1 and 2 and to illustrate this novel technique further reference is made to Figures 3 to 6.

Figure 3 illustrates a sectional view through a doped silicon layer defining a strandard NPN transistor. By altering the layout slightly a P-channel junction field-effect transistor (Figure 4) may be produced in place of the NPN transistor. Compared to the standard NPN transistor, in the P-channel junction field-effect transistor the emitter region is extended to separated the two base regions. The bases become, respectively, the source and the drain of the P-channel junction field effect transistor, while the emitter becomes the gate. The sub-emitter base resistance takes the form of a "pinch" resistor to form the P-channel. Figure 5 illustrates the manner in which part of the circuit design of Figure 1 is realized using the structures of Figures 3 and 4. The drain contact is not essential and could be removed to save area. The use of double (N+ and P+) polysilicon as an interconnect technology is known, but is particularly advantageous in the configuration of the invention as it reduces the number of contact holes needed and hence reduces the chip area per gate.

The plan layout of the chip configuration is illustrated in Figure 6A. As can be seen by comparing with Figures 3 to 5 the major difference between the layout of the NPN transistor and the P- channel field-effect transistor lies in the extended N+ doped "emitter" region which becomes the gate of the P-channel field-effect transistor. The extended N+ doped "emitter" region effectively separates off into two separate regions the P+ doped area which would otherwise define base regions which thereby become respectively the source and drain of the P-channel field-effect transistor.

It is our belief that the logic circuit described above in Figures 5, 6A and 6B has both self-powering advantages usually found in CMOS technology and the very low voltage operation advantages usually found in PL technology. Furthermore the logic circuit structure according to the present invention is we believe fully process compatible with standard bipolar processes, and is potentially faster than PL or CMOS gate structures. In addition the logic circuit structure according to the invention uses very few metal contacts and hence is of high yield. It will be appreciated that whereas Figures 5, 6A and 6B illustrated the structure of an inverter comprising a P-channel junction field-effect transistor and an NPN transistor, in other embodiments of the invention the inverter may comprise an N-channel junction field-effect transistor and a PNP transistor.

Although the present invention has been described with respect to particular embodiments, it should be understood that modifications may be effected within the scope of the invention. For example whereas Figure 1 is a 2-input NOR gate the concept could be extended to at least three inputs; and the JFETs may need to be ratioed as for CMOS, but are unlikely to be critical in this respect. Figure 2 shows the 2-input NAND gate. Multiple input gates will probably be operated in simplified form as in the most recent CMOS, possibly using transmission gates or even "domino" logic.

Different layouts of the circuits are possible in minimising chip area per gate. The cross-section of the proposed structures illustrates one very significant layout advantage (Figure 5). In a "double-poly silicon" process such as Plessey Process HE, poly silicon can be extensively used as the interconnect, with a large saving in the numbers of contacts from the metal layers. This is particularly true of JFET-bipolar logic, and will lead to very compact layouts.

Transistor parameters for the P-JFET have been shown to be relatively unimportant; the same is largely true of the NPN transistor. Series emitter resistance, often a problem in high speed circuits, will actually help operation of this circuit by avoiding "current-hogging" and generally reducing power rail voltage dependence. Gain at low currents is desirably high, since the circuit is intended for low current operation. Here again though, the complementary nature of the switch will help in adverse conditions.

Speed of operation is good and is adjustable to some extent via the power rail voltage. Assuming a standby of lOua, and an estimated 160fF output node capacitance of a 2-input, 2-output gate, over 100MHz should be possible without making allowance for the speed-up effect of the complementary gate. Saturation of the NPN transistor could slow the operation; if this becomes a problem, the addition of a "feedback emitter" claimp should help. Total power consumption (static) on the basis outlined above would be, for say 60,000 gates, 240mW. This is probably an upper limit, although more power will be used dynamically.

Radiation hardness, an increasingly important specification, should be good. The JFET is an inherently hard device, while the low supply voltage will eliminate the possibility of latch-up. Since the current will be limited ultimately by the JFET, the circuit should be particularly hard for most threats.

An embodiment of the present invention is illustrated in Figure 7 which shows the circuit diagram of a static memory cell using the JFET - Bipolar logic configuration. The memory element consists of two NPN type bipolar transistors T₁ and T₂ and two JFETs T₃ and T₄.

The JFETs are advantageously of the 'normally-off or 'enhancement' type as described above.

The transistors T₁ and T₂ are coupled together as a cross- coupled latch. The emitters of the transistors T₁ and T₂ are connected to a negative rail 40 kept at a fixed potential e.g. OV or which may be fed by a current source; the choice being dependent on the memory sensing circuitry.

On each of the transistors T₁ and T₂ a second emitter connection is provided, connected respectively to rails labelled 'bit line 42 and 'bit line' 44. An upper power rail 46 to the circuit can be conveniently used as a 'word line'. The operational sequency is:-

1. Writing a) The data to be written to the element is set on lines

'Bit line' 42 and 'Bit line" 44. One line is high and the other low relative to the negative rail 40.

b) Raise the word line potential.

c) If the bipolar transistor addressed by the low bit line is 'on', it will remain so.

d) If the bipolar transistor addressed by the low bit line is 'off, it will conduct current through the emitter connected to the bit line. This pulls the collector potential down, turning 'off the other half of the latch, and, by regenerative action, latching the side addressed 'on'.

Reading a) The bit lines are connected to a 'sense' amplifier which detects relative 'high' and 'low' levels. b) The word line is taken high.

c) The sense amplifier reads the data in the cell in a nondestructive way, i.e. the current taken from the cell is not sufficient to disturb the sense of the cell.

In the above description of the operational sequence the terms 'high' and 'low' refer to relative logic levels. The exact values will be determined by the circuitry not shown and will depend on the precise characteristics of the devices used.

The random-access bipolar memory cell makes use of very low standby power, occupies very small chip area and is capable of high speed.

A further embodiment of the present invention is illustrated in Figure 8 which shows the circuit diagram of a CMOS-like random access memory cell in a bipolar process. The circuit elements are NPN transistors T₁ and T₂ and P-channel JFETs. The circuit consists of the two bipolar transistors T₁ and T₂ and four JFET transistors T₃, T₄, T₅ and T₆. The circuit is powered through lines marked 'Ov' and 'V_cc'. The latter is maintained typically at V_be + Δ where V_be is the forward base-emitter voltage of the bipolar transistors and Δ is a small voltage, of the order of 10-50mV, but could be as high as 300mV.

In operation, the transistors T₁ to T₄ form a cross-coupled latch circuit. Transistors T₅ and T₆, when addressed by taking the word line low, connect the latch to the lines 'Bit' and 'Bit'. During the write operation, the bit and bit lines are set to appropriate 'high' or 'low' levels. In this context, high is approximately equivalent to Vcc and 'low' is approximately Ov.

When the word line is addressed by taking it low, the cell acquires the high/low combination of levels as set by the bit and bit lines, i.e. if bit is high and bit is low, T₂ turns on, turning T₁ off. Similarly, T₄ turns off, turning T₃ on i.e. the latch repeats the state of the bit lines. In general, it may be necessary to arrange T₅ and T₆ to be larger devices than T₃ and T₄ to ensure this condition. During read operations, the bit and bit lines connect to 'sense' amplifiers which buffer the outputs to the rest of the circuit. Enabling the word line, by taking it low, transfers data from the latch to the sense amplifier.

Advantages of this memory cell over conventional circuits are that much lower power is required than with bipolar memories and higher speed than CMOS memories. Addressing is also simpler than bipolar memories.

Claims

1. An integrated logic circuit comprising bipolar transistors and junction field-effect transistors (J-FETs); wherein the junction field-effect transistors are arranged in the circuit to serve as switching elements, the gates of the field-effect transistors being connected to the bases of the bipolar transistors.

2. An integrated logic circuit as claimed in claim 1 wherein the channels of the J-FETs are connected between a supply voltage line and the collectors of the bipolar transistors.

3. An integrated logic circuit as claimed in claim 1 or claim 2 wherein each of the J-FETs has a P-channel and each of the bipolar transistors is of the NPN type.

4. An integrated logic circuit as claimed in claim 1 or claim 2 wherein each of the J-FETs has an N-channel and each of the bipolar transistors is of the PNP type.

5. An integrated logic circuit as claimed in any one of claims 1 to 4 wherein the channels of the J-FETs are formed in the integrated structure design as "pinch" resistors.

6. An integrated logic circuit as claimed in claim 5 wherein the "pinch" resistor defining the channel is in the form of a doped region of the same or similar type to that used to define a sub-emitter base resistance in the integrated bipolar transistor.

7. An integrated logic circuit as claimed in any one of claims 1 to 6 wherein the thickness of the channel of the J-FET lies substantially within the range 0.5 micron to 0.05 micron.

8. An integrated logic circuit as claimed in any one of claims 1 to 6 wherein the thickness of the channel of the J-FET is 0.2 micron or less.

9. A logic array comprising a plurality of integrated logic circuits, each as claimed in any one of the preceding claims, wherein the junction field-effect transistors are arranged in series relationship to one another and the bipolar transistors are arranged in parallel relationship to one another, the gate of each field-effect transistor being connected to the base of a respective one of the bipolar transistors.

10. A logic array comprising a plurality of logic circuits, as claimed in any one of claims 1 to 6, wherein the junction field-effect transistors are arranged in parallel relationship to one another and the bipolar transistors are arranged in series relationship to one another, the gated of each field-effect transistor being connected to the base of a respective one of the bipolar transistors.

11. An integrated logic circuit constructed, adapted and arranged to operate substantially as hereinbefore described with reference to one or more of Figures 1, 2, 5, 6A and 6B of the accompanying drawings

12. A logic array comprising a plurality of integrated logic circuits as claimed in claim 9.

13. A method of manufacturing an integrated logic device comprising the use of bipolar processing steps to form a bipolar transistor and a junction field-effect transistor within the integrated structure of the device, the thickness of the channel of the junction field-effect transistor being less than 0.5 micron and the channel being formed in the integrated structure to function when in operation in a manner similar to a "pinch" resistor.

14. A static memory cell incorporating an integrated logic circuit as claimed in claim 1.

15. A static memory cell constructed, adapted and arranged to operate substantially as hereinbefore described with reference to Figure 7 of the accompanying drawings.

16. A random access memory cell incorporating an integrated logic circuit as claimed in claim 1.

17. A random access cell constructed, adapted and arranged to operate substantially as hereinbefore described with reference to Figure 8 of the accompanying drawings.