WO1989002125A1 - Systeme de detection d'erreur permettant le classement d'adresses d'instructions - Google Patents

Systeme de detection d'erreur permettant le classement d'adresses d'instructions Download PDF

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Publication number
WO1989002125A1
WO1989002125A1 PCT/US1988/002897 US8802897W WO8902125A1 WO 1989002125 A1 WO1989002125 A1 WO 1989002125A1 US 8802897 W US8802897 W US 8802897W WO 8902125 A1 WO8902125 A1 WO 8902125A1
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WIPO (PCT)
Prior art keywords
address
parity
instruction
sequence
error
Prior art date
Application number
PCT/US1988/002897
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English (en)
Inventor
Dongsun Robert Kim
Original Assignee
Unisys Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corporation filed Critical Unisys Corporation
Publication of WO1989002125A1 publication Critical patent/WO1989002125A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing

Definitions

  • This disclosure is related to the field of computer circuitry where instructions are stored in a control store unit and error detection means are provided for verifying the sequence of instruction addresses.
  • control store In present day computer circuitry, it is not uncommon to use a wide control store, for example, such as that having a magnitude of 32K words where each word has 200 bits and works in conjunction with a corresponding 200-bit output register (where K equals 1024).
  • the control store will normally hold and carry instruction words to be used by the computer circuitry and the instruction words can be addressed by a sequence of "instruction address data" which will access the relevant instruction words.
  • the instruction sequencing is done by generating the next instruction address through the use of the "next address field" of the present instruction as its "base data” , which is under the control of the next address select control field of the present instruction word.
  • next address select control fields of the presently existing instruction word can be designated as NAR (next address register) and as NASCR (next address select control register), and as CSR (condition select register) .
  • the NASCR no address select control register; field controls the selection of the next address from a number of different sources, depending upon which operation-sequence is to be performed.
  • the next . address field, • located in the next address register, WAR, may be used as the next instruction address without any changes in the case where the "uncondi ⁇ tional" branch operation is being used.
  • This next address may be generated by modifying a portion of the next address field by means of test conditions selected under control of the CSR field in the case of the "conditional" branch operations situation.
  • the next address (NA) may also be the "subroutine return address" (SRA) in the case of a return from a subroutine.
  • SRA subroutine return address
  • the next address may be the "initial address" for the new operator, in the case situation where the circuit has finished execution of the current operator and is prepared to enter the new-operator execution routine.
  • NA next instruction address
  • FIG. 1 is 'a block diagram of a system for incorpo ⁇ rating address sequence error detection circuitry in conjunction with an instruction control store in order to detect any errors in the instruction address sequences.
  • FIG. 2 is a diagram of the address sequence error detection logic used in conjunction with the instruction address control store circuitry.
  • a control store 40 may. be a memory structure f 32K words where each word is composed of 200 bits and provided with a 200-bit output register which may be designated as the combination of 41, 42, 43,
  • K is equal to 1024.
  • This control store 40 is serviced by the test conditions select logic unit 28, the next address select logic unit 33, the decoder 26, and the address sequence error detection logic 20 (ASEDL) which can generate an error flag designated as ASPEF. This can be designated as the address sequence parity error flag on line 19.
  • the control store 40 has an output register com ⁇ prised of a number of sections each having their own separate register.
  • the NAR, next address register 41 occupies the first section followed by the PRF or parity relation flag 42, the NASCR or next address select control register 43, the condition select register 44 (CSR), and a series of other command registers designated CR 45.
  • the command registers 45 provide an m-bit wide output bus 29 to control other elements in the system such as the arithmetic logic unit of the data path and other elements.
  • condition select register 44 provides an output bus (three sets of one line each) 27 over to the test condition select logic 28 to define which three test conditions are to be selected for th. ⁇ conditional branch cases. For example, these three conditions might be: (i) operand one is an integer; (ii) operand two is an integer; and (iii) in-teger overflow condition.
  • the next address select control register 43 (NASCR) provides a 2-bit bus output 25 to the decoder 26 to define what type of sequencing is to be carried out.
  • the parity relation flag 42 has but one output line 11 labeled PR which is sent to the address sequence error detection logic unit 20 for error detection.
  • the next address register 41 (NAR) has a 15-bit wide output bus 6 which is connected to the next address select logic unit 33 for the unconditional branch case.
  • the most significant 12-bit field, NA[14:12] designated 6b is concatenated with the 3-bit selected test conditions output bus 7 from the test condition select logic unit 28, in order to form the "next address for the conditional branch” case (NAC), designated 6b+7, and sent to the next address select logic unit 33. Additionally, the least significant 3-bit field 6a, NA[2:3], is sent to the address sequence error detection logic 20 for error detection.
  • the test conditions select logic unit 2- selects three conditions defined by the input lines 27 from the "n" test conditions input 30 that it receives from the various other parts of the system. Examples of these test condi- tions might be — types of operands; results of the ALU operation; status of memory cycles; etc. These three selected conditions on bus 7 are sent to the address sequence error detection logic unit 20 for processing. Additionally, these three lines form a part of the next address for the conditional branch case, NAC, as previously described above.
  • the decoder 26 decodes the two input lines 25 and generates four decoded lines which determine which sequencing operations are to be performed, such as: (i) select new initial instruction address for the next operator 26s; (ii) the subroutine return address 26r; (iii) the unconditional branch signal 8; and (iv) the conditional branch signal 9.
  • next address select logic unit 33 All of these four lines are sent to the next address select logic unit 33 for a proper selection of the next address.
  • the unconditional branch signal 8 and the conditional branch 9 signal lines are also sent to the address sequence error detection logic unit 20 for error detection.
  • the next address select logic unit 33 selects the proper next address from the four possible next addresses based upon the control input lines from the decoder unit 26.
  • the four possible next addresses are: (a) initial operator address 31; (b) the subroutine return address, SRA 32;
  • the selected next address becomes the new present address, PA, and is put upon the output bus 34.
  • This 15-bit output bus, PA 34 is sent to the control store 40 to access the next instruction word. Additionally, the output bus PA 34 is conveyed to the address sequence error detection logic unit 20 for error detection.
  • the key functional unit for this invention is the address sequence error detection logic unit 20 which is further described in connection with FIG. 2.
  • the input lines unconditional branch 8 and the conditional branch lines 9, from the decoder unit 26 of FIG. 1, are fed to the OR gate 10 to generate an output signal designated EASPED (enable address sequence parity error detection).
  • EASPED encodeable address sequence parity error detection
  • This EASPED signal is then fed to one input leg of the two-legged AND gate 17 to enable the error detection only during the unconditional branch case and the conditional branch case.
  • the unconditional branch 8 and the PR 11 are fed into the AND gate 12 to produce the output signal
  • the parity relation is needful of being altered and requires tracking of the relationship.
  • This function is performed by the exclusive OR gates 13a, 13b, and 13c, and 13d.
  • the three selected condition lines 7 of FIG. 2 are fed into the ' exclusive OR gate 13a to generate the output signal SCP (selected condition parity).
  • the SCP signal is then fed to one leg of the exclusive OR gate 13c.
  • the next address field NA[2:3] 6a (FIG. 1) are fed into the exclu ⁇ sive OR gate 13b to generate the output signal NAFP (next address field parity).
  • the NAFP signal is then fed to the other leg of the exclusive OR gate 13c.
  • CPR change in parity relation
  • the signal CPR is then fed to one leg of the exclusive OR gate 13d.
  • the original parity relation bit PR 11 is fed into the other leg of the exclusive OR gate 13d.
  • the output signal of the exclusive OR gate 13d is labeled NPRC (new parity relation for- conditional branch case) and this represents what the new parity relation should be for the conditional branch cases.
  • the NPRC signal and the conditional branch signal line 9 are fed to the AND gate 14 to produce the output signal designated PRC (parity relation for conditional branch). This PRC signal is then fed to the other leg of the OR gate 15.
  • the output signal of the OR gate 15, designated APSBDIFF address parity should be different
  • APSBDIFF address parity should be different
  • the input bus PA 34 present address
  • PAR 24 present address register, FIG. 2
  • the output of the PAR 24 is fed into the exclusive OR gate 22a.
  • the output of the exclusive OR gate 22a (labeled PPAP to designate previous present address parity) represents the parity of the previous present address and it is fed to one leg of the exclusive OR gate 22c.
  • the output signal of the exclusive OR gate 22b represents the parity of the "new" present address, and it is fed to the other leg of the exclusive OR gate 22c.
  • the exclusive OR gate 22c functions as a comparator of the parities of the "previous present address” and of the "new present address” and the output signal, labeled
  • APIDIFF represents the difference of these two parities, thus indicating that the address parity is different. Subsequently, this APIDIFF signal is fed to the other leg of the exclusive OR gate 16.
  • the exclusive OR gate 16 further functions as a comparator of the two input signals, ABSBDIFF and APIDIFF, and operates to produce the output signal desig ⁇ nated ASPE (address sequence parity error) thus indicating that a parity error has been detected in the address sequencing, if the sequencing operation is an "unconditional" branch or is a "conditional” branch case.
  • ASPE address sequence parity error
  • the ASPE signal is fed to the other leg of the AND gate 17.
  • the output signal of the AND gate 17 is labeled ASPED (address sequence parity error detected) which represents that a parity error has been detected in the address sequencing during the conditional or the uncon ⁇ ditional branch case, and this output signal is fed to the flip-flop 18 for latching the error condition.
  • the output signal of the flip-flop 18 is labeled ASPEF (address sequence parity error flag) 19 which is transmitted to the maintenance processor in order to report the error condi— tion and institute a possible recovery action.
  • FIGs. 1 and 2 In 'order to more clearly illustrate the disclosure, the following two examples will refer to FIGs. 1 and 2.
  • the first example is to deal with the "uncondi- tional" branch case and has the following situation:
  • the system has received state signals indicating that an "unconditional" branch sequencing should happen and goes to the address indicated by the NAR 41 of FIG. 1 as the next address.
  • - PAR 24 of FIG. 2 has a binary value of
  • - NAR 41 of FIG. 1 has a binary value of "000001111100001".
  • NASCR 43 of FIG. 1 has an encoded value representing the "unconditional" branch operation.
  • - CSR 44 of FIG. 1 has a binary value of all 0's since it is an unconditional branch case and it is not relevant for this example case.
  • test condition select logic 30 does not play any role since this is an uncondi ⁇ tional branch case.
  • the decoder 26 of FIG. 1 would decode the value of NASCR 43 of FIG. 1 and output signal 8 to "true” indicating the unconditional branch and decode all other lines to "false”.
  • the next address select logic 33 of FIG. 1 selects NA 6 of FIG. 1 and puts that informa- tion onto the output bus at PA 34 of FIG. 1.
  • OR gate 10 EASPED, is "true” since the unconditional branch signal 8 is “true”.
  • the output signal of the AND gate 12, PRU is “true” since the unconditional branch signal 8 is “true” and " the PR 11 is also “true”.
  • the output signal of the OR gate 15 APSBDIFF is also "true” indicating that the address parity should be different.
  • the output signal of the exclusive OR gate 22a, PPAP (previous present address parity), is “true” since the contents of the PAR 24 should be an "odd” parity.
  • the output signal of the exclusive OR gate 22b, NPAP (new present address parity) should be “false” indicating "even” parity if there was no error on PA 34. But it is “true” due to the error on PA 34 indicating “odd” parity.
  • the output signal of the exclusive OR gate 22c, APIDIFF is "false” indicating that the address parity is "not different".
  • the output signal of the exclusive OR gate 16, ASPE is "true because the APSBDIFF is “true” whereas the APIDIFF is “false”.
  • the output signal of the AND gate 17 is “true” because both the input signals, EASPED and ASPE, are “true” indicating that the address sequencing parity error has been detected. This error condition is captured in the flip-flop 18 on the next clock and the output signal, ASPEF, is sent to the maintenance processor for reporting and a possible recovery action.
  • the second example is to deal with the "conditional" branch case and has the following situation:
  • the system of FIG. 1 has received state signals indicating that a "conditional" branch sequencing should happen and it goes to the address of NAC 6b+7, formed by the base field of NAR, NA[14:12] 6b of. FIG. 1, concatenated with the three test conditions selected by lines 7 of FIG. 1, as the next address.
  • PAR 24 of FIG. 2 has a binary value of "000001111100000" indicating the address of the control store word accessed and I ⁇ aded into the registers 41-45.
  • - NAR 41 of FIG. 1 has a binary value of
  • CSR 44 of FIG. 1 has a binary value of "0001,0011,1111" indicating the select three test condi- tions addressed by these three values from the 16 test conditions. Note that these fields could be much larger if there were lots more test conditions to choose from. For ease of explanation, these particulars are chosen for this example. - "Other CR" 45 of FIG. 1 is not immediately relevant to these operations but could be used to control other associated circuitry.
  • the test condition select logic unit 28 of FIG. 1 selects three test conditions defined by the CSR 44 of FIG. 1, and for this example, assuming those three conditions are: "operand 1 is an integer”; "operand 2 is an integer”; and “integer overflow”, and furthermore, assuming all these selected conditions are "true” for this example.
  • the binary value of the selected condition lines 7 of FIG. 1 is "111" and the binary value of the NAC 6b+7 would be "000001111111111”.
  • the decoder 26 • of FIG. 1 would decode the value of NASCR 43 of FIG. 1 and output signal 9 to "true” indicating "conditional” branch and all other lines to "false”.
  • the next address select logic 33 of FIG. 1 selects NAC 6b+7 of FIG. 1 and places that information onto the output bus at PA 34 of FIGs.- 1, 2. Assuming here that an error exists in the next address select logic 33 of FIG.
  • OR gate 10 EASPED, is "true” since the "conditional" branch signal 9 is “true”.
  • the * output signal of the exclusive OR gate 13a, SCP is “true” indicating “odd” parity since all three input lines 7 are true ("111").
  • the output signal of the exclusive OR gate 13b, NAFP is “false” indicating "even” parity since the input bus 6a NA[2:3] has a binary value of "000".
  • NPRC output is also "true”.
  • the output signal of the OR gate 15, APSBDIFF, is also “true” since the PRC is “true” indicating that the address parity should be different.
  • the output signal of the exclusive OR gate 22a is “true” since the contents of the PAR 24 should be “odd” parity.
  • the output signal of the exclusive OR gate 22b, NPAP should be “false” indicating "even” parity if there was no error on PA 34. But it is “true”, due to the error on PA 34 indicating “odd” parity.
  • the output signal of the exclusive OR gate 22c, APIDIFF,. is "false” indicating that the address parity is "not different”.
  • the disclosed system detects address sequencing errors which would not have been detected in a conventional system and would have caused a severe system problem, such as data corruption, by execution of the wrong instruction.

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  • Engineering & Computer Science (AREA)
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  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
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Abstract

Une séquence d'adresses d'instructions accède à une mémoire microprogrammable comportant un grand nombre de mots d'instruction. Un système de coopération mutuelle permet de combiner une unité logique de sélection des conditions de test et une unité logique de détection d'erreur de séquence d'adresses, avec une logique de détection d'erreurs de séquence d'adresses, afin de mettre au point un signal indicateur d'erreur au cas où se produirait une erreur dans la séquence de données d'adresses d'instruction effective fournie à la mémoire microprogrammable.
PCT/US1988/002897 1987-08-31 1988-08-26 Systeme de detection d'erreur permettant le classement d'adresses d'instructions WO1989002125A1 (fr)

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US090,873 1987-08-31

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0842471A1 (fr) * 1995-07-31 1998-05-20 Verifone, Inc. Procede et appareil pour gerer des ressources sous la commande d'un module protege ou d'un autre processeur protege

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3192362A (en) * 1961-08-22 1965-06-29 Sperry Rand Corp Instruction counter with sequential address checking means
GB1038704A (en) * 1964-02-14 1966-08-10 Ibm A self-addressed data store
FR2346770A1 (fr) * 1976-03-30 1977-10-28 Honeywell Inf Systems Italia Appareil de commande microprogramme muni de moyens pour verifier l'adressage de la memoire de microprogrammation
US4074229A (en) * 1975-04-25 1978-02-14 Siemens Aktiengesellschaft Method for monitoring the sequential order of successive code signal groups

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3192362A (en) * 1961-08-22 1965-06-29 Sperry Rand Corp Instruction counter with sequential address checking means
GB1038704A (en) * 1964-02-14 1966-08-10 Ibm A self-addressed data store
US4074229A (en) * 1975-04-25 1978-02-14 Siemens Aktiengesellschaft Method for monitoring the sequential order of successive code signal groups
FR2346770A1 (fr) * 1976-03-30 1977-10-28 Honeywell Inf Systems Italia Appareil de commande microprogramme muni de moyens pour verifier l'adressage de la memoire de microprogrammation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0842471A1 (fr) * 1995-07-31 1998-05-20 Verifone, Inc. Procede et appareil pour gerer des ressources sous la commande d'un module protege ou d'un autre processeur protege
EP0842471A4 (fr) * 1995-07-31 2006-11-08 Hewlett Packard Co Procede et appareil pour gerer des ressources sous la commande d'un module protege ou d'un autre processeur protege

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