WO1988010468A1 - Plaquette de circuits multi-processeurs pouvant etre installee en exemplaires multiples dans des ordinateurs personnels et des bus d'expansion de postes de travail - Google Patents

Plaquette de circuits multi-processeurs pouvant etre installee en exemplaires multiples dans des ordinateurs personnels et des bus d'expansion de postes de travail Download PDF

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Publication number
WO1988010468A1
WO1988010468A1 PCT/US1988/002109 US8802109W WO8810468A1 WO 1988010468 A1 WO1988010468 A1 WO 1988010468A1 US 8802109 W US8802109 W US 8802109W WO 8810468 A1 WO8810468 A1 WO 8810468A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus
personal computer
workstation
circuit board
controlling element
Prior art date
Application number
PCT/US1988/002109
Other languages
English (en)
Inventor
Samuel Winston Bogoch
Original Assignee
Human Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Human Devices, Inc. filed Critical Human Devices, Inc.
Publication of WO1988010468A1 publication Critical patent/WO1988010468A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Definitions

  • the present invention employs a novel configuration of multiple microprocessors, memory and other circuitry to allow many personal computers to be upgraded to parallel processing with the installation of a single board containing many processors in the expansion bus of the personal computer, and allows for installation of as many of these boards as the logical and physical capacity of the expansion bus will allow.
  • the board is designed so that the internal logical organization of microprocessors on the board is reproduced at the level of boards within the PC expansion bus, and may be further reproduced as entire PC expansion buses within larger systems, and indeed at any hierarchical level.
  • One object of the present invention is to provide a circuit board which may be installed singly in the bus of a personal computer, thereby providing that personal computer with at least four additional processing elements, each capable of executing and manipulating data independently from the others.
  • circuit board be multiply installable in the bus of a personal computer, up to the physical capacity (number of slots) or logical capacity (number of memory- mapped and I/O mapped addresses) of the personal computer bus.
  • the board be designed so that logical organization and control structure of multiply-installed boards within the personal computer be logically similar to the logical organization and control structure of processing elements within one board.
  • the invention consists of a circuit board configuration containing a number of microprocessor systems, referred to as processing elements, and a common communications pathway, referred to as the board bus.
  • the circuit board also contains control circuitry and an interface to the bus in which the board is installed, referred to as the host processor bus.
  • Each processing element consists of at least one microprocessor integrated circuit, at least one memory integrated circuit and associated decoding and support circuitry, whose address, data and control lines are connected in what is referred to as the local bus. Additional circuitry such as additional memory, input/output or coprocessor integrated circuits may be included in the design of the processing elements, depending on performance requirements, but at the expense of compactness and low power consumption per element.
  • Each element must also contain a set of controllable bidirectional logic buffers, referred to as element buffers, which connect, address, data and control lines of the element's local bus to the corresponding lines on the board bus. If the element buffers are disabled, the local bus is isolated from the board bus, and the processing element can function independently.
  • the board bus serves as the communications pathway between processing elements.
  • An additional set of controllable bidirectional buffers referred to as the host processor buffers, connect address, data and control lines of the board bus to the corresponding lines on the host processor bus.
  • At least one processing element may contain additional circuitry to allow it to directly control the board bus and other processing elements on the board; this processing element is referred to as the controlling element.
  • the element buffers of the controlling element are referred to as the controlling element buffers.
  • the controlling element may also contain specialized circuitry to perform its DMA transfers at high speeds. as well as input-output circuitry to allow direct attachment to external devices without regard to the host processor bus.
  • address decoding circuitry to signal when the host processor is accessing the board, host buffers, to permit data and addresses to be transmitted between the host and board during said accesses, and a control register, associated control logic, and a set of element- select lines (one per element) and control lines, to arbitrate access to the board bus and processing elements.
  • a set of service-request lines may also be provided, to allow processing elements to request service routines to be performed by the controlling element.
  • a clock generator which generates a synchronous system clock for all processors on the board; this can be disabled in favor, of a host processor system clock in systems where synchronous operation between the host -processor and boards is desired.
  • Memory-mapped decoding may be employed for access to the processing elements by the controlling element, meaning that the memories of processing elements are mapped into logical memory regions of the controlling element.
  • Memory-mapped decoding may also be employed for access to the processing elements by the host processor, meaning that the memories of processing elements are mapped into logical memory regions of the host processor, although not necessarily with the same mapping as used for the controlling element.
  • Memory- mapped decoding is also employed for access to the controlling element by the host processor, meaning that the memory of the controlling element is mapped into a logical memory region of the host processor.
  • one or more input-output mapped registers may. be used to supplement the memory-mapped decoding.
  • FIG.l is a block diagram of the preferred embodiment, showing the logical arrangement of the processing elements, board bus and host processor bus. A configuration with one controlling element and four processing elements is illustrated as an example.
  • DMA direct memory access
  • controlling element 5 When the controlling element 5 needs to access the memory of one of the processing elements 1 through 4, it initiates a read or write operation to that region of its memory map occupied by that processing element, in this case processing element 1 for purposes of illustration.
  • the control logic 8 tied to the control register 7 then initiates a wait signal which causes the controlling element 5 to lengthen the read or write cycle.
  • the control logic 8 activates the controlling element buffers 9, and using the processing element select line 11 (from among lines 11 through 14), signals the selected processing element 1 to suspend operation. Processing element 1 then suspends operation and relinquishes control of the local bus, at the same time activating its processing element buffers 21 and causing the control logic 8 to discontinue the wait signal.
  • the controlling element 5 has direct access to the local memory of processing element 1, and the read or write operation can be completed.
  • the element select line 11 remains active until another processing element is selected or the control register 7 is cleared, so that subsequent read or write operations to the memory of processing element 1 take place without wait states. Accessing another processing element (2 through 4), or clearing the control register 7, causes the control logic 8 to inactivate the element select line 11, allowing the microprocessor in the previously selected processing element 1 to inactivate its element buffers 21, thus isolating its local bus from the board bus. At this point, the previously selected processing element's microprocessor resumes program execution.
  • the control register and circuitry also provide for a broadcast mode, in which multiple processing elements 1, 2, 3, and 4 may be simultaneously accessed via DMA.
  • This mode operates ' similarly to single-element DMA, except that reading from the processing elements' memories, which would cause massive data line contention - on the board bus 6, is disallowed; only writes may be performed in broadcast mode.
  • This mode is available to controlling element 5, which can use it to access all processing elements on its board.
  • Access to controlling element 5 by the host processor 15 functions in a similar manner to access by the processing elements 1 through 4 by controlling element 5, with a few differences.
  • the host processor 15 must employ its high-order addressing to select the board in question, at which point controlling element select line 28 becomes active.
  • Controlling element 5 then suspends operation and relinquishes control of its local bus, at the same time activating host processor buffers and causing the control logic 8 to discontinue the host wait signal.
  • the local bus of the controlling element 5 becomes a logical extension of the host bus 16 in which the board is installed, and reads and writes to the controlling element's memory may be performed by the host.
  • the host now may have access to the board bus and processing elements, since they logically reside in the controlling element's memory map which is available to the host. Access to the processing elements can proceed in exactly the same fashion as described above, except that it is the host, acting via the local bus of the controlling element, which selects processing elements and performs reads and writes.
  • control logic 8 sends non-maskable interrupt (NMI) signals to one or more processing elements; these non ⁇ maskable interrupts may be used to force execution of debugging programs, previously written to element memory by DMA, which facilitate the discovery of errors in other programs being executed by the processing element.
  • NMI non-maskable interrupt
  • An example of such a debugging program would be a 'register dump and wait 1 program, which would cause the processing element's microprocessor to write the contents of its internal registers to a preassigned area in memory, then execute a loop of null instructions. This memory could then be read by the host processor or controlling element in a subsequent DMA operation, to determine the exact microprocessor status at the time the NMI was asserted.
  • the host processor is an IBM PC or compatible personal computer, and the host processor bus is therefore the IBM PC bus, as described in detail in the IBM Personal Computer technical reference manual.
  • the board illustrated in fig. 1 contains four processing elements (more than four processing units may be used) , where each processing element consists of the following components: a UPD70108C10 serves as the microprocessor 1,2,3,4, an 62256 static random-access memory serves as memory 41,42,43,44, a PAL16R4 programmable logic device and 74HC573 octal latch serve as support circuitry 51,52,53,54, and one 74HC245 octal bidirectional buffer and one 74 ⁇ C573 octal latch are used to implement the - processing element buffers 21,22,23,24.
  • One controlling element contains a UPD70208C10 which serves as the microprocessor as well as an 62256 static random-access memory, a 74HC573 octal latch which serves as support circuitry, and one 74HC245 and.one proportion74HC573 which serve as the controlling element buffers.
  • the controlling element also contains a semicustom 2000-gate array circuit HD003 to perform high-speed DMA data transfer to and from the processing - elements, and a Zilog 8536 integrated circuit to perform input or output to devices other than the host PC.
  • the board bus 6 consists of 16 conductors running the length of the board, which are connected to the respective 16 pins on the processing element buffers 21,22,23,24 of each of the four processing elements, as well as to the respective 16 pins on the controlling element buffers of the controlling element. Of these 16 conductors, 7 carry address lines A8-A14, 8 carry multiplexed address/data lines AD0-AD7, and the remaining line carries the read/write line.
  • the host processor buffer is implemented by one 74HC245 octal bidirectional buffer circuit and two 74HC573 octal latch circuits.
  • the decoding circuitry is implemented on semicustom 2000- gate array circuit HD001, and the control register and accompanying logic are implemented in semicustom 2000- gate array circuit HD002.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)

Abstract

Une configuration de microprocesseurs multiples est installée sur une seule plaquette de circuits susceptible d'être connectée au bus d'expansion d'un ordinateur personnel ou d'un poste de travail (15). Cette plaquette de circuits comprend une pluralité de systèmes microprocesseurs et un bus commun (6) de communications de la plaquette qui connecte les systèmes microprocesseurs à un dispositif électronique de commande (5). Un bus de communications relie le bus (6) de la plaquette au bus d'expansion (16) de l'ordinateur personnel ou du poste de travail (15) afin d'assurer la commande des communications entre l'ordinateur personnel ou poste de travail (15) et les systèmes microprocesseurs.
PCT/US1988/002109 1987-06-19 1988-06-17 Plaquette de circuits multi-processeurs pouvant etre installee en exemplaires multiples dans des ordinateurs personnels et des bus d'expansion de postes de travail WO1988010468A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6433587A 1987-06-19 1987-06-19
US064,335 1987-06-19

Publications (1)

Publication Number Publication Date
WO1988010468A1 true WO1988010468A1 (fr) 1988-12-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/002109 WO1988010468A1 (fr) 1987-06-19 1988-06-17 Plaquette de circuits multi-processeurs pouvant etre installee en exemplaires multiples dans des ordinateurs personnels et des bus d'expansion de postes de travail

Country Status (2)

Country Link
AU (1) AU1993088A (fr)
WO (1) WO1988010468A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0465067A2 (fr) * 1990-07-02 1992-01-08 Digital Equipment Corporation Double file d'attente de sortie entrelacée
EP0471928A2 (fr) * 1990-08-20 1992-02-26 Kabushiki Kaisha Toshiba Système de confirmation de l'état de connexion et méthode d'extention d'unité
US5299322A (en) * 1990-02-23 1994-03-29 Kabushiki Kaisha Toshiba Computer system with improved interface control of an I/O expansion unit
EP0686921A2 (fr) * 1994-05-26 1995-12-13 Hitachi, Ltd. Système décentralisé et système à multiprocesseur

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3959775A (en) * 1974-08-05 1976-05-25 Gte Automatic Electric Laboratories Incorporated Multiprocessing system implemented with microprocessors
US4145739A (en) * 1977-06-20 1979-03-20 Wang Laboratories, Inc. Distributed data processing system
US4214305A (en) * 1977-06-20 1980-07-22 Hitachi, Ltd. Multi-processor data processing system
US4504927A (en) * 1982-09-08 1985-03-12 Allen-Bradley Company Programmable controller with expandable I/O interface circuitry
US4570220A (en) * 1983-11-25 1986-02-11 Intel Corporation High speed parallel bus and data transfer method
US4591981A (en) * 1982-04-26 1986-05-27 V M E I "Lenin" Quartal Darvenitza Multimicroprocessor system
US4710893A (en) * 1984-06-22 1987-12-01 Autek Systems Corporation High speed instrument bus

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3959775A (en) * 1974-08-05 1976-05-25 Gte Automatic Electric Laboratories Incorporated Multiprocessing system implemented with microprocessors
US4145739A (en) * 1977-06-20 1979-03-20 Wang Laboratories, Inc. Distributed data processing system
US4214305A (en) * 1977-06-20 1980-07-22 Hitachi, Ltd. Multi-processor data processing system
US4591981A (en) * 1982-04-26 1986-05-27 V M E I "Lenin" Quartal Darvenitza Multimicroprocessor system
US4504927A (en) * 1982-09-08 1985-03-12 Allen-Bradley Company Programmable controller with expandable I/O interface circuitry
US4570220A (en) * 1983-11-25 1986-02-11 Intel Corporation High speed parallel bus and data transfer method
US4710893A (en) * 1984-06-22 1987-12-01 Autek Systems Corporation High speed instrument bus

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5299322A (en) * 1990-02-23 1994-03-29 Kabushiki Kaisha Toshiba Computer system with improved interface control of an I/O expansion unit
EP0465067A2 (fr) * 1990-07-02 1992-01-08 Digital Equipment Corporation Double file d'attente de sortie entrelacée
EP0465067A3 (en) * 1990-07-02 1993-01-27 Digital Equipment Corporation Dual interleaved output queue
US5265229A (en) * 1990-07-02 1993-11-23 Digital Equipment Corporation Single load, multiple issue queue with error recovery capability
EP0471928A2 (fr) * 1990-08-20 1992-02-26 Kabushiki Kaisha Toshiba Système de confirmation de l'état de connexion et méthode d'extention d'unité
EP0471928A3 (en) * 1990-08-20 1993-01-20 Kabushiki Kaisha Toshiba Connection state confirmation system and method for expansion unit
US5377357A (en) * 1990-08-20 1994-12-27 Kabushiki Kaisha Toshiba Connection state confirmation system and method for expansion unit
EP0686921A2 (fr) * 1994-05-26 1995-12-13 Hitachi, Ltd. Système décentralisé et système à multiprocesseur
EP0686921A3 (fr) * 1994-05-26 1996-02-07 Hitachi Ltd Système décentralisé et système à multiprocesseur

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Publication number Publication date
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