WO1988006379A1 - Correction circuit for an amplifier - Google Patents

Correction circuit for an amplifier Download PDF

Info

Publication number
WO1988006379A1
WO1988006379A1 PCT/EP1988/000102 EP8800102W WO8806379A1 WO 1988006379 A1 WO1988006379 A1 WO 1988006379A1 EP 8800102 W EP8800102 W EP 8800102W WO 8806379 A1 WO8806379 A1 WO 8806379A1
Authority
WO
WIPO (PCT)
Prior art keywords
correction circuit
circuit according
impedance
current
transistors
Prior art date
Application number
PCT/EP1988/000102
Other languages
French (fr)
Inventor
Didier René HASPESLAGH
Dirk Herman Lutgardis Cornelius Rabaey
Pierre-Paul François Maurice Marie GUEBELS
Original Assignee
Alcatel N.V.
Bell Telephone Manufacturing Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel N.V., Bell Telephone Manufacturing Company filed Critical Alcatel N.V.
Publication of WO1988006379A1 publication Critical patent/WO1988006379A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/307—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in push-pull amplifiers
    • H03F1/308—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in push-pull amplifiers using MOSFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45508—Indexing scheme relating to differential amplifiers the CSC comprising a voltage generating circuit as bias circuit for the CSC

Definitions

  • the invention relates to a correction circuit for an amplifier including the series connection of two transistors which are of the opposite polarity type and which are provided with control electrodes to which DC control voltages are applied by control means.
  • Such an amplifier is generally known in the art.
  • the nominal values of the DC control voltages are such that the rest currents flowing through both transistors are equal.
  • the DC control voltages may present offsets with respect to the i r nominal values. This may have an adverse effect on the operation of the amplifier. Indeed, when these o f f se ts for instance have an opposite sign with respect to their respective nominal values then this has for effect that the transistors are either more or less conductive. When the offsets are relatively larger this may lead to an excessive current consumption or to a blocking (c r oss-o ve r distorsion) of the transistors.
  • An object of the invention is to provide a correction circuit for such an amplifier by which this adverse effect on the amplifier is obviated or anyhow considerably reduced.
  • this object is achieved due to the fact that the correction circuit is able to maintain the DC voltage between said control electrodes r e lat i ve ly constant.
  • Another characteristic of the present correct i on circuit is that it is constituted by the series connection of an impedance which is connected between said control electrodes, and two current sources which provide a same current and are connected to respective ends of said impedance, said current producing said substantially constant voltage over said impedance.
  • Fig. 1 represents in detail an amplifier and the associated correction circuit according to the invention
  • Fig. 2 is an equivalent schematic diagram of this correction circuit and amplifier to illustrate the operation thereof.
  • the amplifier represented in Fig. 1 is a class AB amplifier and includes a bias circuit BC, a differential amp l i f i er i np ut stage DAS , an o utp ut stage OS and a correction circuit CC.
  • This amplifier includes PMOS transistors PMl to PMll, NMOS transistors NM1 to NH8 and capacitors C1 and C2 and operates with the supply voltages VDD and VSS which are for instance equal to +5 Volts and -5 Volts respectively. Further, a control voltage CV which is equal to VSS or VDD is used to switch the amplifier on or off by making transistor PM2 conductive or by blocking this transistor respectively.
  • Bias circuit BC is a current source constituted by the series connection of transistors PM1, PM2, PM3 and NM1, the gate and drain electrodes of each of PM1, PM3 and NM1 being interconnected and PM2 being controlled by the voltage CV, as mentioned above.
  • Transistor PM1 is connected in current mirror configuration with transistors PM6 and PM10 and the same is true for transistor NM1 and transistors NM4 and NM8. This means that when I is the current flowing through transistors PM1, PM2, PM3 and NM1, the same current also flows through transistors PM6, PM10, NM4 and NM8 when the latter transistors have the same dimensions. However, these dimensions are so chosen that the current I flows through PM10 and NM8» whilst a current II flows through PM6 and NM4.
  • the differential amplifier input stage DAS having input terminals T1 and T2 is constituted by two differential amplifier circuits which are connected in anti-parallel between VDD and VSS.
  • the like named inputs T1, T2 of these circuits are interconnected and each of them is of the type described on page 219 of the book "Analysis and Design of Analog Integration Circuits" by P.R. Gray and R.G. Meyer, John Wiley and Sons, 1977.
  • Th e first of these differential amplifier circuits includes transistors PM4, PM5, PM6, NM5, NM6, whilst the second one includes transistors NM2, NM3, NM4, PM7 and PM8.
  • the source-to-drain path of PM6 is connected between VDD and VSS in series, on the one hand with the source-to-drain path of emitter follower transistor PM4 and the drain-to-source of diode-connected transistor NM5 and, on the other hand, with the source-to-drain path of emitter follower transistor PM5 and the drain-to-source path of NM6.
  • PM6 is a current source providing a current II
  • NM5 is connected in current mirror configuration with NM6 which constitutes an active load having a resistance of nominal value R1 for the amplifier circuit.
  • the drain electrode of NM6 is the output A of the first differential amplifier circuit.
  • the source-to-drain path of diode-connected transistor PM7 and the drain-to-source path of emitter follower transistor NM2 are connected between VDD and VSS in series with the drain-to-source path of NM4 and also the source-to-drain path of PMS and the drain-to-source path of emitter follower transistor NM3 is connected between the same voltages in series with the drain-to-source path of NM4.
  • NM4 is a current source providing the current I1 and PM7 is connected in current mirror configuration with PM8 which constitutes an active load having resistance with nominal value R2 for the amplifier.
  • the drain electrode of PM8 is output B of this second differential amplifier ciruit.
  • the output stage OS includes, between VDD and VSS, the series connected source-to-drain paths of transistors PM9 and NM7 whose gates are connected to the outputs B and A of the second and first amplifier circuits respectively. Moreover, the outputs A and B are connected to the drain electrodes of NM7 and PM9 respectively via capacitors C1 and C2 which are used to determine the frequency characteristic of the amplifier.
  • the first and second differential amplifier circuits thus apply via respective resistances of nominal values R1 and R2 nominal DC control voltages to the gates A and B, and as mentioned above the purpose of the correction circuit CC is to obviate or anyhow considerably reduce the adverse effect of offsets of these DC voltages with respect to their respective nominal values.
  • This correction circuit CC includes the series connection, between VDD and VSS, of the source-to-drain paths of transistors PM10, PM11 and NM8, the drain and source electrodes of PM11 being interconnected.
  • PM10 and NM6 constitute current sources each providing a current I and PM11 is a resistance called R.
  • each of the first and second differential amplifier circuits of the differential amplifier input stage and which in fact constitute control means for the output stage is known per se, and the operation of this stage is therefore not described. It is only be noted that these first and second differential amplifier circuits are used for the amplification of negatively and positively directed signals applied to the input T1, T2 respectively.
  • Fig. 2 represents an equivalent circuit of the amplifier circuit according to Fig. 1, however without the bias circuit BC and on the assumption that transistors PM4, PM5, NM2 and NM3 are conductive.
  • the gate of NM7 is coupled with the junction point A of PM6 and NM6, which constitute a current source and a resistance R1 respectively, this current source providing the current II.
  • Current source NM8 which provides the current I is further connected between the gate and source electrodes of NM7.
  • the gate of PM9 is coupled with the junction point B of PM8 and NM4 which constitute a resistance R2 and a current source respectively, this current source providing the current II.
  • the current source PM10 which provides the current I is connected between the source and gate electrodes of PM9.
  • VA and VB are called the DC voltages on the outputs A and B of the first and second differential amplifier circuits, in the absence of DC offset, then the following relation is valid :
  • both NM7 and PM9 become less conductive and if the voltage change is sufficiently large both these transistors may thus become blocked.
  • VDD - VSS (R2 - R3).(I1 + I2) + R . (I + I2)
  • a DC voltage offset VOSA e.g. produced by a change of R1 to R1 ⁇ R4, on the voltage across BA has an influence similar to an offset VOSB produced by a change of R2 to R2 ⁇ R3.
  • the differential voltage V"B - V"A may be written as follows :

Abstract

Correction circuit for an amplifier (PM1/9, NM1/7) including the series connection of two transistors (PM9, NM7) which are of the oppositive polarity type and which are provided with control electrodes to which DC control voltages are applied by control means (PM1/8, NM1/6). The circuit is constituted by the series connection of an impedance (R) which is connected between the control electrodes (B, A) and two current sources (PM10, NM8) which provide a same current (I) and are connected with respective ends (B, A) of said impedance (PM11) and maintains the voltage between the control electrodes substantially constant (RI).

Description

CORRECTION CIRCUIT FOR AN AMPLIFIER The invention relates to a correction circuit for an amplifier including the series connection of two transistors which are of the opposite polarity type and which are provided with control electrodes to which DC control voltages are applied by control means.
Such an amplifier is generally known in the art. In the ideal case the nominal values of the DC control voltages are such that the rest currents flowing through both transistors are equal. However, by a number of reasons, such as for instance deviations in the process by which the transistors are made, the DC control voltages may present offsets with respect to the i r nominal values. This may have an adverse effect on the operation of the amplifier. Indeed, when these o f f se ts for instance have an opposite sign with respect to their respective nominal values then this has for effect that the transistors are either more or less conductive. When the offsets are relatively larger this may lead to an excessive current consumption or to a blocking (c r oss-o ve r distorsion) of the transistors.
An object of the invention is to provide a correction circuit for such an amplifier by which this adverse effect on the amplifier is obviated or anyhow considerably reduced.
According to the invention this object is achieved due to the fact that the correction circuit is able to maintain the DC voltage between said control electrodes r e lat i ve ly constant.
In this way offsets of the control voltages provided by the control means and which are of an opposite sign with respect to their respective nominal values can have no adverse effect on the operation of the amplifier.
Another characteristic of the present correct i on circuit is that it is constituted by the series connection of an impedance which is connected between said control electrodes, and two current sources which provide a same current and are connected to respective ends of said impedance, said current producing said substantially constant voltage over said impedance.
The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein :
Fig. 1 represents in detail an amplifier and the associated correction circuit according to the invention; Fig. 2 is an equivalent schematic diagram of this correction circuit and amplifier to illustrate the operation thereof.
The amplifier represented in Fig. 1 is a class AB amplifier and includes a bias circuit BC, a differential amp l i f i er i np ut stage DAS , an o utp ut stage OS and a correction circuit CC. This amplifier includes PMOS transistors PMl to PMll, NMOS transistors NM1 to NH8 and capacitors C1 and C2 and operates with the supply voltages VDD and VSS which are for instance equal to +5 Volts and -5 Volts respectively. Further, a control voltage CV which is equal to VSS or VDD is used to switch the amplifier on or off by making transistor PM2 conductive or by blocking this transistor respectively. Bias circuit BC is a current source constituted by the series connection of transistors PM1, PM2, PM3 and NM1, the gate and drain electrodes of each of PM1, PM3 and NM1 being interconnected and PM2 being controlled by the voltage CV, as mentioned above. Transistor PM1 is connected in current mirror configuration with transistors PM6 and PM10 and the same is true for transistor NM1 and transistors NM4 and NM8. This means that when I is the current flowing through transistors PM1, PM2, PM3 and NM1, the same current also flows through transistors PM6, PM10, NM4 and NM8 when the latter transistors have the same dimensions. However, these dimensions are so chosen that the current I flows through PM10 and NM8» whilst a current II flows through PM6 and NM4.
The differential amplifier input stage DAS having input terminals T1 and T2 is constituted by two differential amplifier circuits which are connected in anti-parallel between VDD and VSS. The like named inputs T1, T2 of these circuits are interconnected and each of them is of the type described on page 219 of the book "Analysis and Design of Analog Integration Circuits" by P.R. Gray and R.G. Meyer, John Wiley and Sons, 1977. Th e first of these differential amplifier circuits includes transistors PM4, PM5, PM6, NM5, NM6, whilst the second one includes transistors NM2, NM3, NM4, PM7 and PM8. In the first differential amplifier circuit the source-to-drain path of PM6 is connected between VDD and VSS in series, on the one hand with the source-to-drain path of emitter follower transistor PM4 and the drain-to-source of diode-connected transistor NM5 and, on the other hand, with the source-to-drain path of emitter follower transistor PM5 and the drain-to-source path of NM6. Hereby PM6 is a current source providing a current II and NM5 is connected in current mirror configuration with NM6 which constitutes an active load having a resistance of nominal value R1 for the amplifier circuit. The drain electrode of NM6 is the output A of the first differential amplifier circuit.
In the next differential amplifier circuit the source-to-drain path of diode-connected transistor PM7 and the drain-to-source path of emitter follower transistor NM2 are connected between VDD and VSS in series with the drain-to-source path of NM4 and also the source-to-drain path of PMS and the drain-to-source path of emitter follower transistor NM3 is connected between the same voltages in series with the drain-to-source path of NM4. Hereby, NM4 is a current source providing the current I1 and PM7 is connected in current mirror configuration with PM8 which constitutes an active load having resistance with nominal value R2 for the amplifier. The drain electrode of PM8 is output B of this second differential amplifier ciruit.
The output stage OS includes, between VDD and VSS, the series connected source-to-drain paths of transistors PM9 and NM7 whose gates are connected to the outputs B and A of the second and first amplifier circuits respectively. Moreover, the outputs A and B are connected to the drain electrodes of NM7 and PM9 respectively via capacitors C1 and C2 which are used to determine the frequency characteristic of the amplifier. The first and second differential amplifier circuits thus apply via respective resistances of nominal values R1 and R2 nominal DC control voltages to the gates A and B, and as mentioned above the purpose of the correction circuit CC is to obviate or anyhow considerably reduce the adverse effect of offsets of these DC voltages with respect to their respective nominal values. This correction circuit CC includes the series connection, between VDD and VSS, of the source-to-drain paths of transistors PM10, PM11 and NM8, the drain and source electrodes of PM11 being interconnected. Hereby, PM10 and NM6 constitute current sources each providing a current I and PM11 is a resistance called R.
As already mentioned above, each of the first and second differential amplifier circuits of the differential amplifier input stage and which in fact constitute control means for the output stage is known per se, and the operation of this stage is therefore not described. It is only be noted that these first and second differential amplifier circuits are used for the amplification of negatively and positively directed signals applied to the input T1, T2 respectively.
To understand the operation of the correction circuit CC, reference is now made to Fig. 2 which represents an equivalent circuit of the amplifier circuit according to Fig. 1, however without the bias circuit BC and on the assumption that transistors PM4, PM5, NM2 and NM3 are conductive. The gate of NM7 is coupled with the junction point A of PM6 and NM6, which constitute a current source and a resistance R1 respectively, this current source providing the current II. Current source NM8 which provides the current I is further connected between the gate and source electrodes of NM7. In a similar way the gate of PM9 is coupled with the junction point B of PM8 and NM4 which constitute a resistance R2 and a current source respectively, this current source providing the current II. Further, the current source PM10 which provides the current I is connected between the source and gate electrodes of PM9. When VA and VB are called the DC voltages on the outputs A and B of the first and second differential amplifier circuits, in the absence of DC offset, then the following relation is valid :
VDD - VSS = R.I + (R1 + R2).I1 (1) Because : VB = VDD - R2.I1 (2) and VA = VSS + R1.I1 (3) the relation (1) may be written :
VB - VA = R.I (4) When VOSA and VOSB are called the DC offsets with respect to the nominal values VA and VB, then they can have an adverse effect on the operation of the amplifier. Indeed :
- when VOSA and VOSB are positive and negative with respect to VA and VB respectively, then both NM7 and PM9 become more conductive and thus give result to a higher current consumption;
- when VOSA and VOSB are negative and positive with respect to VA and VB respectively, then both NM7 and PM9 become less conductive and if the voltage change is sufficiently large both these transistors may thus become blocked.
If the correction circuit CC is not present and positive DC offset voltage VOSB with respect to VB is produced, for instance due to the resistance R2 instead of its nominal value R2 having the value R2 - R3, then the following relation may be written because the current II then completely flows through R2 - R3 : V'B = VDD - (R2 - R3).I1 = VB + VSOB (5) V'A = VSS + R1.I1 = VA (6) with VOSB = R3.I1 (7) so that
VB - VA = R.I + VOSB (8)
This means that the full DC offset VOSB appears across the output BA of the amplifier, this being unwanted.
However, if the correction circuit CC is present, then the above mentioned DC offset VOSB has the following influence on the DC voltage appearing across the output BA. By the presence of CC an additional (negative or positive) current 12 may flow from VDD to VSS via R2 - R3, R and RI so that the following relations may be written :
VDD - VSS = (R2 - R3).(I1 + I2) + R . (I + I2)
+ R1 . (I1 + I2) (9) or VDD - R2.I1 - (VSS + R1.I1) = R.I - R3.I1
+ ( R + R 1 + R 2 - R 3 ) . 1 2 ( 10 )
Taking the relations (2), (3) and (4) into account, it follows therefrom that :
Figure imgf000009_0001
Because the voltage V"B - V"A across the output BA is given by V"B - VA = R(I + I2) (12) it may be written as follows, when taking the relation (11) into account :
Figure imgf000009_0002
or, taking the relation (7) into account : VB - VA = RI + F.VOSB (14) when
Figure imgf000009_0003
In case VOSB is produced by an offset of R2 to R2 ± R3 then F is substantially given by :
Figure imgf000009_0004
This means that when
Figure imgf000009_0005
is chosen much larger than 1, this factor F becomes very small, so that the contribution of the DC offset in the differential output voltage which according to the relation (8) is equal to VOSB without CC, is reduced to F.VOSB which is much smaller than VOSB. In other words, the output voltage remains subtantially constant and equal to RI independently from the DC offset of the DC control voltage. In a preferred embodement the value of R is substantially ten times smaller than the sum of RI and R2 and the value of the resistance R3 amounts to some percentages of R1.
It is clear that a DC voltage offset VOSA, e.g. produced by a change of R1 to R1 ± R4, on the voltage across BA has an influence similar to an offset VOSB produced by a change of R2 to R2 ± R3.
If not only R2 but also R1 presents an offset, then the differential voltage V"B - V"A may be written as follows :
Figure imgf000010_0002
In this case the DC offset voltage VOSB-VOSA which without the circuit CC would be fully present across BA» is reduced to
(VOSB - VOSA) . G (18) wherein G is given by :
Figure imgf000010_0001
By chosing this factor G very small the offset on the output voltage becomes negligiably small i.e. this output voltage remains substantially constant and equal to R.I. From the formula (17) it is also clear that the circuit CC only operates when VOSB is different from VOSA and not when these are equal. From this formula it also follows that offsets VOSA, VOSB of a different sign with respect to these respective nominal values as offsets of a same sign but which are different are corrected. While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims

1. Correction circuit for an amplifier (PM1/9, NMl/7) including the series connection of two transistors (PM9, NM7) which are of the oppositive polarity type and which are prov i ded with control electrodes (B,A) to which DC control voltages are applied by control means (PM1/8, NM1/6), characterized in that it is able to maintain the DC voltage between said control electrodes (B,A) relatively constant (RI).
2. Correction circuit according to claim 1, characterized in that it is constituted by the series connection of an impedance (RI) which is connected between said control electrodes (B,A), and two current sources (PM10, NM8) which provide a same current (I) and are connected to respective ends (B,A) of said impedance (PM11), said current (I) producing said substantially constant voltage (RI) over said impedance (R).
3. Correction circuit according to claim 2, characterized in that said DC control voltages are provided by said control means (PM1/8, NM1/6) via other impedances (R2, R1).
4. Correction circuit according to claim 3, characterized in that said two series circuits (PM9, NM7; PM10/11, NM8) are connected in parallel between the poles (VDD, VSS) of a DC voltage source and that said control means (PM1/8, NM1/6) derive said DC control voltages from said DC voltage source (VDD, VSS) via said other impedances (R2, R1).
5. Correction circuit according to claim 2, characterized in that a first of said current sources includes a PMOS transistor (PM10) and a second of said current sources includes a NMOS transistor (NM8).
6. Correction circuit according to claim 2, characterized in that said impedance (R) is constituted by a diode connected MOS transistor (PM11).
7. Correction circuit according to claim 1, characterized in that said transistors (PM9, NM7) are MOS transistors.
8. Correction circuit according to claim 1, characterized in that said amplifier is a class A-B amplifier.
9. Correction circuit according to claim 1, characterized in that said control means include two differential amplifier circuits (PM4/5, NM5/6, NM2/4, PM7/8) whose like named inputs (T1, T2) are interconnected and constitute the inputs of an input stage of the amplifier and whose outputs (A, B) are connected to said control electrodes.
10. Correction circuit according to claims 4 and 9, characterized in that each of said differential amplifier circuits (PM4/6, NM5/6; NM2/4, PM7/8) is constituted by the series connection, between said two poles (VDD, VSS) of a third current source (PM6; NM4) and two parallel branches including emitter follower transistors (PM4, PM5; NM2, NM3) and an active load formed by a current source (NM5, NM6; PM7, PM8) and constituting said other impedance (RI, R2), the emitter follower transistors (PM4, PM5; NM2, NM3) of said differential amplifier circuits being of the opposite conductivity type and having control electrode constituting the inputs (T1, T2) of said input stage and said differential amplifier circuits being connected in anti-parallel between said poles.
11. Correction circuit according to claim 3, characterized in that the value of said impedance (R) is much smaller than the sum of the values of said other impedances (R2, R1).
PCT/EP1988/000102 1987-02-20 1988-02-10 Correction circuit for an amplifier WO1988006379A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
BE8700160 1987-02-20
BE8700160A BE1000333A7 (en) 1987-02-20 1987-02-20 Correction chain ​​for a amplifier.

Publications (1)

Publication Number Publication Date
WO1988006379A1 true WO1988006379A1 (en) 1988-08-25

Family

ID=3882527

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1988/000102 WO1988006379A1 (en) 1987-02-20 1988-02-10 Correction circuit for an amplifier

Country Status (3)

Country Link
BE (1) BE1000333A7 (en)
NO (1) NO880689L (en)
WO (1) WO1988006379A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4888559A (en) * 1987-06-30 1989-12-19 Alcatel N.V. Correction arrangement for an amplifier
EP0544338A1 (en) * 1991-11-28 1993-06-02 Oki Electric Industry Co., Ltd. MOS operational amplifier circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038607A (en) * 1976-08-23 1977-07-26 Rca Corporation Complementary field effect transistor amplifier
US4333058A (en) * 1980-04-28 1982-06-01 Rca Corporation Operational amplifier employing complementary field-effect transistors
US4356453A (en) * 1979-02-08 1982-10-26 Pioneer Electronic Corporation Reduced noise-improved gain transistor circuit
US4480230A (en) * 1983-07-05 1984-10-30 National Semiconductor Corporation Large swing CMOS power amplifier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038607A (en) * 1976-08-23 1977-07-26 Rca Corporation Complementary field effect transistor amplifier
US4356453A (en) * 1979-02-08 1982-10-26 Pioneer Electronic Corporation Reduced noise-improved gain transistor circuit
US4333058A (en) * 1980-04-28 1982-06-01 Rca Corporation Operational amplifier employing complementary field-effect transistors
US4480230A (en) * 1983-07-05 1984-10-30 National Semiconductor Corporation Large swing CMOS power amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4888559A (en) * 1987-06-30 1989-12-19 Alcatel N.V. Correction arrangement for an amplifier
EP0544338A1 (en) * 1991-11-28 1993-06-02 Oki Electric Industry Co., Ltd. MOS operational amplifier circuit

Also Published As

Publication number Publication date
BE1000333A7 (en) 1988-10-25
NO880689L (en) 1988-08-22
NO880689D0 (en) 1988-02-17

Similar Documents

Publication Publication Date Title
AU606171B2 (en) Correction arrangement for an amplifier
US5736892A (en) Differential charge pump circuit with high differential impedance and low common mode impedance
US4581545A (en) Schmitt trigger circuit
US5045806A (en) Offset compensated amplifier
US4573020A (en) Fully differential operational amplifier with D.C. common-mode feedback
GB1592800A (en) Linear amplifier
EP0286347B1 (en) Balanced output analog differential amplifier circuit
US6628148B2 (en) Sample and hold circuit having a single control signal
US8988146B1 (en) Voltage amplifier for capacitive sensing devices using very high impedance
GB2155715A (en) Cmos power-on detection circuit
JPS60158708A (en) Communication calculating amplifier
EP0655831A1 (en) High performance transconductance operational amplifier, of the CMOS integrated type
US4707667A (en) Offset corrected amplifier
WO1988006379A1 (en) Correction circuit for an amplifier
US7579877B2 (en) Comparator
US5675289A (en) Differential amplifier
US5394107A (en) Absolute value circuit
US10788920B2 (en) Differential current conveyor circuit, corresponding device, and method of operation thereof
WO1981000928A1 (en) Sample and hold circuit with offset cancellation
EP0435600A2 (en) Integrated sample and hold circuits
JPWO2004049562A1 (en) Driving circuit
US4438388A (en) Single stage operational amplifier voltage reference
EP0499645A1 (en) Differential amplifying circuit of operational amplifier
JPH06101650B2 (en) Semiconductor integrated circuit device
US20220278662A1 (en) Operational Amplifier

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE FR GB IT LU NL SE