WO1988006349A1 - Reduction of charge transfer inefficiency in charge-coupled devices - Google Patents
Reduction of charge transfer inefficiency in charge-coupled devices Download PDFInfo
- Publication number
- WO1988006349A1 WO1988006349A1 PCT/US1988/000363 US8800363W WO8806349A1 WO 1988006349 A1 WO1988006349 A1 WO 1988006349A1 US 8800363 W US8800363 W US 8800363W WO 8806349 A1 WO8806349 A1 WO 8806349A1
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- WO
- WIPO (PCT)
- Prior art keywords
- charge
- ccd
- packet
- packets
- signal charge
- Prior art date
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- 230000009467 reduction Effects 0.000 title description 2
- 239000000463 material Substances 0.000 claims description 8
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000283986 Lepus Species 0.000 description 1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76825—Structures for regeneration, refreshing, leakage compensation or the like
Abstract
A CCD includes additional cells to collect and isolate charge due to transfer inefficiency and a summing gate which is operated so as to cause each residual charge packet to be added back into its immediately preceding signal charge packet just prior to the signal charge packet being delivered to an output device. The output device converts the signal charge packet to a voltage. By means of this structure charge transfer inefficiency is reduced.
Description
Reduction of charge transfer inefficiency in charge-coupled devices.
Technical Field
This invention relates to charge—coupled devices (CCD's) and more particularly to apparatus for reducing the inefficiencies in transferring charge in such devices. Background Art
A CCD transfers a signal charge packet from one potential well under an electrode to an empty potential well under an adjacent electrode. In a two-phase CCD, if each cell is provided by two adjacent electrodes, then when a signal charge packet is stored under one electrode (in a potential well) then the following potential well will be empty or have no information stored in it. In a three—phase device, if each cell includes three potential wells, only one cell will carry a signal charge packet. So if a charge packet is collected in a potential well, the next potential well will be empty. By changing the potential applied by the phase lines connected to the cell electrodes, charge is transferred from a potential well carrying charge to one which is empty. Charge transfer inefficiency (CTI) occurs in all CCD's during the transfer process. When a charge packet is transferred from one cell to another, a residual amount of such charge is left behind in the preceding cell during each charge transfer. This residual charge can mix into subsequent charge packets. Thus, any residual charge can distort both the original charge packet from which it came as well as subsequent charge packets which can be mixed in with it. This distortion or smearing of charge packets varies as a function of the number of charge transfers. The more frequently a charge packet is transferred, the more it will be distorted.
In order to appreciate the present invention, reference can be made to Fig. 3 which shows a two—phase buried channel CCD. Directly under the electrodes is an n—type layer 56. In layer 56, under the leading edge of each electrode there is implanted p—type material. This implant reduces the channel potential. In Fig. 3A, a signal charge packet I , is shown in a cell which is provided under two electrodes. The following cell contains a residual charge packet R .. The term n+1 means that at this stage in the operation of the charge-coupled device, the charge packet has been transferred n+1 times. The present invention recognizes that if the residual charge R_+1 is added back into the signal charge packet I _ just prior to a readout where charge is converted to a voltage, then the effects of charge transfer inefficiency can be significantly reduced. In other words, the residual charge Rn+1 in the following cell can be considered to be the first order transfer loss from the preceding charge packet In+1- By adding it back into the preceding charge packet, a significant improvement can be made in suppressing CTI. Disclosure of the Invention
The object of this invention is to provide a CCD which reduces the effects of CTI.
In accordance with the present invention there is provided a CCD including a doped semi—conductive substrate, an insulating layer over the substrate and a series of repeating electrodes connected to different sources of potential to define potential wells for storing signal charge packets and potential wells which follow such signal charge packets which collect residual charge, characterized by: means for causing each residual charge packet to
be added into its immediately preceding charge signal packet to thereby reduce charge—transfer inefficiency. A CCD which includes structure in accordance with this invention and which minimizes charge transfer inefficiency effects has the feature that it can be manufactured with a minimum of additional processing steps.
The feature of isolating residual charge from the preceding charge packet reduces charge transfer inefficiency.
Another feature is that CCD's in accordance with this invention have low noise sensitivity. A further feature is that the present invention can be effectively employed in image sensors without the loss of image sensing area. Brief Description of the Drawings
Fig. 1 is a schematic overall view of a partially broken away interline transfer CCD area image sensor utilizing a single horizontal output CCD in accordance with the present invention;
Fig. 1A shows in schematic the potential diagram for the horizontal CCD shown in Fig. 1;
Fig. 2 is a schematic overall view of a frame transfer CCD image area sensor but which utilizes two horizontal output CCD's in accordance with the present invention;
Fig. 3 is a schematic cross—sectional view of a conventional true two-phase CCD which can provide horizontal CCD's for the image sensors of Figs. 1 and 2;
Figs. 3A and 3B show in schematic potential diagrams during the transfer of charge in the horizontal CCD's A and B shown in Fig. 2;
Fig. 4 is a schematic cross—sectional view of any one of the horizontal CCD's shown in Figs. 1 and 2 showing the summing gate;
Figs. 4A—4D show in schematic potential diagrams depicting the transfer of charge at different times in the operation of the summing gate showing Fig. 4 in which residual charge is added into a preceding charge packet; and
Fig. 5 is a waveform diagram of voltages applied to the electrodes. Modes of Carrying Out the Invention
Fig. 1 depicts an interline transfer CCD area image sensor 10 showing elements of several transfer channels. The image sensor 10 provides two—phase, buried channel CCD's. Light from an image is sensed by capacitor elements 42 in each two—phase vertical transfer CCD 44. Also photodiodes could be used as the sensing elements. As is conventional with this type of capacitor structure, certain ones of the sensing elements in each channel may include transparent electrodes which are not covered with an opaque aluminum covering. Light from an image scene passes through the transparent electrodes and causes packets of electrons or charge to be collected in potential wells formed under each capacitor. Charge from each sensing element 42 is transferred to a potential well of a cell in a vertical CCD 44. Each electrode in the vertical CCD 44 is connected to one of the voltage lines ΦV1 and ΦV2- After exposure is over and charge is transferred to the vertical CCD 44, the two— hase voltage signals over lines ΦV1 and ΦV2 are clocked in the well—known manner to move the charge packets, one row at a time into a potential well of a cell in a two-phase horizontal output CCD H. This CCD H includes a summing gate or electrode SG in accordance with the invention. This summing gate SG will be described later, especially in connection. ith Figs. 4 and 4A—4D. Lines φ HI and φu H are used to
-5- transfer charge in the CCD H,. Between adjacent columns of elements 42, there are provided conventional channel stops 45. These channel stops may be formed by a thick field oxide or by a diffusion or by implants. The horizontal CCD H is shown schematically as a block. The CCD H is positioned below a transfer gate 30. An appropriate voltage signal is applied to lead T. to transfer charge packets from the CCD's 44 into potential wells of the horizontal CCD H. After a row of charge packets has been transferred to the CCD H, the transfer gate 30 is closed. By being closed, it is meant that a potential barrier is formed under the gate 30. This is accomplished by lowering the voltage on the lead T. while charge packets are transferred to an output device 3.2. Before reaching the device 32, they pass through the summing gate SG where the residual charge is added into leading charge packets to thereby reduce charge transfer inefficiency in accordance with the invention. The potential well under gate SG is controlled by the potential on voltage line Φ «„_>(__.. Thereafter, the enhanced charge packets are delivered to the output device 32 via an- output gate or electrode 49. The device 32 can include a conventional floating diffusion and an output amplifier that converts charge packets into an output voltage VQ.
Fig. 1A shows four cells of the horizontal CCD H. Signal charge packets I are shown in potential wells of cells 2 and 4. Cells 1 and 3 show residual charge packets R in potential wells. This residual charge has accumulated during transfer through vertical CCD's 44 and CCD H. The operation of CCD H will be described later ip connection with Figs. 4 and 5.
Turning now to Fig. 2, another two—phase frame transfer CCD area image sensor in accordance with the present invention is shown. Where parts correspond with those in the Fig. 1 area image sensor, they have the identical numbers. It will be noted that the Fig. 2 image area sensor includes two output horizontal CCD's, CCD A and CCD B. The use of two such horizontal output CCD devices is, of course, well—known in the art. It will be noted that this device includes an inner gate 30 which is connected to a voltage lead line T, and an outer gate 31 which is connected to a voltage line T . Voltage signals are applied to lines T. and T^ to control the flow of charge packets from the CCD image area sensor into the horizontal output CCD's A and B, respectively. The Fig. 2 device operates as follows: when 30 is open and 31 is closed, charge packets flow into cells in CCD A. However, when both 30 and 31 are open, charge packets flow into cells in CCD B. Only alternate charge packets are passed through to CCD B. The remaining packets are blocked from transfer by channel stops 45. By controlling the voltage applied on lines 1 and φ?, respectively, .charge packets are advanced in CCD's A and B to the right until delivered to a summing gate SG. Then they are merged under a gate. Thereafter all the signal charge packets are sequentially delivered via an output gate 49 controlled by a lead T3 to an output device 32. The device 32 is quite conventional and includes a floating diffusion FD and an output amplifier having two FET transistors 50 and 52, respectively. The voltage on the floating diffusion FD is applied to the gate electrode of FET 50. FET 52 functions as a current source. The output voltage V_ is produced at the electrical junction of FET's 50 and FET 52. Each of the CCD's A
49
-7- and B include a summing gate SG which is operated by a single potential lead line --. The operation of the gate SG, which is used to combine residual charge into a preceding charge packet, will shortly be discussed in connection with Figs. 4 and 5.
Turning to Fig. 3, there is shown in schematic, a cross—sectional portion of a conventional two-phase CCD which can be embodied in any one of the vertical and horizontal CCD's shown in Figs. 1 and 2, respectively. The CCD is shown to be constructed on a silicon semiconductive substrate.
The bulk 54 of the substrate is doped with a p—type material. A suitable p-type dopant is boron. An n-type layer 56 has been diffused into the p—type bulk to provide a buried channel. Suitable n-type materials can be arsenic or phosphorus. A silicon dioxide insulating layer 58 is deposited on top of the layer 56. On top of layer 58 are provided a series of electrodes 60. These electrodes 60 can be made of polysilicon. Under the leading edge of each of the electrodes, p—type material is implanted into the n—type layer 56 to create the potential profiles which are shown in Figs. 3A and B. Figs. 3A and B profiles actually depict the transfer of charge at a particular instant in time under certain of the electrodes in CCD A and CCD B of Fig. 2, respectively. As shown in Figs. 3A and 3B respectively, each cell of the CCD's A and B is provided by two electrodes 60. After n transfers, signal charge packet I is shown in cell 3 in CCD A and in cell 2 in CCD B. The residual charge R is n shown in the following cells 2 and 1 in CCD A and in CCD B, respectively. It is isolated from its preceding signal charge packet. In accordance with the invention, the residual charge is added back into the immediate preceding image charge packet. As
shown in Figs. 1 and 2, this addition occurs shortly before the charge packet is delivered to the output device 32 which converts charge into an output voltage V_. This prevents the formation of new residual charge packets.
Turning now to Fig. 4, we see the same type structure as is shown in Fig. 3 with the exception that the summing gate SG is also shown, Under this gate SG, there is also implanted positive material into the n—type layer 56. At the end of the CCD, each original signal charge packet designated by I is delayed one cycle by the use of the summing gate which acts as barrier to transfer. This holds the charge in position while the trailing cell's charge designated R is added to the original charge packet. Figs. 4A—D show the addition of the residual charge R into its immediately preceding signal f_h charge packet I (where n represents the n charge packet). Transfer is accomplished by operating the gate SG at four different times, tl—14. The voltage levels on the lead lines φ-, φ ___. and Φ___)V_s is shown in Fig. 5. With reference now to Figs. 4A—D and Fig. 5, we will describe the operation of the summing gate SG and the process whereby the residual charge R is added into the signal charge packet I . At time, t equals t_, φl is low, φ2 is high and φSG is low. A potential barrier is raised up under SG to prevent the signal charge packet I from being transferred. At time, t_, Φ__ continues to
2 SG remain low but at this time φ. is changed to a high level and Φ2 to a low potential level. The potential diagram for this condition is shown in Fig.
4B. At time t-, Φ1 is turned low, φ_ high and Φ_G remains low. The residual charge now is added into the preceding signal charge packet I . n
At time t . , φ. is high, φ2 is low and φo..t„- is high. The augmented signal charge packet is now transferred under the cell which follows the gate SG and is subsequently transferred out by gate 49 to the output device 32 which has previously been described. It should be noted that no p—type material is implanted in layer 56 under the electrode which immediately follows gate SG. To further improve CTI, two or more empty potential wells can be used to follow each original charge packet. In such a case, both the first order and second order CTI residual charge can be recombined with the original charge packet by holding the summing gate in a barrier state or two extra cycles. Industrial Applicability and Advantages
The present invention can also be employed in linear CCD arrays, in which charge packets are serial or parallel transferred to one or more CCD's as in delay line or linear image applications. Image sensors could use photodiodes or other charge storage- devices.
Claims
1. A process for reducing the charge transfer inefficiency in a CCD having cells for storing signal charge packets characterized in that the signal charge packets are stored every n cell and the intermediate cells are used to collect the residual charge packets and in that the signals stored in one signal charge packet cell and the intermediate associated cells are added in order to reduce the charge transfer inefficiency.
2. An image sensor comprising: sensing elements for collecting charge packets for representing the intensity of light from an image, a horizontal CCD, means for transferring charge packets from said sensing elements to said CCD, said CCD including a doped semiconductor substrate, .an insulating layer over the substrate and a series of repeating electrodes connected to different sources of a potential to define a plurality of cells for storing signal charge packets and cells which follow each signal charge packet storing cell which collect residual charge, and means for causing each residual charge packet to be added into its immediate preceding signal charge packet to thereby reduce charge transfer inefficiency.
3. The sensor as set forth in claim 2, wherein said adding means includes a summing gate and control means for varying a voltage signal applied to said summing gate which causes residual charge to be added into its immediately preceding signal charge packet.
4. The sensor as set forth in claim 3, wherein said CCD is a two—phase device.
5. The sensor as set forth in claim 4, wherein the substrate is doped with a p—type material and an n-type layer is diffused into said p—type substrate and p—type material is implanted under the leading edge of each said electrode in said n—type layer except under the electrode immediately preceding said summing gate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US1575487A | 1987-02-17 | 1987-02-17 | |
| US015,754 | 1987-02-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1988006349A1 true WO1988006349A1 (en) | 1988-08-25 |
Family
ID=21773414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1988/000363 WO1988006349A1 (en) | 1987-02-17 | 1988-02-08 | Reduction of charge transfer inefficiency in charge-coupled devices |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0302101A1 (en) |
| JP (1) | JPH01502310A (en) |
| WO (1) | WO1988006349A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0438316A2 (en) * | 1990-01-19 | 1991-07-24 | Sharp Kabushiki Kaisha | Image data processing apparatus |
| EP0553869A2 (en) * | 1992-01-31 | 1993-08-04 | Kabushiki Kaisha Toshiba | Method for transferring charge, charge transfer device and solid state image sensing device using the same |
| CN101341735B (en) * | 2005-12-21 | 2010-11-03 | 伊斯曼柯达公司 | Image sensor for still or video photography |
-
1988
- 1988-02-08 JP JP50213788A patent/JPH01502310A/en active Pending
- 1988-02-08 EP EP19880902039 patent/EP0302101A1/en not_active Withdrawn
- 1988-02-08 WO PCT/US1988/000363 patent/WO1988006349A1/en not_active Application Discontinuation
Non-Patent Citations (2)
| Title |
|---|
| IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, Volume 28, 32ND CONFERENCE, IEEE, (Coral Gables, Florida, US), M. KIMATA et al., "A 480 x 400 Element Image Sensor with a Charge Sweep Device", pages 100-101. * |
| RCA REVIEW, Volume 40, No. 3, September 1979, W.F. KOSONOCKY et al., "Low-Loss Charge-Coupled Device", pages 241-277. * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0438316A2 (en) * | 1990-01-19 | 1991-07-24 | Sharp Kabushiki Kaisha | Image data processing apparatus |
| EP0438316A3 (en) * | 1990-01-19 | 1992-10-28 | Sharp Kabushiki Kaisha | Image data processing apparatus |
| EP0553869A2 (en) * | 1992-01-31 | 1993-08-04 | Kabushiki Kaisha Toshiba | Method for transferring charge, charge transfer device and solid state image sensing device using the same |
| EP0553869A3 (en) * | 1992-01-31 | 1994-02-16 | Toshiba Kk | |
| US5459509A (en) * | 1992-01-31 | 1995-10-17 | Kabushiki Kaisha Toshiba | Method for transferring charge, charge transfer device and solid state image sensing device using the same |
| CN101341735B (en) * | 2005-12-21 | 2010-11-03 | 伊斯曼柯达公司 | Image sensor for still or video photography |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0302101A1 (en) | 1989-02-08 |
| JPH01502310A (en) | 1989-08-10 |
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