WO1988006317A1 - Process for priority-dependent processing of various requests of a computer - Google Patents

Process for priority-dependent processing of various requests of a computer Download PDF

Info

Publication number
WO1988006317A1
WO1988006317A1 PCT/DE1987/000543 DE8700543W WO8806317A1 WO 1988006317 A1 WO1988006317 A1 WO 1988006317A1 DE 8700543 W DE8700543 W DE 8700543W WO 8806317 A1 WO8806317 A1 WO 8806317A1
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WO
WIPO (PCT)
Prior art keywords
priority
requests
computer
intx
int1
Prior art date
Application number
PCT/DE1987/000543
Other languages
German (de)
French (fr)
Inventor
Bernhard Donhauser
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO1988006317A1 publication Critical patent/WO1988006317A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Definitions

  • the invention relates to a method for priority-dependent processing of different requirements of a computer in accordance with the preamble of the main claim.
  • the method for priority-dependent processing of different requirements of a computer with the features of the main claim has the advantage that the different urgent requirements can be assigned correspondingly different priorities, the priority assignment in computer operation being able to be adapted and changed if necessary to changing conditions. It is particularly advantageous to subdivide the requests as far as possible into partial requests or segments with different priorities, so that the segments are placed in different positions of a queue according to their priority. The queue is then processed in sequence. If a request with the highest priority occurs, this request is placed at the top of the queue, unless a request with the same priority has already been placed there. The remaining requirements are shifted down one place.
  • a marker M2 is set thereby, which, however, should have the same priority as the program INT1. Since the priorities of INT1 and INT2 are the same, the request INT2 does not interrupt the running program INT1. The mark M2 is not recognized until INT1 has been processed, so that the request INT2 is then processed.
  • the processing section B framed with broken lines can be added to an interrupt program section as desired, depending on the respective program structure.
  • the markers M1, M2, MX can contain priority identifiers so that the associated request INT1, INT2, INTX can be placed in the appropriate position in the queue provided for the various requests.
  • the high priority requests and the lower priority requests are queued lower according to the priority level.
  • the computer then processes the request at the top of the queue, provided that no request with even higher priority occurs in the meantime.
  • requests can also be divided into segments with different priorities, with the individual segments being queued according to their priority be classified for a long time.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Computer And Data Communications (AREA)

Abstract

A process for priority-dependent processing of various requests (INT1, INT2, INTX) of a computer, in which the requests are assigned a priority label corresponding to their degree of priority and are ranked in corresponding positions in a queue. It is particularly advantageous to divide the requests (INTX) into segments, which may have different priorities, so that particularly time-critical segments (INTX) can be processed immediately and non-critical segments (INTXI) can be processed later. By co-ordinating the priority labels, it is possible to organize the processing of different requests to suit the prevailing peripheral conditions to ensure optimal processing by the computer.

Description

Verfahren zur prioritätsabhängigen Bearbeitung von unterschiedlichen Anforderungen eines Rechners Procedure for priority-dependent processing of different computer requirements
Stand der TechnikState of the art
Die Erfindung betrifft ein Verfahren zur prioritätsabhängigen Bearbeitung von unterschiedlichen Anforderungen eines Rechners gemäß der Gattung des Hauptanspruchs.The invention relates to a method for priority-dependent processing of different requirements of a computer in accordance with the preamble of the main claim.
Während der Bearbeitung eines bestimmten Rechenprogramms oder einer bestimmten Rechnerroutine können unterschiedlicDuring the processing of a specific computer program or a specific computer routine, different things can happen
Anforderungen, die auch als Interrupts bezeichnet werden, auftreten, die mehr oder weniger schnell vom Rechner bearbeitet werden müssen. Diesen Anforderungen können entsprechend hohe oder niedrige Prioritäten zugeordnet sein, wobei die Prioritätszuordnung durch die Hardwarekonfiguration des Rechners vorgegeben sein kann. Eine derartige Prioritätszuordnung ist jedoch nicht flexibel, so daß Änderungen von Prioritäten oder eine Prioritätsanpassung während des Rechnerbetriebs nicht möglich ist.Requirements, which are also called interrupts, occur that have to be processed more or less quickly by the computer. Correspondingly high or low priorities can be assigned to these requirements, the priority assignment being predefined by the hardware configuration of the computer. However, such a priority assignment is not flexible, so that it is not possible to change priorities or adjust priorities during computer operation.
Vorteile der ErfindungAdvantages of the invention
Das Verfahren zur prioritätsabhängigen Bearbeitung von unterschiedlichen Anforderungen eines Rechners mit den Merkmalen des Hauptanspruchs hat demgegenüber den Vorteil, daß den unterschiedlich dringenden Anforderungen entsprechend unterschiedliche Prioritäten zugeordnet werden können, wobei die Prioritätszuordnung im Rechnerbetrieb bei Bedarf an sich ändernde Bedingungen angepaßt und abgeändert werden kann. Dabei ist es besonders vorteilhaft, die Anforderungen, soweit es möglich ist, in Teilanforderungen bzw. Segmente mit unterschiedlichen Prioritäten zu unterteilen, so daß die Segmente entsprechend ihrer Priorität in unterschiedliche Positionen einer Warteschlange eingereiht werden. Die Bearbeitung der Warteschlange erfolgt dann der Reihe nach. Bei Auftreten einer Anforderung mit höchster Priorität wird diese Anforderung an die oberste Stelle der Warteschlange eingereiht, sofern nicht dort bereits eine Anforderung mit gleicher Priorität eingereiht ist. Die übrigen Anforderungen werden dabei um eine Stelle nach unten verschoben.The method for priority-dependent processing of different requirements of a computer with the features of the main claim has the advantage that the different urgent requirements can be assigned correspondingly different priorities, the priority assignment in computer operation being able to be adapted and changed if necessary to changing conditions. It is particularly advantageous to subdivide the requests as far as possible into partial requests or segments with different priorities, so that the segments are placed in different positions of a queue according to their priority. The queue is then processed in sequence. If a request with the highest priority occurs, this request is placed at the top of the queue, unless a request with the same priority has already been placed there. The remaining requirements are shifted down one place.
Zeichnungdrawing
Die Erfindung wird nachfolgend anhand eines in der Zeichnung dargestellten Flußdiagramms näher erläutert.The invention is explained in more detail below with reference to a flow chart shown in the drawing.
Befindet sich der Rechner im Programm H und tritt an einer Stelle H1 eine Anforderung INT1 auf, so wird dadurch eine Markierung M1 auf "1" gesetzt. Ist M = 1 so wird die Anforderung INT1 bearbeitet, wobei das Hauptprogramm zu diesem Zweck unterbrochen wird.If the computer is in the program H and a request INT1 occurs at a point H1, a marker M1 is thereby set to "1". If M = 1, the request INT1 is processed, the main program being interrupted for this purpose.
Tritt nun eine zweite Anforderung INT2 auf, so wird dadurch eine Markierung M2 gesetzt, die jedoch gleiche Priorität wie das Programm INT1 haben soll. Da die Prioritäten von INT1 und INT2 gleich sind, bewirkt die Anforderung INT2 keine Un terbrechung des laufenden Programms INT1. Erst wenn INT1 ab gearbeitet ist, wird die Markierung M2 erkannt, so daß dann die Anforderung INT2 abgearbeitet wird.If a second request INT2 now occurs, a marker M2 is set thereby, which, however, should have the same priority as the program INT1. Since the priorities of INT1 and INT2 are the same, the request INT2 does not interrupt the running program INT1. The mark M2 is not recognized until INT1 has been processed, so that the request INT2 is then processed.
Es wird nun angenommen, daß eine Anorderung mit höherer Priorität als INTX auftritt und eine entsprechende Markierung MX gesetzt wird. Da es sich hier um eine Anforderung höherer Priorität handelt, wird zunächst zumindest der zeitkritische Teil der Anforderung INTX sofort abgearbeitet. Anschließend wird die weitere Bearbeitung der unterbrochenen Anforderung INT2 fortgesetzt, bis diese Anforderung vollständig abgearbeitet ist und die Markierung M2 = 0 gesetzt wird.It is now assumed that a request with higher Priority occurs as INTX and an appropriate marking MX is set. Since this is a higher priority request, at least the time-critical part of the INTX request is processed immediately. Subsequently, the further processing of the interrupted request INT2 is continued until this request has been completely processed and the marker M2 = 0 is set.
Unter der Voraussetzung, daß die Anforderung INTX mit hoherAssuming that the INTX requirement is high
Priorität aus zwei Segmenten unterschiedlicher Priorität besteht, kann nun das weniger kritische Segment INTX1 bearbeitet werden, welches die Markierung MX1 hat. Ist auch die ses Segment INTX1 vollständig abgearbeitet und die Kennung MX1 = 0 gesetzt, so kann wieder zum Hauptprogramm zurückgekehrt werden.Priority consists of two segments of different priority, the less critical segment INTX1 can now be processed, which has the marking MX1. If this segment INTX1 has also been completely processed and the identifier MX1 = 0, you can return to the main program.
Der mit unterbrochenen Linien umrahmte Bearbeitungsabschnitt B kann abhängig von der jeweiligen Programmstruktur beliebig an einen Interrupt-Programmabschnitt angefügt werden.The processing section B framed with broken lines can be added to an interrupt program section as desired, depending on the respective program structure.
Die Markierungen M1, M2, MX können Prioritätskennungen enthalten, so daß die zugehörige Anforderung INT1, INT2, INTX an die entsprechende Position der für die verschiedenen Anforderungen vorgesehenen Warteschlange gesetzt werden kann. Dabei werden die Anforderungen mit hoher Priorität oben und die Anforderungen mit niedrigerer Priorität entsprechend dem Grad der Priorität weiter unten in die Warteschlange eingereiht. Vom Rechner wird dann jeweils die oben in der Warteschlange befindliche Anforderung bearbeitet, sofern zwischenzeitlich keine Anforderung mit noch höherer Priorität auftritt.The markers M1, M2, MX can contain priority identifiers so that the associated request INT1, INT2, INTX can be placed in the appropriate position in the queue provided for the various requests. The high priority requests and the lower priority requests are queued lower according to the priority level. The computer then processes the request at the top of the queue, provided that no request with even higher priority occurs in the meantime.
Entsprechend können auch Anforderungen in Segmente mit unterschiedlicher Priorität unterteilt sein, wobei die einzelnen Segmente entsprechend ihrer Priorität in die Wartesch lange eingereiht werden. Accordingly, requests can also be divided into segments with different priorities, with the individual segments being queued according to their priority be classified for a long time.

Claims

Patentansprüche Claims
1. Verfahren zur prioritätsabhängigen Bearbeitung von unterschiedlichen Anforderungen eines Rechners, wobei Anforderungen mit höherer Priorität eine momentane Bearbeitung einer Anforderung niedrigerer Priorität unterbricht, dadurch gekennzeichnet, daß jeder Anforderung (INT1, INT2, INTX) eine den Grad der Priorität entsprechende Prioritätskennung zugeordnet ist, und daß die Anforderungen (INT1, INT2, INTX) in Abhängigkeit von dem Grad der zugeordneten Priorität in entsprechende Positionen einer Warteschlange eingereiht werden, wobei die in der Warteschlange befindlichen Anforderungen (INT1, INT2) der Reihe nach vom Rechner bearbeitet werden.1. A method for priority-dependent processing of different requests from a computer, requests with higher priority interrupting the current processing of a request with lower priority, characterized in that each request (INT1, INT2, INTX) is assigned a priority identifier corresponding to the degree of priority, and that the requests (INT1, INT2, INTX), depending on the degree of the assigned priority, are placed in corresponding positions in a queue, the requests (INT1, INT2) in the queue being processed in sequence by the computer.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Anforderungen (INTX, INTX1) in vom Rechner separat bearbeitbare Segmente unterschiedlicher Priorität unterteilt sind, denen jeweils unterschiedliche Prioritätskennungen zugeordnet sind, und daß die Segmente (INTX, INTX1) in deren Priorität entprechende Positionen der Warteschlange eingereiht werden.2. The method according to claim 1, characterized in that the requirements (INTX, INTX1) are subdivided into segments of different priority that can be processed separately by the computer, each of which is assigned different priority identifiers, and that the segments (INTX, INTX1) have positions corresponding to their priority queued.
3. Verfahren nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, daß Segmente und/oder Anforderungen (INT1, INT2) gleicher Priorität entsprechend ihrem zeitlichen Auf treten untereinander in die Warteschlange eingereiht werde . 3. The method according to any one of claims 1 or 2, characterized in that segments and / or requests (INT1, INT2) of the same priority are placed in the queue with one another according to their temporal occurrence.
4. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß der Grad der Priorität codiert jeder Anforderung (INT1, INT2, INTX, INTX1) zugeordnet ist. 4. The method according to any one of the preceding claims, characterized in that the degree of priority coded is assigned to each request (INT1, INT2, INTX, INTX1).
PCT/DE1987/000543 1987-02-21 1987-11-23 Process for priority-dependent processing of various requests of a computer WO1988006317A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP3705577.1 1987-02-21
DE19873705577 DE3705577A1 (en) 1987-02-21 1987-02-21 METHOD FOR PRIORITY-DEPENDENT PROCESSING OF DIFFERENT REQUIREMENTS OF A COMPUTER

Publications (1)

Publication Number Publication Date
WO1988006317A1 true WO1988006317A1 (en) 1988-08-25

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PCT/DE1987/000543 WO1988006317A1 (en) 1987-02-21 1987-11-23 Process for priority-dependent processing of various requests of a computer

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EP (1) EP0345255A1 (en)
JP (1) JPH02502227A (en)
DE (1) DE3705577A1 (en)
WO (1) WO1988006317A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415515A2 (en) * 1989-09-01 1991-03-06 Litton Systems, Inc. Computer system
EP0554611A3 (en) * 1991-10-28 1995-12-06 Monarch Marking Systems Inc Spooler for barcode printers
EP0706126A1 (en) * 1994-10-07 1996-04-10 International Business Machines Corporation Multi-priority level scheduler
US6253260B1 (en) * 1998-10-22 2001-06-26 International Business Machines Corporation Input/output data access request with assigned priority handling
US6510479B1 (en) 1999-09-15 2003-01-21 Koninklijke Philips Electronics N.V. Transmit pre-arbitration scheme for a can device and a can device that implements this scheme
US6615302B1 (en) * 1999-09-15 2003-09-02 Koninklijke Philips Electronics N.V. Use of buffer-size mask in conjunction with address pointer to detect buffer-full and buffer-rollover conditions in a CAN device that employs reconfigurable message buffers
US7689749B2 (en) 2004-10-18 2010-03-30 Mstar Semiconductor, Inc. Interrupt control function adapted to control the execution of interrupt requests of differing criticality

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2012084A (en) * 1978-01-09 1979-07-18 Honeywell Inf Systems Queuing data
EP0106366A2 (en) * 1982-10-20 1984-04-25 Hitachi, Ltd. Control Method for internal combustion engines
DE3439560A1 (en) * 1983-10-28 1985-05-23 Ricoh Kk Interrupt-processing method using a microcomputer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2012084A (en) * 1978-01-09 1979-07-18 Honeywell Inf Systems Queuing data
EP0106366A2 (en) * 1982-10-20 1984-04-25 Hitachi, Ltd. Control Method for internal combustion engines
DE3439560A1 (en) * 1983-10-28 1985-05-23 Ricoh Kk Interrupt-processing method using a microcomputer

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415515A2 (en) * 1989-09-01 1991-03-06 Litton Systems, Inc. Computer system
EP0415515A3 (en) * 1989-09-01 1992-02-19 Litton Systems, Inc. Computer system
EP0554611A3 (en) * 1991-10-28 1995-12-06 Monarch Marking Systems Inc Spooler for barcode printers
EP0706126A1 (en) * 1994-10-07 1996-04-10 International Business Machines Corporation Multi-priority level scheduler
US6253260B1 (en) * 1998-10-22 2001-06-26 International Business Machines Corporation Input/output data access request with assigned priority handling
US6510479B1 (en) 1999-09-15 2003-01-21 Koninklijke Philips Electronics N.V. Transmit pre-arbitration scheme for a can device and a can device that implements this scheme
US6615302B1 (en) * 1999-09-15 2003-09-02 Koninklijke Philips Electronics N.V. Use of buffer-size mask in conjunction with address pointer to detect buffer-full and buffer-rollover conditions in a CAN device that employs reconfigurable message buffers
US7689749B2 (en) 2004-10-18 2010-03-30 Mstar Semiconductor, Inc. Interrupt control function adapted to control the execution of interrupt requests of differing criticality

Also Published As

Publication number Publication date
DE3705577A1 (en) 1988-09-01
EP0345255A1 (en) 1989-12-13
JPH02502227A (en) 1990-07-19

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