WO1988003343A1

WO1988003343A1 - Multiplex digital communications system

Info

Publication number: WO1988003343A1
Application number: PCT/US1987/001752
Authority: WO
Inventors: Sang H. Lee
Original assignee: Bell Communications Research, Inc.
Priority date: 1986-10-22
Filing date: 1987-07-23
Publication date: 1988-05-05

Abstract

Method and apparatus for achieving a desired scrambling of high-speed multiplexed digital signals at the outputs of frame-synchronized multiplexers by applying different and equivalent scrambling patterns to each of the tributary signals at the multiplexer inputs. This permits the scrambling to occur at low tributary bit rates with its attendant advantages. The mathematical characteristics of pseudo random sequences can be used to determine the tributary equivalent sequences. Also, empirical methods can be used to determine the equivalent sequences or they can be determined by circuit analysis given the multiplexer block diagram. If the number of lines being multiplexed is an integral power of 2, the equivalent tributary sequences turn out to be the same as the high-speed line sequence except for the starting point or phasing.

Description

Multiplex Digital Communications System

Background of the Invention

This invention relates to multiplexed, digital communications systems wherein improvement of line statistics is achieved by scrambling the high-speed digital signals with pseudo random sequences. More particularly, the invention relates to techniques for achieving a desired scrambling of such high-speed signals by applying equivalent pseudo random sequences to tributary signals before the multiplexing thereof.

Pseudo random sequences (PRSs), also called pseudo noise (PN) sequences, or m-sequences, are binary sequences of N bits length where N=2^m-1. These sequences have many useful properties and are extensively used in range finding, scrambling, fault detecting, modulat ion and synchroni z ing c ircuitry . Such sequences have predictable mathematical characteristics, for example, the autocorrelation function of these sequences is either unity or -1/N. Also the ratio of binary ones to binary zeros is very close to 50-50. This property makes them useful in scrambling digital communication signals for achieving dc balance and sufficient transition density which are important characteristics of high-speed multiplexed signals. These characteristics facilitate the recovery of the clock at the receivers.

Pseudo random sequences are defined by primitive polynomials, h(x), of degree m, wherein m is the highest power of the variable x in the polynomial. Feedback shift registers can be used to generate any PRS by arranging appropriate feedback through modulo-2 adders wherein the outputs of the stages of the shift register representing the terms of the polynomial are applied to the left-hand register stage. Such a register with m stages is capable of repetitively generating a PRS of length N=2^m-1 bits.

Among the known mathematical characteristics of PRSs is the fact that given a PRS of length N bits, any number, L, of other PRSs, all of length N may be derived from the given PRS by alternately selecting the terms of the derived PRSs from the binary terms of the given PRS. This relationship applies only if N and L are relatively prime, that is if they have no common factors. A further characteristic of such derived PRSs is that where L is an integral, non-zero power of 2, i.e., 2, 4, 8 etc., the given and all of the derived sequences turn out to be the same except for the starting points (or the phases).

Part of the inventive concept herein comprises the recognition by the present inventors that the aforementioned mathematical relationships could be utilized to facilitate the application of a desired scrambling PRS to high-speed multiplexed signals by appropriate scrambling of the low bit rate tributary signals at the inputs of frame-synchronous multiplexers. Certain known multiplexed digital systems are frame-synchronous, in which case the frames of all tributary signals are synchronized at each multiplexer in the system by means of such circuitry as frame buffers which are part of the preprocessing circuitry in each tributary line, or by adding new framing bits to each tributary. Such systems permit the framing and related overhead bits or bytes to be sent unscrambled which facilitates the adding or dropping of tributary channels. Non-frame aligned systems have certain advantages however; the randomly varying frame alignment between the tributary channels in such systems makes it impossible to predict what the high-speed line PRS will be with any given set of PRSs applied to the input tributary signals. Thus, in such systems the scrambling must be done on the high-speed line and the present invention is not applicable to such non-frame aligned systems. A recent patent application of J. A, Bellisio entitled "Multilevel Multiplexing," Serial No. 864,037, filed on May 16, 1986, discloses and claims apparatus for achieving frame synchronization with simplified circuitry by providing auxiliary framing bytes which can be displaced or slid relative to the randomly-varying data and conventional framing bytes. The auxiliary framing bytes of all tributary signals are aligned or synchronized at each multiplexer and this facilitates the multi-level multiplexing of such signals. The present invention is applicable to such systems.

Ideal multiplexed systems are those in which the only circuitry which processes the high-speed multiplexed signals are the bit-interleavers of the multiplexers and the bit de-interleavers of the demultiplexers. Such systems will permit the highest degree of multiplexing and hence can carry the maximum amount of information. Scrambling is accomplished by means of modulo-2 addition of the data or intelligence signal with the chosen PRS. This can be accomplished with simple circuitry comprising an Exclusive-Or gate to which the two signals are applied. Such simple circuitry presents many practical problems when it is desired to operate at bit rates in the gigabit region of the spectrum. By scrambling each of the input tributary signals at a multiplexer, the scrambler bit rate is reduced by a factor equal to L, the number of tributary channels being multiplexed. This tributary scrambling has not been effectively used in the prior art since no one knew how to choose the equivalent tributary scrambling patterns or sequences (PRSs) to achieve the desired scramble of the high-speed signal at the multiplexer output. Prior art systems have used tributary scrambling only for multiplexing factors (L) of 3 or 4, or have combined tributary scrambling with line coding. In addition to facilitating tributary scrambling, the present invention can be used to provide separate scrambling of each of n, parallel lines in a parallel system prior to parallel-to-serial conversion, to provide a scrambled serial signal with n times the bit rate of the parallel signals.

It should be noted that the aforementioned copending application entitled "Multilevel Multiplexing" describes systems in which scrambling and descrambling are achieved in tributary preprocessors at each multiplexer, however, there is no teaching therein of the relationship between the equivalent tributary PRSs and the desired high-speed line PRS.

Summary of the Invention

In the multiplexed, digital systems of the present invention a desired pseudo random sequence of length N is determined for each high-speed signal in the system, the systems being frame-synchronous and each multiplexer therein having a multiplexing factor L with L and N being chosen as relatively prime. Each of the multiplexers has preprocessing circuitry for processing each tributary signal applied thereto, the circuitry comprising means to scramble each of the tributary signals with an equivalent pseudo random sequence of length N, the equivalent pseudo random sequence being chosen to yield the desired PRS at the output of each multiplexer in the system, and wherein the equivalent PRSs are determined from the known mathematical characteristics of PRSs or by empirical methods. At the demultiplexers, descrambling is accomplished after the high-speed signals are deinterleaved, using the same equivalent tributary PRSs for descrambling. The present invention comprises a digital multiplexed system which permits a desired scrambling pattern to be achieved on a high-speed multiplexed line by the proper choice of pseudo random sequences applied to each input tributary signal at the inputs of each multiplexer in a frame-synchronous system. The equivalent tributary sequences can be obtained from formulae or can be derived empirically, for example by de-interleaving a desired high-speed line PRS into L different sequences which are recorded to yield the equivalent tributary sequences.

This concept can also be applied to parallelto-serial converters to permit scrambling at the low bit rate of each parallel line and to yield a desired scrambling of the high-speed serial signal.

The PRSs can be generated by known means such as feedback shift registers or can be stored in look-up tables (or memories). Where the number of lines being multiplexed is an integral power of 2, the desired and all of the tributary equivalent PRSs turn out to be the same except for the starting points, n, (or the phasing thereof). In such cases each of the tributary signals may include in its overhead a SEED byte denoting the starting point and this SEED byte can control the descrambling circuitry at any demultiplexer in the system.

The invention also comprises a novel method of achieving any desired scrambling pattern (or PRS) on a high-speed multiplexed digital line at the output of a multiplexer by the proper choice of equivalent PRSs applied to each input tributary signal at the multiplexer. The invention also comprises novel circuitry by which the aforementioned concepts may be implemented. It is thus an object of the invention to provide an improved digital multiplexed system in which a desired high-speed line scrambling pattern can be achieved by the proper choice of tributary equivalent scrambling patterns. Another object of the invention is to utilize the known mathematical characteristics of pseudo random sequences to achieve a desired scrambling of a high-speed digital line signal at the output of a multiplexer in a frame-synchronous system by applying equivalent PRSs to each of the tributary signals at the multiplexers. A further object of the invention is to provide novel circuitry for generating a plurality of PRSs which comprise the same sequence with different starting points. A still further object of the invention is to provide a digital multiplexed communication system which is frame-synchronous with a desired scrambling pattern (PRS) of length N on the high-speed lines at the outputs of each of the multiplexers in the system, the multiplexers each having multiplexing factors L, wherein L is a non-zero integral power of 2, and wherein each of the L tributary signals applied to each of the multiplexers has applied thereto the same PRS as the desired scrambling pattern except that each of the patterns applied to the L tributary signals has a different starting point than that of the desired PRS on the high-speed line. The tributary PRSs with different starting points can be generated by means of a ring or circular type memory or look-up table in which the digits of the PRS are stored, or they may be obtained from the outputs of a plurality of feedback shift registers.

These and other objects and advantages of the invention will become apparent from the following detailed description and the drawings.

Brief Description of the Drawings

Figures 1a, 1b, 2a, and 2b illustrate two pseudo random sequences and circuitry for generating them.

Figure 3 represents a non-frame synchronous multiplexing system.

Figure 4 represents a multiplexing system to which the present invention is applicable.

Figures 5 and 6 are diagrams of multiplexer/demultiplexers, illustrating how the equivalent pseudo random sequences are determined.

Figure 7 illustrates the derivation of the starting phases of equivalent tributary sequences using the teachings of the present invention.

Figure 8 represents the solution of Equation (7) for many combinations of L and N. Figure 9a illustrates a particular sequence with

N=31.

Figure 9b illustrates a multiplexer in which the tributary sequences are that of Figure 9a. Figure 10 represents another multiplexer with

L=4 and N=31.

Figure 11 shows a prior art multiplexer. Figures 12 and 13 show a multiplexer/demultiplexer according to the present invention.

Figure 14 shows a scrambler/descrambler with a programmable pseudo random generator.

Figure 15 shows a scrambler/descrambler including a pseudo random sequence generator with a circular memory.

Figure 16 shows tributary processing circui try which may be used to implement the present invention.

Figure 17 shows part of the circuitry of Figure 16 in more detail. Figure 18 is a system embodying the present invention. Detailed Description

Two sets of pseudo random sequences of length N=7 can be generated since two primitive polynomials exist for N=7. The two polynomials are h(x) =x3+x+1 and h(x) =x³+x²+1. the two sets of sequences corresponding to these polynomials are shown in Figures 1a and 2a, respectively. The digital sequence of Figure 1a is 1110010 1110010, which comprises a 7 digit binary sequence repeated once. Any repetitive 7 digit sequence comprises 7 distinct 7-digit sequences, each with a different starting point. The starting points can be denoted as n=1 through n=7. In Figure 1a, two of these different sequences are denoted by the rectangular dashed-line boxes or windows labeled as n=1 and n=4. If the sequence is repeated once as in Figures 1a and 2a, the N different component sequences can be determined by sliding an N- digit long window, such as those illustrated, along the sequence. The sequences of Figures 1a and 2a can each be thought of as a single 7 digit sequence, with 7 different starting points, n=1 to n=7. The polynomial h(x)=x³+x+1, wherein m=3, specifies an m-stage feedback shift register wherein the feedback is accomplished through modulo-2 adders (or Exclusive-Or gates) which are arranged in accordance with the terms of the polynomial. For example, the sequence of Figure 1a will be repetitively generated by the 3-stage register of Figure 1b. The three binary stages of this register are 11, 13, and 15. The binary sequence appears on output line 19 as the register is clocked to shift the contents thereof to the right. The input of stage 15 is labeled x³, the Input of stage 13, x² and the input of stage 11, x. The output of stage 11 is labeled 1. The modulo-2 adder 17 adds the output 1 of stage 11 and the output, x, of stage 13. The sum or the output of adder 17 is applied to the input of stage 15. This circuitry will repetitively generate the sequence of Figure 1a since its feedback circuitry modulo-2 adds the x and 1 signals to form the x³ term. The initial binary states of the three register stages determines which of the 7 different sequences will be generated, or what the starting point of the single sequence is. For example, if all of the register stages of Figure 1b are initially binary 1, the starting point will be n=1 and the sequence 1110010 will be repetitively generated at output 19 as the shift register is clocked and all digits are shifted to the right.

Figure 2a illustrates the other sequence (or set of sequences) corresponding to the primitive polynomial h(x)=x³+x²+1, the n=1 sequence of which is 1110100 and the n=6 sequence of which is 0011101, as illustrated. The feedback shift register of Figure 2b, with a single modulo-2 adder having as inputs the x² and 1 terms of the polynomial and its output feedback as the x³ term will repetitively generate these 7 sequences, again depending on the initial states of the register stages. The n=1 sequence will be generated if all three register stages are initially in the 1 state. Thus, any one of the 2^m-1 different sequences may be generated by the proper selection of the 2^m-1 different initial states of the register stages. At least one stage must be initially binary 1 or only a meaningless string of o's will be generated. Thus, the length of all pseudo random sequences is always 1 less than 2 raised to m, the degreee of the polynomial corresponding to tne sequence. Thus, N may equal 7, 15, 31, 63, etc. Further details concerning pseudo random sequences will be found in an article entitled "Pseudo Random Sequences and Arrays" by MacWilliams and Sloan in the Proceedings of the IEEE, Vol. 64, No. 12, December 1976.

Figure 3 shows a 2 to 1 multiplexer 31 with two input tributary signals 33 and 35 and a high-speed multiplexed output signal 39. This system is a non-frame synchronous one to which the present invention is not applicable because the random and varying phase slippage between the tributary input signals, indicated by the double-headed arrow 37, makes it impossible to predict the output line pseudo random sequence (39) with any given set of sequences applied to the tributary signals.

Figure 4 illustrates a frame-synchronous system in which the framing bytes, F, and the overhead bytes, OH, of both of the tributary signals 43 and 45 are synchronized and have applied thereto different equivalent pseudo random sequences, indicated by the oppositely slanted shading of the intelligence portion of the signals between the framing bytes and the overhead bytes. The output high-speed signal 47 will have a predictable PRS which is a composite of the two input sequences, as indicated by the cross-hatched intelligence signal of the output line 47. Figure 5 is a simplified system which illustrates the mode of operation of the invention. A multiplexer (or demultiplexer) 59 has two input/output tributary lines 61 and 63 and high-speed input/output line 65. This illustrative system uses the 7 digit sequence of Figure 1a. If the high-speed line 65 has the illustrated PRS thereon, with starting point n=1, it is a simple matter to deduce the demultiplexed or equivalent sequences resulting therefrom on the tributary lines 61 and 63. This can be done by circuit analysis (or by hand) by simply alternately selecting the terms of the input sequence on line 65 and forming therefrom the two output or tributary sequences. It is assumed that the deinterleaver 59 will first connect the line 65 to line 61, then to 63 and then back to 61, etc. Thus the first digit of the sequence on line 65 will form the first digit on line 61 and the second digit on line 65 will form the first digit on line 63, and so on. It can be seen from inspection of the two sequences on lines 61 and 63 that each is the same sequence as that on the input high-speed line, but each with different phases, or starting points. Line 61 has a starting point of n=2 and for line 63, n=6. The mathematical characteristics of pseudo random sequences will result in such a relationship between the high-speed line sequence and all tributary sequences as long as the number of tributary lines is an integral, non zero power of 2, i.e., 2, 4, 8, etc. Also, it is apparent from the reciprocity theorem that if the circuit is being used as a multiplexer (or bit interleaver) and the illustrated tributary sequences are applied to the tributary lines 61 and 63, the high-speed output line 65 will have the desired illustrated sequence applied thereto, thus the illustrated tributary sequences are the equivalent sequences required to produce the desired high-speed line sequence. When the number of lines being multiplexed, L, also called the multiplexing factor, is not an integral power of 2, the desired and equivalent tributary sequences will not be the same sequence (or the same set of sequences); however the sequence lengths, N, will be the same if L and N have no common factors. This restriction usually obtains in any event, since 7, 31 and 63 are all prime numbers and L would seldom be chosen as any of these. Figure 6 shows a 3 to 1 multiplexer/demultiplexer in which the desired sequence on high-speed line 51 is the 7 bit sequence of Figure 1a with starting point n=4. Circuit analysis shows that the illustrated three tributary sequences will appear on tributary lines 53, 55, and 57 as the illustrated highspeed sequence is de-interleaved by demultiplexer 49. Inspection of the three tributary sequences shows that they are all the other 7 bit sequence (or set of sequences), shown in Figure 2a, with different starting points, namely, n₁₌6, n₂₌4, and n₃=2, for the three lines 53, 55, and 57, respectively.

For more complex systems, the circuit analysis method of determining equivalent tributary sequences can be aided by electronics. For example, the desired high- speed line sequence can be recorded and fed to an operating de-interleaver which can drive recording devices connected to each tributary l ine to recor d the resultant tributary sequences . For example, a printer or a CRT may be arranged to record all the output sequences properly lined up by rows and columns.

The mathematical characteristics of pseudo random sequences can be generalized through the following analysis. S. W. Golomb in his book entitled Shift Register Sequences, 1982, Aegean Park Press, states and proves the following theorem: if {a_k} is a pseudo random sequence of period N, then {a_LK} is also a pseudo random sequence with the same period, if and only if gcd (L,N)=1 (in other words, if L and N have no common factors except 1).

This theorem means that if the PRS {a_K } of length N is de-interleaved into L tributary PRSs, each tributary sequence will also have N digits but each will have a different starting point (or phase). These L sequences can be represented by the following notation:

TABLE I

In order to find the starting points or phases of each of the sequences represented by each of the rows of the above matrix, we first assume that the starting point of a_{1 , 1}is 1. Then the starting point of a_1,n can De expressed as: a_{1 , n} = ( 1+ ( n- 1 ) L ) _N ( 1 )

wherein ( )_N represents modulo N, except the (N)_N=N instead of zero. Our objective is to find the starting point of the 1^th tributary sequence, {a_Lk}¹. This is the phase of starting point of the digit a_{1 ,1} in the matrix of Table I. Let n₁ be the starting point or phase of the 1^th tributary, then,

a1,1 = a_1,n₁ (2)

Substituting (2) into (1) yields,

1 = (1+(n₁-1)L)_N (3)

In the same way we can derive the starting point of the (1+1)^th tributary sequence, as follows:

1+1 = (1+(n₁₊₁-1)L)_N (4)

Subtracting (3) from (4) yields,

1 = ((n_1+1-n₁₎L)_N (5)

Now let

Δ=n₁₊₁-n₁ (6)

Thus Δ is the starting point difference between each pair of adjacent tributary sequences. Combining (5) and (6) yields the final important equation,

1-(ΔL)_N = 0 (7)

Equation (7) can be interpreted as requiring the phase relationships shown in Figure 7 between the L equivalent tributary sequences applied therein to multiplexer 301, to yield the high-speed line sequence {a_k}. As shown In this figure, each of the equivalent tributary sequences has a starting point or phase equal to Δ digits greater than that of the preceding sequence. Equation (7) does not give the starting point of the high-speed sequence {a_k} , since for all odd and some even values of L, the high-speed and tributary sequences will be different PRSs and hence the relative starting points thereof have no meaning. However, the preceding analysis proves that the high-speed sequence {a_k} is a PRS of N digits and yields the starting points of all tributary sequences. As long as the scrambling takes place at the tributary level, there is no need to know the phase or starting point of {a_k }

Figure 8 provides in tabular form the solution of Equation (7) for N equal to 31, 63, 127, and 255, and for L (the multiplexing factor) from 2 through 32. These solutions cover almost all practical cases. As examples of the use of the information in the table of Figure 8, let us assume that a sequence of N=31 digits is desired for a high-speed line PRS. There are six different PRSs (or sets of PRSs) with N=31, corresponding to the following six primitive polynomials:

h1(x) = x⁵+x²+1, h₂(x) = x⁵+x³+1,

h3(x) = x⁵+x⁴+x²+x+1, h₄(x) = x⁵+x⁴+x³+x +1, h5(x) = x⁵+x³+x²+x+1, and h₆ (χ) = x⁵+x⁴+x³+x²+1.

The respective PRSs corresponding to these polynomials are as follows: 0000 1001 0110 0111 1100 0110 1110 101; 0000 1010 1110 1100 0111 1100 1101 001; 0000 1110 0110 1111 1010 0010 0101 011; 0000 1101 0100 1000 1011 1110 1100 111; 0000 1011 0101 0001 1101 1111 0010 011; and 0000 1100 1001 1111 0111 0001 0101 101. If L=3, from Figure 8 we get the solution Δ = 21. Further assume that the chosen PRS corresponds to the aforementioned h₁(x) = x⁵+x²+1, and that the starting phase of the first tributary sequence is arbitrarily chosen as 5. Figure 9b shows the aforementioned PRS corresponding to h₁(x) on the first tributary, with the starting point of 5. As can be s een from Figure 9b, the starting points of the second and third tributary sequences are easily found by simply adding +21 to the starting points of the preceding tributary. Figure 9b also shows that the high-speed PRS on the left side of the multiplexer 303 resulting from these three tributary sequences is another 31 bit sequence which corresponds to the aforementioned polynomial h₄(x). Figure 9a shows the PRS corresponding to h₁(x) with all the digits thereof numbered. Note that the starting point 16 of the third tributary sequence of Figure 9a is less than the starting point 26 of the second tributary. This results from the fact that the starting point 16 is in the next repetition of the constantly repeating sequence. Thus if we add 5 to the starting point 26 of the second tributary sequence, the digit 31 of the sequence is arrived at and the next digit is 1. Thus, the starting point of the third sequence is 21-5 or 16. The modulo arithmetic of equation (7) automatically compensates for these transitions between the repeating sequences. If Δ is larger than the remaining number of digits from the starting point of the preceding sequence, the N complement of Δ can be subtracted from the preceding sequences starting point. Thus in the example of Figure 9a, the N complement of 21 is 31-21 or 10 and this number could have been subtracted from 26 to arrive at 16 for the starting point of the third tributary sequence.

As another example, assume that N=31, L=4 and that the sequence corresponding to h₁(x) is desired to be applied to the tributary lines, with a starting point of 1 in the first tributary. In this case Δ = 8 and the tributary sequences with their starting points are all illustrated in Figure 10. It can be seen that the resultant high-speed sequence in this case is also the same sequence corresponding to h₁(x). This follows from the fact that L is an integral power of 2. In Figure 10 the 4 to 1 multiplexer is indicated by reference numeral 305.

Figure 11 shows a prior art multiplexer/demultiplexer 87 in which scrambling/descrambling is done in the high-speed line 91 by means of modulo adder 89, to which the desired PRS is applied via line 93. Assuming that the high-speed line bit rate Is 2.24 gigabits/sec, the scrambling must be done at this frequency. Figure 12 shows a circuit in which a tributary scrambling is utilized to reduce this scrambling frequency by a factor of 16. Figure 12 shows a 16 to 1 multiplexer/demultiplexer 95 comprising high-speed line 97 and 16 tributary lines numbered 1-16. The double-ended arrows on these lines indicate that the same circuitry can function either as a multiplexer or as a demultiplexer. In this system the PRS selected has 31 digits and since 16 is a power of 2, the desired sequence in line 97 and all of the tributary sequences will be the same except for starting points. There are 6 sets of 31 digit PRSs as noted above. The particular one selected for the circuit of Figure 12 is as follows: 0000 1001 0110 0111 1100 0110 1110 101, which corresponds to the primitive polynomial, h₁(x)=x⁵+x²+1. The starting points n1 through n-₁₆ of the tributary lines are indicated at the sequence inputs of the modulo-2 adders, such as 96, in each tributary line. The intelligence signal to be scrambled forms the other input of each modulo-2 adder, as shown for example by line 103 for line 1. The starting points of the equivalent tributary sequences could have been determined by means of the empirical techniques discussed above, but in this case have been determined with the aid of a formula derived partially from the known mathematical characteristics of PRSs and partly from empirical observations. This formula is as follows:

n₁ = f(2^m[ 1 +n₀-1+c]/L)

wherein: c = L-1 if m = 2, 4, 6 (8)

c = 0 if m = 3, 7

c = m(L-1) if m = 5

n1 = 1,2,3,...N is the starting point of the sequence of the 1^th tributary. n₀ is the starting point of the sequence on the high-speed line, and usually equals 1. The function f is evaluated the same as modulo-N except that f(N) equals N instead of 0. Thus if the number in parenthesis comes out as N, n_{1 =} N. For any other number the parenthesis is evaluated modulo-N. For example, for line 1 of Figure 12, 1=1, m=5, L=16, n₀=1, and c=5(15)=75. Thus the value of the function is 32/16(1+1-1+75) = 2(76) = 152. The modulo-31 value if this function is: 152-4(31) = 28.

Equation (8) is a special formula which yields all of the tributary sequence starting points as well as the high-speed sequence starting point for all sequences from m = 2 through m = 7, for cases where L is an integral power of 2. Examples of such sequences not already stated herein are as follows: 011, corresponding to h(x) = x²+x+1; 0001 0011 0101 111, corresponding to h(x) = x⁴+x+1; 0000 0100 0011 0001 0100 1111 0100 0111 0010 0101 1011 1011 0011 0101 0111 111, corresponding to h(x) = x⁶+x = 1; and 0000 0010 0000 1100 0010 1000 1111 0010 0010 1100 1110 1010 0111 1101 0000 1110 0010 0100 1101 1010 1101 1110 1100 0110 1001 0111 0111 0011 0010 1010 1111 111, corresponding to h(x) = x⁷+x+1. A still further reduction can be made in the scrambling bit rate if for example the 16 input tributary lines of Figure 12 originate from 8 bit parallel devices, for example a keyboard which encodes characters in parallel 8-bit ASCII code, which must be converted to serial format prior to application to a multiplexer such as that of Figure 12. In such a case the scrambling can be done when the tributary signals are in the parallel format to result in a further 8-fold reduction in scrambling frequency. Thus the 2.24 gigabit/sec. highspeed line signal could be effectively scrambled at 17.5 megabits/sec. A parallel-to-serial converter for accomplishing this is shown in Figure 13. It is assumed that this circuitry would form the input tributary scrambling for line 16 of Figure 12 and would replace the circuitry shown in dashed-line box 104. Since a parallel-to-serial converter is nothing more than a frame-synchronous multiplexer, the symbol 99 of Figure 13 is the same as the multiplexer/demultiplexer symbols of the other figures. Since the starting point of the tributary equivalent sequence of line 16 is 27, the sequence at the output of the converter 99 would have its starting point equal to 27. Thus in the above formula

(8), n_o would be equal to 27, L to 8, m to 5, and n₁ would refer to the 8 input lines of the parallel-to-serial converter 99. Solution of equation (8) with these values results in the starting points n₁ through n₈ as applied to the corresponding parallel input lines of Figure 13. The intelligence signals and the pseudo random sequences would be applied to the 8 modulo-2 adders such as 110 just as they are in lines 1-15 of Figure 12. The first step in choosing a PRS is to select N, which as a practical matter should be no less than 31, in order that the mark density be kept close to 50%. N must be relatively prime with respect to L, as explained above. In systems like that of Figure 12 where L is an integral power of 2, the seed byte will be an m-bit byte which identifies the starting points of the sequences at the different tributaries. If N=31 there are only 6 different sequences (or sets of sequences) which may be chosen, since there are only 6 primitive polynomials of degree 5. The chosen PRS will be used system-wide. Thus each tributary signal will have its distinctive seed byte which can be utilized by receivers or retransmitting circuitry to phase or select the proper starting points of local PRS generators used for descrambling. Like the framing and other overhead bytes, the seed byte is left unscrambled. During the add or drop of tributaries from one multiplexing facility to another, it may be necessary to descramble using one SEED and rescramble using a different one. If the SEED is embedded in the overhead information, then scrambled tributaries from other facilities can be dynamically switched and added to a multiplexed facility. It is possible to eliminate the seed bytes in the overhead structure and use only hard-wired SEEDS at the different bit interleaver/de-interleaver tributary processing circuits. This, however, would eliminate the element of dynamism in the add/drop of scrambled tributary signals. Figure 14 shows a scrambler/descrambler utilizing a programmable 5-stage feedback shift register for generating a 31 bit PRS, and illustrating how the m or 5-bit seed byte determines the starting point of the sequence generated. The register comprises the stages 121, 123, 125, 127 and 129 and feedback modulo-2 adder

131. This circuitry will generate the aforementioned 31 bit PRS corresponding to the polynomial h(x) =x⁵+x²+1. the PRS output on line 139 is applied to one input of the scrambler/descrambler 133 which is also a modulo-2 adder. The data signal 135 forms the other input of adder 133, and this signal may be scrambled or unscrambled depending on whether the circuit is functioning as a scrambler or a descrambler. The initial states of the register stages are determined by the binary states of the signals of the seed byte on the five lines 141. Each digit of the seed byte is applied to a different register stage, as shown, to set the initial binary state thereof and thus to determine the starting point (or phase) of the output PRS on line 139.

Figure 15 shows how an N-digit circular memory,

149, may be controlled by the m-bit seed byte to generate on output line 144 the desired PRS with the proper starting point determined by the value of the seed byte.

In Figure 15, the modulo-2 adder 143 scrambles or descrambles the data signal applied thereto on line 145.

The scrambled or unscrambled data signal appears on output line 147. The SEED determines the initial address of the circular memory to be accessed, as explained above.

During scrambling, the frame pulse or strobe could reset the table pointer to an offset determined by a preselected

SEED and the SEED could be written into the appropriate overhead seed byte. During descrambling, the SEED would be extracted and used to compute a table offset for PRS readout.

A recommended procedure for scrambling/descrambling at any tributary processor in a system using the concepts disclosed herein would include the following steps:

1. Frame detection; examination of the SEED; and transfer thereof to a feedback shift register.

2. PRS generation and data scrambling using the received SEED. It might be necessary to reset the shift register to the SEED at every frame strobe if the frame length is not an integral multiple of N.

3. The transfer of a new SEED into the shift register and into that tributary's overhead or SEED byte in the frame.

4. PRS generation and data scrambling using the new SEED.

Figure 16 is a block diagram of tributary signal processing circuitry that utilizes a parallel scrambler and a sequence with N=31. This requires a 5-stage feedback shift register as illustrated in Figure 14. This circuit also requires a translation table read-only memory of size 32 by 5 for mapping seed values into feedback shift register initial states. Since scrambling/descrambling is frame synchronous, frame detection and alignment must precede the scrambling/descrambling function. Thus, in Figure 16 the block 151 performs frame detection and alignment and also serial-to-parallel conversion on the serial incoming data stream applied thereon via line 155. The parallel data output lines are indicated by reference numeral 157, the slash with the number 8 indicating that there are eight separate lines. The circuit 151 also passes bytes and strobe signals to the scrambler/descrambler 153. There are five strobes: the frame byte strobe (FSTB), the span-ID strobe (SPSTB), the control byte strobe (CSTB), the SEED byte strobe (SDSTB) and the data byte strobe (DSTB) all carried on the lines 159, 161, 163, 165 and 167, respectively. These strobes indicate the presence of the corresponding bytes on the parallel data output lines 157. The scramble/descramble circuit 153 does not alter the framing, control or span-ID bytes and merely passes them through to output line 173. Parallel-to-serial conversion is done in the circuit 153 and the serial data bit stream appears on output line 173, which is connected to a bit interleaver (not shown) together with the output lines from all other tributary processing circuits at the multiplexer. A hard-wired SEED (XMT-SEED) with m bits is applied via line 169 to circuit 153 and a strobe signal (LD-SEED) on line 171 determines whether the hard-wired seed or the seed extracted from the incoming stream is to be used in the scrambler/descrambler. The mode of operation of the scrambler/descrambler is determined by the enable signals, SCEN (scramble enable) on line 177 and the DCEN (descramble enable) on line 175. The first mode of operation is "pass through" in which data is neither descrambled nor scrambled. In this case the circuit of Figure 16 functions as a pure framer. This mode is achieved if SCEN=DCEN=0 , that is, the signals on lines 175 and 177 are both binary 0. The second mode Is "scramble only" in which the data is scrambled with hard-wired seed (XMT-SEED) which is also inserted into the seed byte of the outgoing signal. This mode is used prior to multiplexing at channel end points and corresponds to

SCEN=1 and DCEN=O. The third mode is "descramble only" in which there are two sub-modes. In the first sub-mode (LD-SEED=0), the SEED is extracted from the received signals by the circuit 151 and applied to the circuit 153 for descrambling purposes. In the second sub-mode (LD- SEED=1), the hard-wired seed is used to descramble. This mode is used after demultiplexing at channel end points of channels received from a transmission facility and corresponds to SCEN=0 and DCEN=1. The fourth mode is "descramble and scramble" in which descrambling is done on the basis of the SEED extracted from the incoming signal and scrambling is done with the hard-wired SEED, which is also injected into the outgoing seed byte. This mode is used with add or drop scrambled tributaries from one multiplexed facility to another. The ability to change the basis for scrambling (the SEED) is essential for dynamic add-drop, since the SEED is dependent on the tributary number and multiplexing factor, L. This mode corresponds to SCEN=DCEN=1. Figure 17 shows a circuit like that of circuit

153 of Figure 16, in more detail, and which can perform most of the same functions. The strobe lines 159, 161, etc., and the parallel data input lines 157 and the control inputs to this circuit have the same reference numerals in the two figures. The parallel data lines 157 are applied to five different registers 201, 203, 205, 207 and 209, each of which has a different one of the five strobe signals, FSTB, SPSTB, etc., applied thereto, as illustrated. It should be noted that each of these five registers actually comprises 8 parallel registers, one for each of the 8 parallel input lines. The 5 strobe signals indicate when the corresponding bytes appear on the 8 parallel input data lines 157 and these bytes are stored in the registers and later clocked out to the succeeding circuitry, namely, to the formatter 211 or to the scrambling/descrambling circuitry. As noted above, the framing, span-ID and control bytes from the registers 201, 203 and 205 always pass through this circuitry unaltered. The lines 213, 215 and 217 on which these bytes appear are applied directly to formatter 211 where they are assimilated into the outgoing serial data signal (SDO) on line 173. The formatter also performs parallel-to-serial conversion. The outgoing data signals on lines 224, which may be scrambled or unscrambled, as well as the appropriate seed byte on line 219 are also assimilated into the outgoing SDO on line 173. The circuitry includes two PRS generators, one of which (223) has as its input the incoming SEED obtained from register 207 via line 218, and the other of which (225) receives its m-bit input from line 169 (XMT-SEED), on which the hard-wired SEED appears. These PRS generators may be of the types shown in Figures 14 or 15. The output of generator 223 is applied to descrambler 237 and the output of generator 225 is applied to both of the scramblers 235 and 231. The data bytes on line 221 at the output of register 209 are applied to the descrambler 237 and to scrambler 235 as well as to the O input of four-way selector 241. The output 239 of descrambler 237 forms the 1 input of selector 241 and is also applied to the input of scrambler 231. The output (243) of scrambler 235 forms the 2 input of selector 241 and the output (233) of scrambler 231 the 3 input thereof. The binary state of the two control input signals of the selector 241 on lines 175 (DCEN) and 177 (SCEN) determines which of the four input signals will be applied to the formatter over lines 224. The selector is thus a form of four-way electronic switch. The flip flop or two-way electronic switch 172 has as its 1 input the incoming seed byte from line 218 and its 0 input is the hard-wired SEED from line 169. The state of this switch determines which of these seed bytes is applied to the outgoing signal SDO via lines 219. The control input of this circuit is the binary signal LD-SEED applied thereto via line 171. If DCEN=SCEN=0, then the data signal is passed through and the 0 input of selector 241 is connected to lines 224. If DSEN=1 and SCEN=0, the descrambled signal from circuit 237 is selected for application to the formatter. If DSEN=0 and SCEN=1, then the 2 input of selector 241 Is connected to lines 224 and the scrambled data output of circuit 235 is applied to lines 224. If DSEN=SCEN=1, the incoming data signal from register 209 is descrambled in circuit 237, using the sequence derived from generator 223, then the descrambled data is applied to scrambler 231 via line 229 for rescrambling with the output of generator 225. The output of circuit 231 is applied to the selector's 3 input via line 233 and thence to lines 224.

Figure 18 shows a diagram of a simplified multiplexing system embodying the concepts of the present invention. The multiplexer 250 has applied thereto three tributary lines, 253. The preprocessors 255, 257 and 259 comprise means to scramble the tributary signals with the aforementioned equivalent pseudo random sequences, as well as other processing circuitry. The signals are then applied to the interleaver 251 to form the high-speed signal on line 277. The demultiplexer 256 comprises deinterleaver 261 and framing circuit 265 which has as its input one of the tributary output signals via line 263 and which has Its output on line 267 connected to the deinterleaver to adjust the phasing thereof. The tributary signals are applied to processing circuits 269, 271 and 273, wherein descrambling takes place by means of the equivalent pseudo random sequences generated locally by means of the hard-wired SEED or by the extracted incoming SEED, as explained above in connection with Figures 16 and. 17. The descrambled tributary signals appear on output l i nes 275 .

While the invention has been described in connection with illustrative examples, obvious variations therein will occur to those skilled in the art, without the exercise of invention, accordingly, the invention should be limited only to the scope of the appended claims.

Claims

What is claimed is:

1. A multiplexed digital communication system comprising one or more multiplexers utilized to interleave tributary signals to form high-speed signals on high-speed lines and wherein one or more demultiplexers are provided for demultiplexing said high-speed signals, said system being frame synchronous, said system further compri sing means to achieve a desired pseudo random pattern or sequence of length N digits on said high-speed lines by the correct choice and phasing of equivalent pseudo random sequences also of length N which are used to scramble each of said tributary signals at each of said multiplexers and to descramble the same tributary signal at each of said demultiplexers, and wherein the number of lines, L, being multiplexed and the said number, N, are chosen to be relatively prime, that is L and N have no common factors.

2. The system of claim 1 wherein L is chosen as a non-zero integral power of 2, whereby said pseudo random sequence on said high-speed lines and said equivalent sequences applied to each of said tributary lines will be the same, except for different phasings or start ing points.

3. The system of claim 1 wherein means are provided to provide each of said tributary signals with an overhead SEED byte indicating the starting points of each of said equivalent pseudo random sequences.

4. The system of claim 1 wherein the choice of said equivalent pseudo random sequences is achieved empirically by circuit analysis of the system or by deinterleaving the said desired pseudo random sequence and observing the resulting tributary equivalent sequences.

5. In a frame-synchronous, multiplexed digital communication system in which a desired pseudo random sequence of length N has been selected for scrambling the high-speed signals therein, and wherein the multiplexing factor, L, and N are relatively prime, said system comprising one or more multiplexers and one or more demultiplexers, said multiplexers comprising preprocessing circuitry for processing each tributary signal applied thereto, said preprocessing circuitry comprising means to scramble each of said tributary signals with an equivalent pseudo random sequence of length N, said equivalent pseudo random sequence being selected to yield said desired pseudo random sequence at the output of each said multiplexer in said system, and wherein said equivalent pseudo random sequences are determined from the known mathematical characteristics of such sequences or by empirical methods, and wherein said demultiplexers comprise means to de-interleave said high-speed signals and to then descramble the resulting tributary signals using said equivalent pseudo random sequences.

6. A method of achieving a desired pseudo random scrambling pattern or sequence on a high-speed multiplexed digital line, in a frame synchronous system wi th a mu lt ip lexing fa ctor of L , sa id pattern compr i s ing a pseudo random sequence of length N which is derived from a primitive polynomial, and wherein L and N are relatively prime, comprising the steps of scrambling each of the tributary signals used to form said high-speed signal with a different pseudo random sequence also of length N and choosing said different sequences so that when said different sequences are interleaved, the said desired scrambling pattern will be formed on said high-speed line.

7. The method of claim 6 wherein said different pseudo random sequences are determined by de-interleaving the desired high-speed line sequence and observing the resultant tributary sequences.

8. The method of claim 6 wherein said different pseudo random sequences are determined by circuit analysis of the multiplexed system.

9. The method of claim 6 wherein the starting points of said different pseudo random sequences are determined from the relationship, 1-(ΔL)_N = 0, wherein the starting point of any of said different sequences is Δ digits greater than that of the next preceding sequence.

10. A multiplexed digital communication system comprising one or more multiplexers with L tributary signals connected thereto, and one or more demultiplexers, said multiplexers and demultiplexers connected with highspeed lines, and means connected to said multiplexers to produce a desired pseudo random sequence of N digits length on said high-speed lines by scrambling each of said L tributary signals with a different equivalent pseudo random sequence of N digits length, wherein L and N are relatively prime.

11. The system of claim 10 wherein L is 16 and wherein said equivalent pseudo random sequences are the same as said desired sequence except for the starting points thereof, and wherein N=31 and said sequences are derived from the primitive polynomial; h(x)=x⁵+x²+1, and wherein the starting points n₁...n₁₆ of the 16 equivalent sequences are in numerical order of said tributary signals: 28, 30, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, and 27.

12. The system of claim 10 wherein said L tributary signals are all of the same pseudo random sequence with different starting points, and wherein said starting points of any of said tributary signals is Δ digits greater than that of the next preceding tributary signal, wherein Δ is determined from the relationship,

1-(Δ L)_N= 0.

1 3 . A programmable pseudo random generator comprising a feedback shift register of m stages with feedback through modulo-2 adders arranged in accordance with the terms of a primitive polynomial, and means connected to each of said register stages to program the initial states of said stages, whereby said generator will produce 2^m-1 different pseudo random sequences depending on said initial states.

14. A frame-synchronous digital communication system comprising one or more multiplexers with L tributary signals connected thereto and one or more demultiplexers, said multiplexers and demultiplexers connected with high-speed lines, and means connected to said multiplexers to produce a desired pseudo random sequence of N digits length on said high-speed lines by scrambling each of said L tributary signals with the same pseudo random sequence also of N digits length, but wherein each of said same pseudo random sequences has a different starting point or phase, L and N being relatively prime.