WO1988002956A2

WO1988002956A2 - Frequency synthesiser

Info

Publication number: WO1988002956A2
Application number: PCT/GB1987/000727
Authority: WO
Inventors: Mark Stephen John Mudd; Peter Henry Saul
Original assignee: Plessey Overseas Limited
Priority date: 1986-10-20
Filing date: 1987-10-16
Publication date: 1988-04-21
Also published as: GB2196455A; GB8625091D0; WO1988002956A3

Abstract

A frequency synthesiser and a method of synthesising frequencies in which a chosen binary word is repetitively input to a binary accumulator and the carry-out signal of the most significant of the adders of the accumulator forms the synthesised frequency waveform.

Description

FREQUENCY SYNTHESISER

This invention relates to direct frequency synthesisers suitable for use in radio receivers and transmitters. The class of "Direct Digital Synthesisers" has been known for some years, although practical devices have been limited to low frequencies; indeed, until recently, the primary use of this class of synthesisers was for the generation of L.F. (low frequency) and V.L.F. (very low frequency) sinewaves. The known synthesiser, which may be integrated onto one or more I.C.s consists of an adder, with latches for delay equalisation, a ROM in which the coordinates of a sine wave are stored, retiming latches and a digital-to-analogue converter. In use, a digital word corresponding to the required frequency is applied to the adder, which addresses the ROM, thus generating a sinewave in digital form, to be constructed in analogue form by the DAC. This system can work very well, and a recently constructed chip of this type is capable of up to 100MHz output with a 327 MHz clock.

Shortcomings of the known frequency synthesiser are the relatively low available output frequency, the chip complexity, power consumption and, at least in radio systems, the output which although nominally a sinewave, varies from this form. In many radio applications the output waveform is converted to a square wave before use in a mixer circuit.

It is an object of the present invention, therefore, to provide an improved frequency synthesiser wherein the short comings of direct digital synthesisers, known heretobefore, are overcome.

According to the present invention, there is provided a method of synthesising a square wave of a particular frequency comprising the steps of inputting to an n-bit binary accumulator, repetitively at a predetermined substantially constant clock frequency, a binary word of value less than 2ⁿ, the binary word being selected such that its ratio to 2ⁿ is equal to the ratio; of the particular frequency to the clock frequency, and taking the MSB carry-out signal of the accumulator as the square wave.

The invention also provides a frequency synthesiser for synthesising a square wave of a particular frequency, comprising clock means for producing clock pulses at a substantially constant predetermined frequency, an n-bit accumulator including n full adders each arranged to receive a respective bit input of a binary word and each having its carry-out connected to the carry-in of the next more significant of the adders, input means for inputting, repetitively at the clock frequency, a binary word to the accumulator adders, and output means for receiving the carry-out signal of the most significant of the adders for delivering the square wave of the particular frequency. The synthesiser of the invention does not have a phase or frequency locked loop, but employs, for its operation, a high frequency, stable clock oscillator source (which may be separately provided) and uses digital techniques to produce from this source any arbitrarily chosen frequency, limited only by the channel spacing and the clock frequency chosen. Because no loop is used, the synthesiser is able to change frequency at a rate limited only by the clock oscillator.

The present invention will now be described, by way of example, with reference to the accompanying drawings in which:

Figure 1 is a schematic block diagram of a frequency synthesiser in accordance with the present invention;

Figure 2 illustrates some simplified waveforms in the device shown in figure 1 under conditions of relatively low output frequency; and

Figure 3 is a schematic block diagram of a further embodiment of a frequency synthesiser in accordance with the present invention.

Referring to figure 1, a frequency synthesiser comprises an accumulator 10 with latches 12 for increasing the speed of operation, a D-type divider 14 and an output buffer 16. Compared to a conventional direct synthesiser, there are fewer latch stages, no RDM and no DAC The complexity and therefore power consumption is reduced to less than one quarter of an equivalent sinewave system, and an improvement in operating speed, for given power levels, is possible as there is no ROM or DAC.

In more detail, the accumulator 10 comprises a plurality n of full adders 18 having inputs 20 whereto a binary word may be repetitively applied at the frequency of a clock (not shown). The clock produces pulses at a substantially constant frequency and this frequency determines the maximum synthesised frequency of the synthesiser.

Each adder 18 has a D-type flip-flop 22 for storing the sum of the inputs, and the carry-out of each adder 18 is connected to the carry-in of the next more significant adder 18 through a respective one of the latches 12, each constituted by a D-type master slave flip-flop. In this way, carry signals are retimed and no delay is occasioned by ripple.

The carry-out output of the most significant of the adders 18 is fed to the D-type divide-by-two divider 14 and then to the output buffer 16.

The chosen binary word, which may have any value less than 2ⁿ is generated in a controllable counter so as to be changeable, as desired. In operation, the binary word is chosen in dependence upon the particular frequency to be synthesised and is applied to the inputs 20. This word is, very conveniently, equal to the "channel number" i.e. the particular output frequency expressed as a multiple of the channel frequency spacing. Channel spacing itself is determined by the clock frequency divided by the length of the adder (2^N bits in the example shown), i.e. channel frequency spacing = clock frequency /2ⁿ and; channel frequency spacing x word = particular output frequency, and therefore, particular output frequency/clock frequency = binary word /2ⁿ. Practical systems may derive the chosen binary word serially possibly with provision for decimal input. Very fast frequency changes ("hopping") is more easily achieved if the chosen word is derived in a parallel manner.

The adder continuously sums the bits of the input word and the outputs of the latches (flip flops 22 and 12). The latches (flip flops 12) between adder stages provide retiming, i.e. "pipelining" of the carry-out signals of the adders 18 through the adder chain, so that the result of the addition is available at the full clock rate.

Figure 2 shows some simplified waveforms in the device under conditions of relatively low output frequency. The upper graph is not actually present anywhere in the all-digital circuit: it is an analogue representation of the number in the adder, and shows it accumulating and then overflowing. The second graph is the overflow waveform i.e. the carry-out signal of the most significant adder 18. In the general case, the mark space ratio will not be symmetrical. The D-type divide-by-two divider 14 restores approximate symmetry, reducing the spurious output level by an averaging process. The carry-out from the top (most significant adder 18) of the accumulator is, in the general case, an irregular rectangular wave of mark-space ratio dependent on the exact frequency. This is regularised to some extent by the D-type divider 14, although the exact point of the zero crossings will be channel number dependent. Spectrally, this effect will show as spurious outputs in the spectrum which will vary with the particular frequency. The output buffer 16 provides an interface to a circuit in which the synthesiser is used.

A further embodiment of a frequency synthesiser according to the invention, is shown in Figure 3. This embodiment may be used in frequency hopping radios. In the arrangement described with reference to Figure 1, when the input word is changed to change the particular frequency, the output frequency changes over a number of clock periods determined by the frequency difference up to a maximum of N clock cycles. Each of the inputs 20 to the accumulator 10 of Figure 3 has a number of serially connected D-type flip-flops 24. The number of flip-flops 24 is equal to the bit position. Thus the LSB input has one flip-flop 24: the next input has two flip-flops and so on. Each bit is thus delayed a number of clock pulses equal to the number of flip flops 24 in its input 20. In the embodiment of Figure 3, the particular frequency will remain at its first value for N clock periods, and then change on the Nth clock pulse instantaneously to the new particular frequency. The choice of the embodiment (Figure 1 or Figure 3) to use will depend on the application.

The concept as described is entirely process independent, but it is obvious that a faster circuit operation will lead to a faster output, and since speed is the limiting parameter in present systems, it would be advantageous to use a fast process. A single chip solution could easily be achieved on modern silicon bipolar processes, some of which are capable of clock rates of over 1GHz.

Practical limitations of the synthesiser primarily arise from variation in the particular frequency generated. This occurs whenever 2ⁿ is not an integral multiple of the chosen binary word. The acceptable level of spurs is dependent on the use to which the synthesiser is put. It may be improved by filtering, but this may be undesirable in some systems. The best outputs will be found when, the clock frequency is much higher than the particular frequency i.e. when there are many clock pulses per cycle of the output waveform. This is because the carry-out changes will then occur with a more constant mark/space ratio and timing jitter at the D-type flip-flop 14 input will be minimised. Higher particular frequencies will suffer greater degrees of spurious output level, but even outputs at one third of the clock frequency wiil be acceptable in some cases; experiments have shown non-harmonically related spurious levels to be at least 20db below the carrier.

The invention is not confined to the precise details of the foregoing examples and variation may be made thereto. For instance, if the binary word input to the accumulator 10 has a zero for its most significant bit or a plurality of zeros for its more significant bits then the carry-out signal of the next most, significant of the adders 18 provides an output at twice the particular frequency, and the output of the next lower adder 18 provides an output at four times the particular frequency and these outputs can be used instead of or in addition to the most significant adder 18 carry-out signal to synthesise additional frequencies.

Claims

1. A method of synthesising a square wave of a particular frequency comprising the steps of inputting to an n-bit binary accumulator, repetitively at a predetermined substantially constant clock frequency, a binary word of value less than 2ⁿ, the binary word being selected such that its ratio to 2ⁿ is equal to the ratio of the particular frequency to the clock frequency, and taking the MSB carry-out signal of the accumulator as the square wave.

2. A method as claimed in claim 1 in which the binary accumulator comprises n full adders, each connected to receive a respective bit of the binary word and each having a carry-out connected to the carry-in of the next more significant adder, and further comprising the step of retiming each of the carry-out signals to avoid ripple-induced delay.

3. A method as claimed in claim 1 or 2 comprising the step of dividing the signal from the MSB carry-out and buffering it to produce a square wave output.

4. A method as claimed in claim 1, 2 or 3 comprising the steps of generating the binary word in a counter and controlling the counter so as to be able to change the chosen binary word and thereby the particular frequency.

5. A method as claimed in any preceding claim wherein each bit of the binary word is fed to its respective accumulator input simultaneously and wherein, on changing from one binary word to a new binary, the particular frequency changes gradually to the new particular frequency.

6. A method as claimed in any preceding claim wherein each bit of the binary word is fed to its respective accumulator input after a delay of a number of clock pulses equal to the bit position so that, upon changing from one binary word to a new binary word, the frequency changes from the particular frequency to the new particular frequency in one step .

7. A method as claimed in any preceding claim wherein the binary word is of value less than 2^(n-1) and a square wave of twice the particular frequency is available at the carry-out of the (n-1) bit of the accumulator.

8. A method of synthesising a square wave of a particular frequency, substantially as hereinbefore described.

9. A frequency synthesiser for synthesising a square wave of a particular frequency, comprising clock means for producing clock pulses at a substantially constant predetermined frequency, an n-bit accumulator including n full adders each arranged to receive a respective bit input of a binary word and each having its carry-out connected to the carry-in of the next more significant of the adders, input means for inputting, repetitively at the clock frequency, a binary word to the accumulator adders, and output means for receiving the carry-out signal of the most significant of the adders for delivering the square wave of the particular frequency.

10. A synthesiser as claimed in claim 9 wherein the input means comprises a counter controllable to select the binary word for inputting to the accumulator.

11. A synthesiser as claimed in claim 9 or 10 wherein the carry-out of each adder is connected to the carry-in of the next more significant of the adders through a D-type master slave flip-flop to retime the carry signals.

12. A synthesiser as claimed in claims 9, 10 and 11 wherein the output means includes a divide-by-two divider and a buffer.

13. A synthesiser as claimed in any of claims 9 to 12 wherein the input means includes for each adder, a number of D-type flip-flops equal to the bit position to retime the input bit to that adder.

14. A synthesiser as claimed in any of claims 9 to 13 wherein the output means includes a supplementary output from the carry out of one of the less significant adders to provide a square wave output of frequency equal to a multiple of the particular frequency, when the input to that adder and all more significant of the adders due to the binary word in zero.

15. A frequency synthesiser, for synthesising a square wave of a particular frequency, substantially as hereinbefore described with reference to and as illustrated in Figure 1 or Figure 2 of the accompanying drawings.