WO1988002123A1 - Circuits integres - Google Patents

Circuits integres Download PDF

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Publication number
WO1988002123A1
WO1988002123A1 PCT/GB1986/000547 GB8600547W WO8802123A1 WO 1988002123 A1 WO1988002123 A1 WO 1988002123A1 GB 8600547 W GB8600547 W GB 8600547W WO 8802123 A1 WO8802123 A1 WO 8802123A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
circuit
monitor
indication
pattern
Prior art date
Application number
PCT/GB1986/000547
Other languages
English (en)
Inventor
Michael Geoffrey Pitt
Daniel Vincent Mccaughan
Original Assignee
The General Electric Company, P.L.C.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB08514621A priority Critical patent/GB2176352B/en
Application filed by The General Electric Company, P.L.C. filed Critical The General Electric Company, P.L.C.
Priority to JP61504865A priority patent/JPH01500785A/ja
Priority to EP19860905368 priority patent/EP0281552A1/fr
Priority to PCT/GB1986/000547 priority patent/WO1988002123A1/fr
Publication of WO1988002123A1 publication Critical patent/WO1988002123A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324—Display of status information
    • G06F11/327—Alarm or error message display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches

Definitions

  • This invention relates to integrated circuits.
  • large scale integrated circuits reduce the margins for in- service variations of the parameters of the individual components within the circuits, before failure of the circuit.
  • Such failures may occur, for example due to electromigration in conductive tracks within the circuits causing open or short circuits of the tracks this occurring when excessive current passes through a conductive track.
  • Small changes in cross-sectional areas of the tracks may also drastically reduce the time to failure of the circuit.
  • Another example of a possible variation leading to failure of the circuit is that of threshold voltage instabilities, for example MOS devices within the circuit due to ion diffusion in the gate oxide, hot carrier trapping, or the effects of ionising radiation. Whilst in systems made up of a large number of smaller integrated circuits, the smaller integrated circuits can be easily tested and replaced, this is more difficult in systems made up of one or more large scale integrated circuits.
  • an object of the present invention to provide an integrated circuit wherein this problem is alleviated.
  • an integrated circuit including a monitor circuit designed to fail prior to the rest of the integrated circuit whilst allowing the rest of the integrated circuit to function, and means for providing an indication of when the monitor circuit has failed.
  • the monitor circuit includes a conductive pattern and means for providing current through the pattern such that the current density through the pattern is greater than for the rest of the integrated circuit.
  • a monitor circuit finds application monitoring possible failures of conductive portions within the integrated circuit due to electromigration.
  • the means for providing an indication provides the indication when an open circuit has occurred in the pattern.
  • the means for providing an indication provides the indicat ⁇ ion when a short circuit has occurred between the pattern and an adjacent conductor.
  • the monitor circuit comprises a field effect device, means for electrically stressing the device, and means for comparing the threshold voltage of the device to a reference voltage.
  • Such a monitor circuit finds application in monitoring possible variations of threshold voltages in field effect devices.
  • Figure 1 is a schematic diagram of a monitor circuit incorporated in the first integrated circuit
  • Figure 2 is a schematic diagram of a monitor circuit incorporated in the second integrated circuit with the monitor circuit's switches in a first configuration
  • Figure 3 shows the monitor circuit of Figure 2 with its switches in a second configuration.
  • the monitor circuit incorporated in the first integrated circuit to be described is designed to monitor possible failure of metallic tracks within the integrated circuit due to electromigration.
  • the monitor circuit comprises a metallic test pattern in the form of a stripe indicated as 1 connected in series with a resistor 3 across two supply rails 5, 7.
  • the test pattern is formed on the integrated circuit at the same time as the other conductive tracks within the circuit such that variations in track thickness due to processing variations will be reflected in the stripe 1.
  • the value of the resistor 3 is chosen such that in operation of the integrated circuit incorporating the monitor circuit, the current density through the stripe 1 is greater than the value usually regarded as a maximum rating for a metallisation pattern within the integrated circuit.
  • a U- shaped conductive track 9 Spaced from the stripe 1 by a distance equivalent to the minimum recommended line spacing in the integrated circuit.
  • the track 9 is connected to the supply rail 7 by a resistor 11 having a somewhat greater value of resistance than that of the resistor 3.
  • the voltages V1 of a point between the stripe 1 and resitor 3, and V2 of a point on the conductive track 5 each measured with respect to earth are continuously monitored.
  • the resistance of the stripe will be much less than the resistance of the resistor 3
  • the voltage V1 will remain close to that of the rail 5 until an open circuit in the stripe 1 , due to for example -H- electromigration, occurs, in which case the voltage V1 will become close to that of the rail 7.
  • a warning circuit (not shown) will normally be either connected to or incorporated in the integrated circuit which is responsive to the voltage V1 to provide a warning when the monitored voltage V1 indicates that an open circuit has occurred In the stripe 1 , this then providing an early warning that the integrated circuit is likely to fail before the integrated circuit actually fails which may, in some circumstances be catastrophic. Appropriate action can then be taken such as total removal of the integrated circuit from the system in which it is incorporated where high reliability is required.
  • the warning circuit will also be responsive to the voltage V2 which normally will be zero, but will approach the value of the voltage on the rail 5 in the event that electromigration causes the stripe 1 to become electrically connected to the track 9. It will be appreciated that the test pattern may take many forms in order to simulate possible failure modes, e.g. it may include steps over under ⁇ lying polysilicon lines, or border contact holes.
  • a monitoring circuit designed to be responsive to possible failure through elctromigration of metallic tracks need, in some circumstances, .be only responsive to open circuits or short circuits in the test stripe.
  • the second integrated circuit to be described includes a monitor circuit designed to monitor possible threshold voltage instabilities in MOS transistors within the integrated circuit.
  • a monitor transistor 21 is connected as shown in this figure across two supply rails 23, 25, the gate of the transistor 21 being connected to the rail 23 via a moveable contact and a fixed contact of a two position switch 27, and the drain of the transistor being connected to the rail 23 via a biassing resistor 29, with the other fixed contact of the switch 27 being connected to a point 30 between the drain and the resistor 29.
  • a series arrangement of two similarly valued resistors 31, 33 are also connected across the rails 23, 25.
  • a fixed contact of a second two way switch 35 is connected to a point between the junction of the two resistors 31, 33, the moveable contact of the switch being connected to one electrode of a capacitor 37, the other fixed contact of the switch 35 being connected to the point 30 between the drain of the transistor 21 and the resistor 29.
  • the second electrode of the capacitor 37 is connected to the gate electrodes of one n channel 39 and one p channel 41 MOS transistors, the drain of the n channel transistor 39, being connected to the rail 25, the source of the p channel transistor 41 being connected to the rail 23, and the remaining source and drain being connected together.
  • the second electrode of the capacitor is also connected via a switch 43, shown closed in Figure 2 to the conductor connecting the source of the transistor 39 and the drain of the transistor 41, the voltage V3 being monitored at this point.
  • the switches 27, 35 and 43 all consist of transmission gate circuits clocked synchronously.
  • the switches are set in the positions shown in Figure 2.
  • the gate of the monitor transistor 21 is thus directly connected to the rail 23 so as to provide a maximum gate bias.
  • the output voltage V3 will be approximately half the potential difference across the rails 23, 25 i.e. V RE as indicated in the figure, the capacitor 37 charging up to this voltage.
  • the gate of the monitor transistor 21 is connected to the drain which will settle to around the threshold voltage V ⁇ 0 f the transistor, assuming the resistor 29 is of sufficiently high value.
  • the voltage applied to the capacitor 37 will thus increase by V_--V_, p _- as switch 35 is switched to the position shown in Figure 3, and switch 43 is opened.
  • V- is greater than V-.-.-. then only transistor 41 will be conductive, and the voltage V3 will be that of the line 25. If however V-_ is less than V-.-,-., then only transistor 39 will be conductive, and the voltage V3 will be that of the line 23.
  • a warning circuit (not shown) may then use the value of V3 to give a warning signal if the threshold voltage V ⁇ is less than -,_---. It will be appreciated that the value of
  • monitoring circuits described herebefore by way of example monitor possible failures due to electro- migration, or variation of threshold voltages
  • integrated circuits in accordance with the invention incorporating monitoring circuits in accordance with the invention incorporating monitoring circuits for monitoring many other variations in parameters likely to lead to circuit failure are also possible.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Un circuit intégré comprend un circuit moniteur (1, 3) destiné à défaillir avant le reste du circuit intégré, tout en permettant au reste du circuit intégré de continuer à fonctionner. Un circuit d'avertissement indique quand le circuit moniteur (1, 3) tombe en panne.
PCT/GB1986/000547 1985-06-10 1986-09-17 Circuits integres WO1988002123A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB08514621A GB2176352B (en) 1985-06-10 1985-06-10 Integrated circuits
JP61504865A JPH01500785A (ja) 1986-09-17 1986-09-17 集積回路
EP19860905368 EP0281552A1 (fr) 1986-09-17 1986-09-17 Circuits integres
PCT/GB1986/000547 WO1988002123A1 (fr) 1986-09-17 1986-09-17 Circuits integres

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/GB1986/000547 WO1988002123A1 (fr) 1986-09-17 1986-09-17 Circuits integres

Publications (1)

Publication Number Publication Date
WO1988002123A1 true WO1988002123A1 (fr) 1988-03-24

Family

ID=10591172

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1986/000547 WO1988002123A1 (fr) 1985-06-10 1986-09-17 Circuits integres

Country Status (3)

Country Link
EP (1) EP0281552A1 (fr)
JP (1) JPH01500785A (fr)
WO (1) WO1988002123A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2160829A1 (fr) * 1971-11-24 1973-07-06 Ibm
EP0017808A1 (fr) * 1979-04-06 1980-10-29 General Instrument Corporation Procédé comportant l'essai d'un circuit de mémoire microélectronique electriquement alterable
EP0073721A2 (fr) * 1981-08-28 1983-03-09 Fujitsu Limited Dispositif à semi-conducteur intégré à grand échelle comprenant un détecteur de défauts et son procédé de fabrication
US4528505A (en) * 1983-03-29 1985-07-09 Motorola, Inc. On chip voltage monitor and method for using same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2160829A1 (fr) * 1971-11-24 1973-07-06 Ibm
EP0017808A1 (fr) * 1979-04-06 1980-10-29 General Instrument Corporation Procédé comportant l'essai d'un circuit de mémoire microélectronique electriquement alterable
EP0073721A2 (fr) * 1981-08-28 1983-03-09 Fujitsu Limited Dispositif à semi-conducteur intégré à grand échelle comprenant un détecteur de défauts et son procédé de fabrication
US4528505A (en) * 1983-03-29 1985-07-09 Motorola, Inc. On chip voltage monitor and method for using same

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Volume 17, No. 9, February 1975, (New York, US), A.K. GHATALIA et al.: "Semi-Conductor Process Defect Monitor", pages 2577-2588, see the whole document *
IBM Technical Disclosure Bulletin, Volume 19, No. 1, June 1976, (New York, US), D.A. JEANNOTTE: "Circuit Device Testing by on-side Model", pages 192-193, see the whole document *
IBM Technical Disclosure Bulletin, Volume 22, No. 6, November 1979, (New York, US), J.B. VOGE: "Detection of Shorting Defects by Resistance Measurement", pages 2448-2449, see the whole document *
IBM Technical Disclosure Bulletin, Volume 26, No. 4, September 1983, (New York, US), C.M.H. SIEH et al.: "Metal Electromigration Sensor", pages 1998-1999, see the whole document *
IEEE Journal of Solid State Circuits, Volume SC-19, February 1984, (New York, US) K.P. RODBELL et al.: "A new Method for Detecting Electromigration Failure in VLSI Metallisation", pages 98-99, see the whole document *
Proceedings of the IEEE, Volume 62, No. 2, February 1974 (New York, US), E.D. COLBOURNE et al. "Reliability of MOS LSI Circuits", pages 244-259, see page 246, column 2, paragraph 4 - page 249, column 1, paragraph 3; figures 2-5 *

Also Published As

Publication number Publication date
EP0281552A1 (fr) 1988-09-14
JPH01500785A (ja) 1989-03-16

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