WO1988001426A1

WO1988001426A1 - Integrated semiconductor memory and integrated signal processor having such a memory

Info

Publication number: WO1988001426A1
Application number: PCT/NL1986/000024
Authority: WO
Inventors: Jozef Louis Van Meerbergen; Wilhelmus Christianus Hyacintus Gubbels
Original assignee: N.V. Philips' Gloeilampenfabrieken
Priority date: 1986-08-11
Filing date: 1986-08-11
Publication date: 1988-02-25
Also published as: DE3683056D1; EP0282475B1; EP0282475A1; US5121355A; JPH0823996B2; JPH01500468A

Abstract

Increasing the storage capacity of high-performance (signal) processors while maintaining the original RAM cell necessitates modification of the entire lay-out of the circuit. The invention relates to the once-only design of peripheral circuitry which provides control of blocks of 4 Full CMOS RAM cells (easy to process) or 9 double-layer polysilicon cells (more difficult to process, but having smaller dimensions). It is defined in the RAM peripheral circuitry whether all 9 cells can be accessed (memory capacity from 2**n to 2**(n+1) + 2**(n-2)) or 8 cells can be accessed (memory capacity from 2*n to 2**(n+1)).

Description

Integrated semiconductor memory and integrated signal pro¬ cessor having such a memory.

The invention relates to an integrated semicon¬ ductor memory, comprising memory cells which are arranged in a matrix and peripheral circuits for addressing memory cells at least in order to read data from the addressed ■ memory cells. The invention also relates to an integrated signal processor having such a memory.

Within the family concept of an integrated pro¬ duct, preferably product versions having different storage capacities are made available. An increased storage capa-¹ city of an integrated memory implies an increased number of memory cells and an increased addressing capacity of the address decoding circuits in the periphery. In that case the surface area of the substrate increases substant¬ ially linearly; this usually has far-reaching consequences because it necessitates¹ redesigning. ' '

Expansion of the storage capacity has far- reaching consequences notably when the memory is integrated' on a substrate together with a signal processor. Not only the memory, but also the parts of the processor which are arranged around the memory will be "shifted", so that a completely new lay-out must be made for the integrated pro¬ cessor and the associated memory. Redesigning an integrated product is expensive so that redesigning of a signal pro¬ cessor, necessitated by the expansion of the storage capa- city of the memory integrated on the same substrate, is found to be very disadvantageous.

It is the object of the invention to provide an integrated semiconductor memory and an integrated signal processor having such a memory where, when the storage capa- city is to be increased, the memory is integrated within the already existing limits for the lay-out of the memory.

A memory in accordance with the invention is cha- characterized in that the number of addressable memory cells deviates substantially from a number of memory cells to be potentially addressed by the peripheral circuits.

The invention will be described in detail herein¬ after with reference to the drawing; therein:

Fig. 1 shows a lay-out of a signal processor.

Figs. 2A and B show two different types of static memory cells, . '

Fig. 3 shows diagrammatically a set-up of a me¬ mory in accordance with the invention.

Fig. 4 shows a part of the circuit of the memory.

Fig. 5 shows a part of the address decoding cir¬ cuit for the memory in accordance with the invention,

Figs. 6A and B show a memory section with a low cell density and a high,cell density, respectively, and

Fig. 7 shows a truth table for the addressing of the memory sections shown in the figures 6A and 6B.

Fig. 1 shows a lay-out of a signal processor 1_ which includes an input register 3, an arithmetic and logic unit 5 with accumulators and multipliers', an.output register

1 _t a read-only memory 9, a read/write memory .11 , and a timer unit 13. Should more storage capacity be required for a given application of the processor 1 , so that the read/ write memory 11.would occupy a larger surface area, it would be necessary to reconsider or redesign the entire set¬ up of the processor 1.

By utilizing types of memory cells which differ as regards size and by making the decoder circuits suitably for the highest storage capacity (i.e. the memory matrix is then filled with, the smallest (as regards surface area) memory cells) , the processor can be constructed so as to have different storage capacities, without necessitating a modification of lay-out of the integrated processor. This will be illustrated hereinafter with reference to the figures.

Fig. 2A shows a known six-transistor memory cell 2A which includes a CMOS-transistor flipflop which is con- nected between the power supply terminals V and V and which- comprises two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2, which cell also includes two NMOS access transistors N3 and N4. The outputs Q and Q of the flipflop are connected to the bit line BL and to the integrated bit line BL, respectively, when the access tran¬ sistors N3 and N4 receive an appropriate control signal via the word line WL. The dimensions of a memory cell 2A of this

2 kind are, for example 40.5 x 40.75,um .

Fig. 2B shows a known four-transistormemory cell 2B. The parts which correspond to those of the memory cell 2A are denoted by .corresponding reference numerals. Instead of two large PMOS transistors (P1 and P2, fig. 2A) , the flipflop of the memory cell 2B utilizes polysilicon re¬ sistors R1 and R2 , which require a more difficult techno¬ logy but which result in a memory cell 2B whose surface area

2 amounts to 25.5 x 25.5 ,um . The polysilicon resistors R1 and r2 could alternatively be omitted, thus simplifying the technology to be used for the manufacture of the cell and resulting in a quasi-static memory cell. The surface areas of the CMOS memory cell 2A and the memory cell. 2B relate approximately as 2 : 1. However, the both types of cell are substantially square and the ratio of the lengths (and the widths)of the cells _2A_ and 2B is 3 : 2. Instead of a group of 2 x 2 CMOS transistor memory cells, a group of 3 x 3- memory cells with polysilicon resistors R1 and R2 can be arranged on the same substrate surface area, so that the storage capacity is more than doubled. Doubling the storage capacity means that the addressing will require an address whose bit length has been increased by a single bit.

Fig. 3 diagrammatically shows a set-up of a me¬ mory 3_p_ in accordance with the invention which includes two matrices 31A and 31B of memory cells which are arranged in rows and columns. Memory cells are addressed by means of the address signals DP, Y_Q, X_Q, X.. , X₂, 3 , ₄ and Xr. When use is made of CMOS transistor memory cells, the address signal DP can actually be dispensed with as will be explained hereinafter. The address signals X₂, 3, ^ and _c are applied to an X-preselection circuit 33A wherefrom 8 selection signals are derived which are applied, via a connection 35 having a width of 8 bits, to an X-selection circuit 37. The address signals DP, XO and X1 are applied to an X/Y preselection circuit 33B which generates three X-preselection signals and three Y-preselection signals which are applied to an X-postdecoding circuit 3_9 and an Y-selection circuit _41_, respectively, the latter circuit also receiving -the- address signal Y_Q. Outputs of the X- selection circuit 3_7 are connected to further inputs of the X-postdecoding circuit 39, so that the word line drivers in both word line driver circuits 43A and 43B can be con¬ trolled by the combination of the three preselection sig¬ nals, via an output of the X-postdecoding circuit 3_9. Each word line driver in the circuits 43A and 43B controls a word line of the memory cell matrices 31A and_s31B, res¬ pectively. The Y-selection circuit 41 controls two multi¬ plex circuits 45A and 45B whereby each time 8 columns of me¬ mory cells are simultaneously selected in each matrix 31A and 31B. The eight selected columns of memory cells in the matrices 31 and 31B are connected, via the multiplexer circuits 45A and 45B, to a corresponding number of read and write circuits in the input and output circuits 47A and 47B which are controlled by the signals RWN and øprech which will be described hereinafter. The signal prech is also applied to the precharge/hold circuits 49A and 49B whereby the bit line BL and the inverted bit line BL are charged for each read or write operation.

Fig. 4 shows a detail of fig. 3: a precharge/ hold circuit 49 of, for example the circuit 49A, a memory cell 51 of the matrix 31A, a part 4_5 of the multiplex cir¬ cuit 45A, and a read and write circuit 47 of the circuit 7A. The memory 3_0 operates in synchronism with a precharge/ sample clock pulse. When the signal øprech is "high", the bit line BL and the inverted bit line BL are charged to the same potential; the NMOS transistors 52, 53 and 54 are turn- ed on. Furthermore, the read amplifier 55 is switched off, because the inverted signal øprech is applied to the gate of the transistor 56. The write circuit _5_7 is also inactive, because the signal HIZ, derived from the signals øprech and RWN, turns off the transistors 58, 59, 61 and 62. The bus lines BUS and BUS are charged to ^V _DD~^V _TN ^{via the} NMOS transistors 63 and 64 which are controlled by the sig¬ nal øprech. The bus lines BUS and BUS connect outputs of the multiplex circuits 45A and 45B to inputs of the output ™ circuits 47A and 47B, respectively.

During the "high" state of the signal øprech, the address applied to the inputs DP, YO, XO to X5 is also decoded as far as the X-postdecoding circuit 3_9_. After termination of the signal prech ( prech becomes "low") , the memory 3_0 enters the sample mode. Via the X postdecoding circuit 3_9_, a word line is activated so as to connect the cells connected to the word line to the bit lines BL and BL. The cross-coupled PMOS transistors 66- and 67, connected to the power supply source V via an NMOS transistor 65, ensure that the data from the memory cell 51 remains stable on the bit lines BL and BL. The bit lines BL and BL are connected to the bus lines BUS and BUS via two transistors 68 and 69 of the multiplex circuit 45.

Via the bus lines BUS and BUS, the data from the cell 51 reaches the gates of the PMOS transistors 81 , 84 and the PMOS transistors 82, 83, respectively, as well as the gates of the NMOS transistors 88 and 87, respectively. The read amplifier J5_5_ also includes two cross-coupled PMOS tran¬ sistors 85 and 86, of which the junctions of the gates and main electrodes respectively are connected to one of the connections between the transistors 83 and 87 and between the transistors 84 and 88, respectively and form the output OUT and the inverted output OUT for the data.

When new data is to be written into the memory cell 51, the signal HIZ is rendered "high", so that the data on the input DATA IN is applied to the bus lines BUS and BUS via the four transistors 71, 72 and 73, 74 which form two push-pull amplifiers. Fig. 5 shows a detail of the preselection cir¬ cuits 33A and 33B, of the X-selection circuit 3_7, of the X postdecoding circuit 3_9_, and of the Y-selection circuit 41. The preselection circuit 33A includes eight 2-input NOR-gates 33AN and eight inverters 33AI. The four feasible combinations of the address signals X2, X2, X3 and X3 are applied to four of the NOR-gates 33 N, the other four NOR- gates 33 N receiving the four feasible combinations of the address signals X4 , x , X5 and X5~, the eight NOR output signals being^'applied, via an inverter 33 I, to 2-input

NOR gates 37N of the X-selection circuit 3_. The outputs of the inverters 33AI are applied to the 16 NOR-gates .37N so that each logic combination of X2, X , X3 and X3 is com¬ bined with each logic combination of X4, X4, X5 and X5. Each output of the NOR-gates 37N is connected to an input of three NAND-gates 39E (only one has been shown) of the X-postdecoding circuit 39, each of said NAND- gates receiving the inverted signal øprech on a second .input. The output of each NAND-gate 39.E is connected to an input . of a word line driver 43D. A third input of the three NAND- gates 39E receives either X-preselection signal XPO or XP1 or XP2. The Figure shows only one NAND-gate 39E which re¬ ceives the preselection signal XP1. The Y-selection circuit 41 includes six 2-inρut NAND-gates 49E, three of which re- ceive the address signal 40 and one of the Y-preselection signals YPO, YP1 , YP2. The other three NAND-gates receive the address signal YO and one of the Y-preselection signals YPO, YP1 , YP2.

The outputs of the NAND-gates 49E control, via inverters 491, the multiplex transistors (see figure 4, transistors 68 and 69) of the multiplex circuits 45A and 45B.

The described selection method aims to achieve the following: using the address signals X2, X3 , X4 and X5, a block of eight or eighteen memory cells is selected (see figs. 6A and 6B) , the address signals DP, XO, X1 and Y0 de¬ termining which cell of the relevant block is addressed. When the memory 3_0 (fig. 3) includes CMOS transistor memory cells, the block selected by means of the signals X2 to X5 will include eight cells and the address signal DP should always be "zero" in order to select a cell from the block by means of the remaining address signals XO, X1 and YO (see fig. 6A) . The cells in the block selected by means of the selection signal XSEL are numbered from 0 to 7. For the selection of cell 0, the signals XPO, YPO, and YO should be high (when the signal YO^* is high, the cell 1 is selected). For the selection of the cell 5, the signals XP2, YP2 and YO should be high. This procedure is illustrated by the table of fig. 7 in which the relationships between the address signals DP, XO, X1 and YO, the preselection sig¬ nals XPO, XP1 , YPO, YP1 and YP2 and the cells to be select¬ ed thereby are stated in the upper four lines. Because of the absence of any activity of the signals' P1 and YP1 , actually only two word line drivers 43DO and 43D2 need be present. The word line driver 43D1 is denoted by a broken line, because it will be integrated to the single lay-out to be made; however, it will not be connected. Furthermore, the multiplex circuit 4_5 neeed receive only four control signals (4-to-1 multiplexer) , so that the number of tran¬ sistors controlled by the combinations (YP1 , Y0) and (YP1 , YO) can actually be omitted in the present embodiment.

Fig. 6B shows the situation in which the memory 30 is composed of a matrix comprising smaller memory cells with polysilicon resistors (R1 , R2, see fig. 2B) . Using the signal "XSEL", ^"a block of 18 memory cells is selected; 16 memory cells thereof can be selected by means of the address signals DP, X0, X1 and YO via the three NAND-gates 39E which control the word line drivers 43DO, 43D1 and 43D2. The preselection signals YPO, YP1 and YP2 control, in conjunction with the address signal Y0, the six-to-one multiplex circuit 45 via the Y-selection circuit 41. It is to be noted that the cells denoted by the reference X can¬ not be addressed. The cells which can be addressed are numbered from 0 to 15. From the last two columns and the "high" (= 1) and the "low" (= 0) values of the address sig¬ nals DP, XO to X5 and YO in the table of fig. 7 it can be deduced in which situation the preselection signals XPO, XPl, XP2, YPO, YP1 , YP2 may be active for the selection of given cells. It can also be deduced from the table how the address signals DP, XO and X1 must be logically combined in order to form the desired preselection signals.

It is to be noted that the address signals XO, X1 and also the signal DP are used for the word line select- ion (row selection) • as well as the bit line selection (column selection) when the memory capacity is doubled.

The dummy cells which are denoted by the refer¬ ence X in each block, of course, can be addressed when a further address bit is used in addition to the address signal DP. However, only 1/8 of the addressing capacity of this additional address bit will then be used.

Claims

<L i $

1. An integrated semiconductor memory, comprising memory cells which are arranged in a matrix and peripheral circuits for addressing memory cells at least in order to read data from the addressed memory cells, characterized in that the number of .addressable memory cells deviates sub¬ stantially from a number of memory cells potentially addressable by the peripheral circuits.

2. An integrated semiconductor memory as claimed in Claim 1 , in which the memory cells are arranged in a number of rows and a number of columns, the peripheral circuits including row address decoding circuits and column address decoding circuits, characterized in that the number of addressable memory cells is smaller than the product of the number of column address decoding circuits and the number of row address decoding circuits.

3. An integrated semiconductor memory as claimed in Claim 2, characterized in that the number of outputs of the column decoding circuits is larger than the number of column driver circuits of the matrix.

4. An integrated semiconductor memory as claimed in Claim 2, characterized in that the number of outputs of the row decoding circuits is larger than the number of rows of the matrix.

5. An integrated semiconductor memory as claimed in Claim 3 or 4 , characterized in that the memory cells comprise PMOS transistors and NMOS transistors, three column de¬ coding outputs and three-row decoding outputs being present for every two columns and rows, respectively.

6. An integrated semiconductor memory as claimed in Claim 1 or 2, characterized in that the memory cells are sub¬ divided into groups of nine cells which are arranged in three adjacent rows and three adjacent columns, only eight cells thereof being addressable.

7. An integrated memory circuit as claimed in Claim 6, characterized in that the memory cell in the second row and the second column of each block is a dummy cell.

8. An integrated semiconductor memory, comprising memory cells which are arranged in a matrix and address decoding circuits and peripheral circuits for addressing memory cells at least in order to read data from the addressed memory cells, a first part of a multi-bit address being applied to column decoding circuits for the addressing of a memory cell whilst a second part of the address is applied to row decoding circuits, characterized in that a bit of the address is applied to the column decoding cir¬ cuits as well as to the row decoding circuits.

9. An integrated semiconductor circuit, comprising a memory as claimed in any one of the Claims 1 to 8.