WO1988000773A1 - Systeme d'amplificateur de basses frequences - Google Patents

Systeme d'amplificateur de basses frequences Download PDF

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Publication number
WO1988000773A1
WO1988000773A1 PCT/US1986/001517 US8601517W WO8800773A1 WO 1988000773 A1 WO1988000773 A1 WO 1988000773A1 US 8601517 W US8601517 W US 8601517W WO 8800773 A1 WO8800773 A1 WO 8800773A1
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WO
WIPO (PCT)
Prior art keywords
signal
supplied
audio
output
modulator
Prior art date
Application number
PCT/US1986/001517
Other languages
English (en)
Inventor
Robert Ponto
Original Assignee
Robert Ponto
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Ponto filed Critical Robert Ponto
Priority to PCT/US1986/001517 priority Critical patent/WO1988000773A1/fr
Priority to PCT/US1987/000680 priority patent/WO1988000774A1/fr
Publication of WO1988000773A1 publication Critical patent/WO1988000773A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices

Definitions

  • the present invention relates to signal amplification systems and power supply systems and more particularly to low signal distortion amplifiers and power supply systems particularly useful in connection with such amplifier systems, as well as other purposes.
  • MOSFET metal oxide silicon field effect transistors
  • the present invention provides new, useful, and particularly inexpensive, but effective, arrangements for power supply and audio amplifier systems.
  • the present invention provides audio systems which can accommodate change in loading of the .system yet maintain quality of response and avoid the adverse characteristics of various prior art arrangements under similar changes by providing a system which limits the power which can be supplied by the unit but is substantially
  • a power supply can be provided for use with audio sys ' tems of the present invention wihich is economical to fabricate and which utilizes dual transistor
  • the present invention provides a -_ power supply and audio amplifier system including an audio amplifier system adapted to receive an audio signal which is supplied to an attenuator which receive the signal and selectively attenuate the signal which is then supplied to a buffer and filter circuit to condition the signal.
  • 0 attenuated, filtered, signal is then supplied to a modulator where it is converted to a square wave signal having a pulse width a function of the level of the audio signal.
  • the square wave pulse signal is then supplied to push-pull converter to generate an alternating current signal which is supplied to the primary coil of a transformer an amplified output signal is supplied to a load from the secondary of the transformer.
  • the load characteristics are analyzed and a loading signal is supplied to an input clipper circuit which prevents the output from exceeding selected load limits.
  • a power supply system including a pulse signal generator to operate transistor devices to supply square wave current pulse through an inductive coil at a rate determined by a clock where such current is supplied as a square wave and where the square wave pulses drive first and second transformers which operate first and second switches to gate supply power to the primary coil of a transformer in push-pull relation in response to the pulsed output signal from the pulse signal generator arrangement to improve efficiency and reduce losses in the conversion.
  • Devices within the scope of the present invention further provide filter arrangements to allow wide variation in output loading without substantially affecting audio characteristics of an associated audio amplifier.
  • Figure 1 is a schematic illustration of an example of a power supply within the scope of the present invention
  • FIG. 2 is a flow illustration of an audio amplifier system also within the scope of the present invention.
  • FIG. 3A-3C present a more detailed schematic of the amplifier system shown in Figure 2 ,- and
  • Figure 4 is a graphic illustration of a signal generated in accordance with one feature of the present invention.
  • Figure 1 illustrates a power supply useful in devices within the scope of the present invention as well as other - applications.
  • a direct current voltage source VDC for example a 120 VAC rectified supply is provided across input terminals 41, 42.
  • a current sensing fuse 21 and a temperature sensitive fuse 22 are provided in terminals 41 and 42 along with a filtering capacitor Cll.
  • Terminals 41, 42 are connected through transistors Q41, Q42 gated by series transformer windings L2A, L2B so that as the transistors Q41, Q42 are gated current flows through the transistors to the primary coil Pi of a transformer Tl.
  • Windings L2A, L2B are operated directly in response to operation of pulse width modulator 40, for example part • number 3524 which supplies a pulsed output 43 to drive the base of transistors Q43, Q44 and supply current to winding 61 which is a primary coil for secondary coils L2A, L2B by means of core 44.
  • Pulsing current to coil Ll is supplied through a coupling capacitor C2 and transistors Q43, Q44 are provided to regulate the duty cycle of the primary coil Ll -
  • the resistor capacitor network R,-C provides a damping network while the capacitor C2 provides a current blocking angement.
  • Diodes D, D ⁇ are clamping diodes and capacitor C, provides bypass capacitor.
  • Clamping diodes D3, D4 are provided, as shown, across the base emitter B-E of transistors Q43, Q44 to allow internal transistors in modulator 40 to drive the rising edge of a pulse and Q43 and Q44 to drive the falling edge of the pulse which is inherently slow in a modulator at a relatively low switching rate to avoid the inefficiencies commonly encountered in the operation of similar prior art devices.
  • a control circuit 44 is provided which is unique in that it provides three things not available with a pulse c width modulator:
  • modulator 40 operates in a push-pull mode current flow is generated through the primary Pi of transformer Tl at the rate set by the pulse width modulator 40 which
  • 25 provides an inexpensive means of setting dead time between the on-off cycles of transistors 41, Q42 so that a square wave output of desired characteristics is generated through the primary Pi of transformer Tl as opposed to for example
  • the pulse width modulator 40 is driven in response to clock pulses provided by means of input 68 from a clock (described hereinafter) to an opto- coupler OP41 provided to isolate pulse width modulator 40 where the isolated clock pulses are provided at input 47 is a 5 voltage supply voltage.
  • the coil Pi is the primary frequency determing element of pulse width modulator 40, and the pulses from input 68 to modulator 40 syncronize.
  • the tap 49 from the primary Pi of transformer Tl provides current limiting input to modulator 40 where resistor R2 is low impedance current sensing resistor so the voltage generated across resistor R2 is reduced by the R3/R4 divider and supplied to pulse modulator 40 for current sensing and limiting.
  • a higher voltage output from the secondary SI is provided through a rectifier circuit RCTl as shown to terminals 51, 52 and is also supplied through a zener diode D6, which limits the overall voltage from the device by way of an opto isolator OP42 where the output 52 from collector of the transistor of isolator OP42 is connected to pulse with modulator 40 to control the output pulse width in response to the output voltage.
  • This control system is a standard way of regulating the power supply but designs within the scope of the present invention do not use it except for over voltage protection, not regulation. This is significant for two reasons:
  • the logic output of the and gate of isolator 0P41 is connected through lead 48 to capacitor C48 to the pulse width modulator 40 as previously described.
  • the output drives the modulator 40 to sychronize operation of modulator 40 with the clock input 68 from the clock system described hereinafter.
  • a resistor R48 is provided in the output 51 to act as a pullup while capacitor c48 is provided as a differentiating capacitor to generate samll spikes.
  • Figure 2 is a flow chart illustration of an example of an amplifier device within the scope of the present invention to provide a general understanding of one example of a device within the scope of the present invention.
  • FIG. 3A-3C A more detailed description of one example of a . device within the scope of the present invention is shown in Figures 3A-3C.
  • an audio signal AD is provided
  • Signal 69 is supplied to a digital attenuator 70 which attenuates the signal, for example, in a binary mode, that is IdB, 2dB, 4, 8, 16, 32. etc. up to 63dB in ldB
  • the attenuated output signal 79 is supplied to a buffer 80 which then supplies a buffered signal 89 to a high pass, low pass filter combination 90, (which can be a multiple order filter) to supply a filtered attenuated signal 99 of selected characteristics, - j e Signal 99 is supplied to modulator 100 which converts the alternating signal to a pulse width modulated signal M which is reflective of the characteristics of the output signal 226 from the device as described hereinafter.
  • the output M from modulator 100 is then supplied to a gating Q system 110 which generates a 4 phase output Ql, Q2, Q3, Q4, then to drivers 120, 121, 130, 131 to generate signals 129, 139 which is utilized to drive the primary coils P3, P4 of transformers T3 and T4 .
  • the secondary coils 53A, 53B, 54A, 54B are connected in a 4 phase mode operated at a rate 5 determined by the characteristics of output drivers 140, 160, 180, 200 to supply alternating power to a load L.
  • a feedback signal 226 is supplied from filter circuit 210 to modulator 100 to indicate loading on the circuit. Signal 226 is also supplied to a clipper circuit 220 which supplies
  • FIG. 3A illustrates example of an attenuator and amplifier system useful within the scope of the present invention
  • an amplifier A60 is connected in a differential mode to input AD through coupling capacitors C21, C22 and adjusting resistors R21, R22 to supply a signal 23 to a signal attenuation switch network 24.
  • the switch network consists of a number of solid state switches SWl—SW6, SW1B-SW6B cooperatively connected to switches SW1A-SW6A which in the example are manual switches to operate the solid state switches SW1-SW6 by means of inverting buffers B1-B6 but it will be understood that other means such as programmable controllers can also be used.
  • Resistor ladders (R1A-R6A), (R1B-R6B) (R1C-R6C) are provided and sized so that binary attenuation is provided by appropriate adjustment of the switch SW1A-SW6A positions to attenuate the signal in a binary format. That is, switch SWlA introduces a one dB change in characteristics while switch SW2A introduces a change of 2 dB, switch SW3A introduces a change of 4 dB and so on until switch SW6A introduce a change of 32 dB so that by proper selection of the switches any decibel(dB) attenuation between 0 and 63 can be provided to supply a selectively attenuated signal 31 at the output.
  • Attenuated signal 31 is supplied through a network terminating resistor R31 to signal buffer circuit including an operational amplifier A2 with negative feedback loop having a resistor R32.
  • the buffered signal 32 is then supplied through a series of high-pass low-pass amplifier systems as shown where RC pairs R3(A-E); R5(A-E) and C3CA-E); C5(A-E)are provided along with operational amplifiers A3-A5 each with a feedback loops respectively to define three high pass-low pass filter networks.
  • the signal 33 from amp A5 is supplied to a final filter including an amplifier A6 and resistors R33, R6A and capacitors C6E, C6A, C6B, C6E in feedback loops provided so that overall an eight order low pass filter and a seventh order high pass filter is provided.
  • a filtered attenuated audio signal J is provided from the filter network.
  • Figure 3A-36 also illustrate another feature of the present invention namely a clipping circuit operated by signal 225 from an LC filter 210 in the load output as shown in Figure 2 and 3C which operates the clipping circuit 220 to supply the signal 225 in direct response to the load.
  • clipping circuit power is supplied from a power tap S4 where an input voltage, for example plus 150 volts is supplied from the output of a terminal of the power supply previously described.
  • a voltage regulator RF3 is provided to supply an output signal 226 which is filtered by means of a RC filter R15-C15 to the base of a transistor Q221 which drives an opto isolator OP220A in responce to signal from R16 Jhaving its collector supplied by voltage source S4.
  • the emitter 72 of opto isolator OP220 is then supplied to an adjusting circuit including an op-amp A7 to operate as a DC bias eliminator to adjust the signal to keep the transistor of opto coupler OP220 at "0" volts, while still passing audio in a linear manner.
  • the emitter 72 of the opto coupler OP220 provides an adjusted AC signal 225 directly proportional to the current through the load L and in response to the signal 226 received from filter 210.
  • the signal 225 is directly proportional to the current through the load and is supplied through adjusting potentiometer P3 to op-amps A8, A9, of Figure 3A connected as a full wave rectifier to generate rectified signal 74 indicative of the loading which is supplied op-amp A9 which supplies a signal F which is indicative of loading on the unit.
  • a signal present indicator is also provided by means of amplifier AlO which gates transistor Qll in the preence of a load signal to turn on light emitting diode LED 11.
  • the signal F from the output of the amplifier All is supplied to an amplifier A15 having an output AF to be supplied to the base of a transistor Q20.
  • a potentiometer P223 is provided to adjust a voltage reference VR 220 to adjust the operational amplifier All which determines the level at which the current to load L is to be clipped as described hereinafter where the signal 74, 75 is provided to one input of operational amplifier All connected as differential amplifier having its second input from voltage reference VR 220 for example a part No. LN317 adjusted by means of a potentiometer P223 to adjust the reference signal to adjust output F from the operational amplifier All.
  • Potentiometer P223 sets the voltage clipping level and the signal F is supplied to an amplifier A13 to supply an inverted signal -F to an amplifier A14 and the signal F is supplied to amplifier A15.
  • the op-amps A14, A15 are operated in voltage bias mode -across the audio signal J where the reference for the inverting amplifiers is supplied from audio signal J through resistors R71, R72 with clamping diodes D5-D8, provided as shown.
  • the adjusted reference voltage -AF is supplied to adjust the signal J while the signal AF is supplied to the emitter of a transistor Q3 having its collector supplied from a voltage source S6 through a light emitting diode LED 2 and the transistor base operated by the audio signal J.
  • Output signal -AF is then connected to the audio channel signal to provide signal which is the combined effect of the audio signal and reference signal F. If the combined signal is in excess of the voltage necessary to gate the signal J is then increased to clip power as described hereinafter.
  • Diodes D5, D7 block the reference signals F, -F from the audio signal unless the audio exceeds the value of F or -F then they conduct the output of op-amps A15, A13 to clip the audio at the value of reference F or -F.
  • the transistor Q20 is in series with diode D7 and is turned on any time D7 is conducting.
  • the appropriate diode clamps the audio channel voltage at the reference before it can exceed the permissible band and limits the load current as described hereinafter as shown in Figure 3B.
  • the signal J is supplied to the inputs of op-amps A16 and A17 which supply inverted and balanced outputs K and L as inputs to op-amps A18, A19 connected as integrators.
  • the integrators are clocked by means of a pair of exclusive "OR" gates 0R1, 0R2 so signals M and N are provided at the outputs.
  • the input to the integrators A18, A19- is further modified by negative- feedback 274, 276 from load L as shown in Figure 2.
  • the feedback loops for op-amps A18, A19 including resistors R48, R47 and capacitors C25, C27 assist in converting the audio signal to a pulse width modified signal shown in Figure 4. It has been found that the arrangment shown creates generally flat audio response signals M, N to supplied the input of comparator A20 to generate a signal "0".
  • signal F is fixed at a setting which will clip the audio at a selected input level. If the maximum load current is exceeded the signal 74 will exceed this reference F and only then will it cause signal F to reduce and in turn reduce the input clipping level.
  • the signal 0 is applied to "OR" gates 0R3, 0R4 where the second input of “OR” gate 0R3 is grounded and the second input of “OR” gates OR4, OR5 is from a voltage reference S8.
  • the second input to “OR” gates OR5 , OR6 is from a clock CL101 which includes OR gates OR7, or OR8 driven by a timer Tl with appropriate adjustment.
  • the outputs from the "OR” gate, starting with “OR” gate OR110 are as follows where "OR” means exclusive “OR” Gates:
  • the output from the buffers B1-B4 drive the Mosfets Q13-Q20 which are paired to be connected to the primaries P2-P3 of transformers T4 and T5 so that the buffers cycle on and off to the primary coils. That is the current from primary P2 is slightly delayed to prevent overlap with the signal from primary 1 which is operated by the outputs from buffers Bl, B2. Operation of the units is cycled in order to provide the push-pull characteristics necessary to operate secondaries S1-S4 of transformer T4-T5 provided to be operated by the primary P2, P3 as shown.
  • Appropriate rectifiers circuits are F1-F4 -associated with the secondaries , 51-54 to operate "OR" gates OR9-OR12 and the outputs 161-164; 171-174; 181-184; and 191-194 to operate drive circuits DR1-DR4 utilizing quad OR gates OR13-OR24 as shown which in turn operate MOSFETS Q21-Q28 which, respectively operate MOSFETS Q29-Q32 where the MOSFETS (Q21, Q22) , (Q23, Q24), (Q25 , Q26) and (Q27,Q28) are tied together and the MOSFETS 29-Q32 are tied together as are MOSFETS Q30, Q31 to supply AC power to load L, through a filter 210 for example a notch filter as known in the art.

Abstract

Un système d'alimentation et d'amplification de basses fréquences comprend un amplificateur basse fréquence conçu pour recevoir un signal (AD) basse fréquence fourni à un atténuateur (70) qui reçoit et atténue sélectivement ledit signal, lequel est ensuite fourni à un circuit de tampon (80) et à un circuit de filtrage (90) servant à conditionner ledit signal. Le signal (99) ainsi atténué et filtré est ensuite délivré à un modulateur (100) où il est converti en un signal d'onde rectangulaire présentant une largeur d'impulsion qui est fonction du niveau du signal basse fréquence. Le signal d'impulsion d'onde rectangulaire est ensuite délivré à un convertisseur push-pull (110) qui produit un signal de courant alternatif fourni à la bobine primaire (P3, P4) d'un transformateur (T3, T4), un signal de sortie amplifié étant délivré à une charge (L) provenant de la bobine secondaire (S3A, S3B, S4A, S4B) du transformateur. Les caractéristiques de la charge sont analysées et un signal de chargement est fourni à un circuit écrêteur (220) qui empêche la sortie de dépasser des limites de charge sélectionnées.
PCT/US1986/001517 1986-07-17 1986-07-17 Systeme d'amplificateur de basses frequences WO1988000773A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US1986/001517 WO1988000773A1 (fr) 1986-07-17 1986-07-17 Systeme d'amplificateur de basses frequences
PCT/US1987/000680 WO1988000774A1 (fr) 1986-07-17 1987-03-30 Amplificateur basse frequence

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1986/001517 WO1988000773A1 (fr) 1986-07-17 1986-07-17 Systeme d'amplificateur de basses frequences

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PCT/US1986/001517 WO1988000773A1 (fr) 1986-07-17 1986-07-17 Systeme d'amplificateur de basses frequences
PCT/US1987/000680 WO1988000774A1 (fr) 1986-07-17 1987-03-30 Amplificateur basse frequence

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001035527A2 (fr) * 1999-11-11 2001-05-17 Broadcom Corporation Emetteur-recepteur pour gigabit ethernet, a extremite frontale analogique
US6876243B2 (en) 1999-11-11 2005-04-05 Broadcom Corporation High linearity large bandwidth, switch insensitive, programmable gain attenuator
US6894558B2 (en) 1999-11-11 2005-05-17 Broadcom Corporation Adjustable bandwidth high pass filter for large input signal, low supply voltage applications
US6967529B2 (en) 1999-11-11 2005-11-22 Broadcom Corporation Large dynamic range programmable gain attenuator

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986498A (en) * 1998-04-14 1999-11-16 Harman International Industries, Incorporated Audio direct from power supply
US6392476B1 (en) 2000-03-14 2002-05-21 Harman International Industries, Incorporated System and method of producing direct audio from a power supply

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4326170A (en) * 1980-06-09 1982-04-20 Siemens Corporation High power and/or high voltage switching operational amplifier
US4571551A (en) * 1984-02-28 1986-02-18 Washington Innovative Technology, Inc. Flyback modulated switching power amplifier

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4218660A (en) * 1978-11-06 1980-08-19 Carver R W Audio amplifier and method of operating the same
US4445095A (en) * 1980-05-19 1984-04-24 Carver R W Audio amplifier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4326170A (en) * 1980-06-09 1982-04-20 Siemens Corporation High power and/or high voltage switching operational amplifier
US4571551A (en) * 1984-02-28 1986-02-18 Washington Innovative Technology, Inc. Flyback modulated switching power amplifier

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001035527A2 (fr) * 1999-11-11 2001-05-17 Broadcom Corporation Emetteur-recepteur pour gigabit ethernet, a extremite frontale analogique
WO2001035527A3 (fr) * 1999-11-11 2002-03-07 Broadcom Corp Emetteur-recepteur pour gigabit ethernet, a extremite frontale analogique
US6472940B1 (en) 1999-11-11 2002-10-29 Broadcom Corporation Gigabit ethernet transceiver with analog front end
US6876243B2 (en) 1999-11-11 2005-04-05 Broadcom Corporation High linearity large bandwidth, switch insensitive, programmable gain attenuator
US6894558B2 (en) 1999-11-11 2005-05-17 Broadcom Corporation Adjustable bandwidth high pass filter for large input signal, low supply voltage applications
US6967529B2 (en) 1999-11-11 2005-11-22 Broadcom Corporation Large dynamic range programmable gain attenuator
US7038533B2 (en) 1999-11-11 2006-05-02 Broadcom Corporation Gigabit ethernet transceiver with analog front end
US7081790B2 (en) 1999-11-11 2006-07-25 Broadcom Corporation Adjustable bandwidth high pass filter for large input signal, low supply voltage applications
US7102428B2 (en) 1999-11-11 2006-09-05 Broadcom Corporation Large dynamic range programmable gain attenuator
US7106122B2 (en) 1999-11-11 2006-09-12 Broadcom Corporation High linearity large bandwidth, switch insensitive, programmable gain attenuator
US8841963B2 (en) 1999-11-11 2014-09-23 Broadcom Corporation Gigabit ethernet transceiver with analog front end

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