WO1987003447A1 - Procedure et dispositif pour la commutation croisee de lignes de transmission de donnees synchrones ou asynchrones, notamment pour la transmission de donnees en serie - Google Patents

Procedure et dispositif pour la commutation croisee de lignes de transmission de donnees synchrones ou asynchrones, notamment pour la transmission de donnees en serie Download PDF

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Publication number
WO1987003447A1
WO1987003447A1 PCT/HU1986/000063 HU8600063W WO8703447A1 WO 1987003447 A1 WO1987003447 A1 WO 1987003447A1 HU 8600063 W HU8600063 W HU 8600063W WO 8703447 A1 WO8703447 A1 WO 8703447A1
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WIPO (PCT)
Prior art keywords
lines
group
line
time slot
input
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Application number
PCT/HU1986/000063
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English (en)
Inventor
Ferenc BÁNKI
József HUNYADI
Pál KARÁDI
László KÖVESHEGYI
István MAYER
Eörs REÉ
Endre SZEBÉNYI
Zoltán SZEMEREKI
F. Károly SZÜCS
Original Assignee
Mta Központi Fizikai Kutató Intézete
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Publication of WO1987003447A1 publication Critical patent/WO1987003447A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Definitions

  • the subject of the invention is a procedure and a device for orosspoint-switching of asynchronous and/or sjmchronous data transmission lines, particularly for serial data transmission.
  • TDM Time Division Multiplex
  • Characteristic of the TDM systems is that the input data lines are sequentially sampled, and the switched output signals are regenerated from these data samples.
  • each of the data lines is sampled four times per one bit time, that means, 25 % system distortion arises on the regenerated output data.
  • Another feature of this concept is that the highest number of lines that may be switched is considerably limited by the sampling rate.
  • a great advantage of these switching systems is undoubtedly the fact that due to the bit oriented sampling method data switching itself does not require the exact anticipation of all of the bit, byte, protocol etc. characteristics (with the exception of the maximum data rate) of the data to be switched and transmitted (fully transparent data transmission), respectively,
  • a system operating on this principle is for example the EDXS line switching system of SIEMENS.
  • the EDXS system is basically, a character- oriented TDM multiplexer.
  • serial input characters are first transferred in bit-parallel format, then the parallel-format characters are sampled.
  • This solution increases total data transmission speed and capacity.
  • devices realizing this principle are relatively complicated and data transmission is not transparent any more at byte (or character) level.
  • Develnet an improved product of Develcon Electronics Corporation, can practically be regarded as a distributed data communication network operating as a statistical multiplexer.
  • the operation principle of STDM systems is that data (arriving from one or more appropriate inputs) are interpreted and temporarily stored in an input memory. Stored data are transferred via a statistically allocated data transmission medium to an output memory, from where data is given to one or more appropriate outputs.
  • every subscriber module being able to serve for eight input channels is controlled by its own Z8000 microprocessor.
  • the advantage of this method is that due to the statistical allocation of the data transmission medium data transmission capacity is extremely high as compared with traditional TDM systems. However, this solution is very expensive and complicated.
  • a further disadvantage is that data transmission is not transparent even on the system protocol level, that means, bit and data formats, moreover, all the protocols, being used along with the input channels must be known and fixed in advance, moreover, actively manipulated by the switching equipment itself, although it is merely a transmit medium.
  • the aim of the invention is to simultaneously eliminate said drawbacks and to develop a line switching system operating on a certain time division basis, which system
  • the basis of the invention is that the task can be easily solved if data signals arriving on input lines and to be switched are sampled at the moment when the logical state of said signal actually changes.
  • the procedure according to the invention is an improvement of a known procedure on course thereof it is first decided which of the date transmission lines being present should be interconnected to establish one or more connection paths between selected lines Then, a definite time slot is assigned to every connection path to be established. Thereafter, every (transmit) line transmitting data is sampled in the time slot assigned to the respective interconnection path and sampled values are given onto the predetermined line or lines and after every selected line has been sampled, the who'le process should be repeated.
  • the invention lies in the improvement that the input line is sampled at the very moment the logical state thereof changes, then both the signal sample and the value of the time when said signal changes is stored. Every line is successively sampled and subsequently the adequate sampled and stored values are successively given onto the predetermined lines in the appropriate time slot or slots assigned to respective, interconnection or interconnections, while both any possible new value appearing on any of the input lines and corresponding time value characterizing instant of any signal change are simultaneously stored for the next sequence of time slots. According to the invention moments of data changes and those of the time slots are suitably measured and determined in relation to the beginning of the respective sampling period.
  • the time value of the moment of signal change is transferred concurrently with the value of the sampled data.
  • the sample values, given out in the corresponding appropriate assigned time slot be received and stored at the indicated "channel, and thereafter, in relation to the beginning of the next sampling period, after a time period determined by the time value previously received has elapsed, output data be restored withthe logical state. determined by the last data sample.
  • the invented device is an improvement of a known device, which comprises a control unit, signal encoder and time slot assigner circuits, time slot selector and signal decoder circuits, respectively, which are one by one connected to a group of central lines.
  • the improvement lies in that said control unit, said signal encoder and time slot assigner circuits, further said time slot selector and signal decoder circuits are connected (in addition to said group of central lines) also to a group of internal lines.
  • the invented device is provided with a group of input lines representing inputs of said device and connected individually to corresponding inputs of said signal encoder and time slot assigner circuits, furhter with a group of output lines representing outputs of said device and connected one after the other to outputs of said time slot selector and signal decoder circuits.
  • said control unit suitably comprises a central processor unit, a synchronize unit and a supervisor unit.
  • Inputs/outputs of said central processor unit are connected to inputs/outputs of said synchronizer unit and to those of said supervisor unit via a bunch of central lines being a subset of said group of central lines.
  • the outputs of said synchronizer unit are applied to a first, a second and a third synchronizer line, said three lines listed above constituting a part of said group of central lines.
  • Inputs of said supervisor unit are taken from a group of supervisor lines, which form a part of said group of internal lines.
  • said signal encoder and time slot assigner circuit comprises a time slot assigner and enabler circuit, a gating circuit and a signal encoder circuit. Inputs/outputs of said time slot assigner and enabler circuit are connected to said bunch of central lines, representing a subset of said group of central lines, one of the inputs of said time slot assigner and enabler circuit is connected(via said first synchronizer line, being part of said group of central lines) to an input of said signal encoder circuit, a further input thereof comes from said third synchronizer line, being a part of said group of central lines, the outputs of said time slot assigner and enabler circuit are partly applied to the input of said gating circuit (via a time slog assigner line), partly connected to said group of supervisor lines, constituting a subset of said group of internal lines, respectively.
  • Further inputs of said signal encoder circuit are connected partly to said second synchronizer line, being part of said group of central lines, and partly to said group of input lines, respectively. Outputs of the above circuit are applied, via a group of encoded signal lines, to further inputs of said gating circuit. Outputs of said gating circuit are led to said group of internal lines.
  • said signal encoder circuit comprises a counter, a first storage block, a second storage block, a first bistable multivibrator, a second bistable multivibrator and a signal change indicator circuit , respectively.
  • Inputs of said counter are one by one connected to said first and said second synchronizer line (both being part of said group of central lines), furthermore, via said first synchronizer line to an input of said first and said second storage block, in addition to an input of said first and said second bistable multivibrator.
  • Outputs of said counter are connected (via a group of data lines) to data inputs of said first storage block. Further inputs of said second storage block are taken via a first group of stored data lines from outputs of said first storage block while outputs thereof are applied to a second group of stored data lines being a part of said group of encoded signal lines.
  • a further input of said first bistable multivibrator is connected via an input line representing a part of said group of input lines, to an input of said signal change indicator circuit and a further input thereof is connected via a write data line, to one of the inputs of the first storage block and to an output of said signal change indicator circuit.
  • An output of said first bistable multivibrator is applied to a further input of said second bistable multivibrator.
  • An output of said second bistable multivibrator is connected to a stored line which is a part of said group of encoded signal lines.
  • said signal encoder circuit includes also a third and a fourth storage block.
  • Inputs of said third storage block are connected to said bunch of input lines (which is a subset of said group of input lines), moreover, other inputs thereof are connected to said write data line and to said first synchronizer line.
  • Outputs of said third storage block are applied (via a third group of stored data lines) to inputs of said fourth storage block.
  • a further input of said fourth storage block comes from said first synchronizer line, its outputs are applied, to a fourth, group of stored data lines, which in turn is a subset of the group of encoded agnal lines.
  • said time slot assigner and enabler circuit comprises an address decoder unit, a time slot storage register, an enable register, a count register, a first gate circuit and a second gate circuit. Inputs of said address decoder unit are connected via said bunch of central lines being a subset of said group of central lines to inputs of said time slot storage register and to those of. said enable register.
  • An output of said address decoder unit is connected via a first selector line to an input of said time slot storage register and another output thereof is applied via a second selectro line an input of said enable register.
  • Inputs of sail count register come partly from said first and third synchronizer line, being part of said group of central lines on the one hand and via a group of time slot lines from outputs of said time slot storage register on the other hand.
  • An output of said count register is connected via a time slot line to an input of said first and to an input of said second gate circuit.
  • a further input of said first gate circuit comes via a first enable line from an output of said enable register, the output of said first gate circuit is connected to said time slot assigner line.
  • a further input of said second gate circuit is connected via a second enable line to a further output of said enable register.
  • Outputs of said second gate circuit are connected to said group of supervisor lines, which represent a subset of said group of internal lines.
  • the time slot selector and signal decoder circuit comprises a signal decoder circuit as well as a time slot selector and enabler circuit. Inputs of said time slot selector and enabler circuit are connected to said bunch of central lines, being a subset of said group of central lines, a further input thereof is connected via the first synchronizer line to an input of said signal decoder circuit with another input thereof connected to said third synchronizer line, while the output thereof is connected via a sampling line to an input, of said signal decoder circuit. Further inputs of said signal decoder circuit are connected partly to said group of internal lines, partly to said second synchronizer line being a part of said group of central lines while outputs of said signal decoder circuit are applied to said group of output lines.
  • said signal decoder circuit includes a time code store, a time counter, a first sign storage, a second sign storage and a first gate.
  • Inputs of said first sign storage are connected via said group of internal lines with inputs of said time code store, a further input is connected via the sampling line with a further input of said time code store, while the output of said first sign storage is applied to an input of said second sign storage, respectively.
  • Inputs of said time counter are connected to outputs of said time code store, a further input thereof is connected via the first synchronizer line with further input of said second sign storage and another input thereof to said second synchronizer line, while an output thereof is applied to an input of said first gate.
  • a further input of said first gate comes from an output of said second sign storage and an output thereof is led to an output line, being part of said group of output lines.
  • said signal decoder circuit also includes a first auxiliary store, a second auxiliary store and a second gate .
  • Inputs of said first auxiliary store are connected to said group of internal lines, another input thereof to said sampling line while its outputs are applied to inputs of said second auxiliary store.
  • a further input of said second auxiliary store is taken from said first synchronizer line, while outputs thereof are connected to inputs of said second gate.
  • a further input of said second gate comes from said output of said time counter. Outputs of said second gate are applied to said bunch of output lines being a subset of said group of output lines.
  • said time slot selector enabler circuit comprises an address decoder circuit, a time slot storage, an enabler unit, a time counter and an output gate.
  • Inputs of said address decoder circuit are connected to said bunch of central lines being a subset of said group of central lines, and via said bunch of central lines with inputs of said time slot storage and to those of said enabler unit, respectively,
  • Outputs of said address decoder circuit are connected via an addressing line to an input of said time slot storage and via the command line to an input of said enabler unit, respectively.
  • Inputs of said time counter are taken partly from outputs of the time slot storage, partly from said first and from said third synchronizer line, respectively, both being part of said group of central lines.
  • Fig. 1 is a time diagram illustrating the invented procedure
  • Fig. 2 is a further time diagram, illustrating additional details of the invented procedure
  • Fig. 3 is a block diagram, illustrating a conventional switching device improved according to the invention
  • Fig. 4 is a block diagram, illustrating a possible embodiment of the control unit in the invented device
  • Fig. 5 is a block diagram illustrating a possible embodiment of the signal encoder and time slot assigner circuit in the invented device
  • Fig. 6 is a block diagram illustrating a possible embodiment of the signal encoder circuit in the invented device
  • Fig. 7 is a block diagram illustrating a possible embodiment of the time slot assigner and enabler circuit in the invented device
  • Fig. 8 is a block diagram, illustrating a possible embodiment of the time slot selector and signal decoder circuit in the invented device
  • Fig. 9 is a block diagram illustrating a possible embodiment of the signal decoder circuit in the invented device
  • Fig. 10 is a block diagram illustrating a possible embodiment of the time slot selector and enabler circuit in the invented device.
  • Fig. 1 represents the time diagram of the multiplexing
  • Fig. 2 shows that of the demultiplexing part of the invented procedure.
  • signal manipulation is synchronized by three basic synchronizing signals. These are the following: frame synchron signal aa, time slot synchron signal bb and time code synchron signal cc.
  • the time code synchron signal cc is generated by means of said frame synchnron signal aa and time slot synchron signal bb.
  • a time slot signal dd is also generated in a way that as a consequence of a defined, subsequent OFF-ON transition following a preceding ON-OFF transition of said frame synchron signal aa of said time slot synchron signal said time slot signal dd goes to ON, and thereafter as a result of the immediately following OFF-ON transition of said time slot synchron signal bb said time slot signal dd goes to OFF again.
  • a simultaneous OFF-ON transitions of said frame synchron signal aa said time slot synchron signal bb and said time code synchron signal cc indicate the peculiar moment relatively to which a time distance value should be measured, for example by using a counter. The least significant bit. of this counter is shown on Fig.
  • Said transit sign signal kk and transit data signal 11 is sampled and stored by the time slot signal dd, especially as a third stored sign signal mm and a third stored data signal nn.
  • Said third stored sign signal mm will temporarily be stored as a fourth stored sign signal oo and simultaneously a timing is started practically by loading said third stored data signal mm into a counter then letting said counter count down.
  • This timing is represented oh Fig. 2 as a second time counter signal pp, the ON-OFF transition of which causes data according to said fourth stored sign signal oo to be gated onto the output as output channel data signal rr.
  • the device comprises a control unit 11, severel signal encoder and time slot assigner circuits 12a-12n and several time slot selector and signal decoder circuits 13a-13n, which are connected one by one to a group A of central lines.
  • Data arriving on one or any of groups C 1 -C n of input lines are received and sampled by the corresponding signal encoder and time slot assigner circuits 12-12n, that is they generate an appropriate time slot, and in said given, time slot they give sampled data onto the group A of central lines, if so instructed by a control unit 11 via group A of central lines.
  • the appropriate time slots (that is d ⁇ ta samples in the appropriate time slots) appearing on said group A of central lines are received by corresponding time slot selector and signal decoder circuit 13a-13n, if so instructed by said control unit 11 via said group A of central lines, and output data will regenerated from said data samples and given onto outputs (D 1 -D n group of output lines).
  • the invented device will also be described with reference to Fig. 3.
  • the invented device differs from the known solution in that a control unit 11, signal encoder and time slot assigner circuit 12a-12n and time slot selector and signal decoder circuits 13a-13n are connected hot only to said group A of centrallines but also to a group B of internal lines.
  • Inputs are represented by group C 1 -C n of input lines connected individually to inputs of said signal encoder and time slot assigner circuits 12a-12n.
  • GroupD 1 - D n of output lines connected one after the other to the outputs of said time slot selector and signal decoder circuits 13a- 13n constitute, however, the outputs of the device.
  • the operation of the device according to the invention differs from that of the known solution in that said signal encoder and time slot assigner circuit 12a-12n instead of immediately generating a time slot pulse (and sampling at the same time ), at first indicates signal change on its input and determines and stores sign and time of this change. Thereafter, if so instructed by said control unit11, it gives identification (sign) of data onto the group A of central lines and at the same time it gives time code (that is the value of time elapsed from a relative time base up to the signal change) onto, said group B of internal lines,too. Output data will be regenerated from these two types of data samples by said time slot selector and signal decoder circuits 13a-13n. Output data regenerated in this way will be equivalent to the input data with regard to both sign and phase.
  • Said control unit 11 of the invented device will be described hereinafter with reference to Fig. 4 in detail.
  • Said control unit 11 includes a central processor unit 14, a synchronizer unit 15 and a supervisoer unit 16.
  • Inputs/outputs of said central processor unit 14 are connected via a bunch E of central lines to inputs/outputs of said synchronizer unit 15 and those of said supervisor unit 16 which bunch E is a subset of said group A of central lines.
  • Outputs of said synchronizer unit 15 are applied to first, second and third synchronizer lines b, g and h, respectively, said three lines constituting a part of said group A of central lines.
  • Inputs of said supervisor unit 16 are taken from a group G of supervisor lines being part of said group B of internal lines.
  • central processor unit 14 controls the operation of said synchronizer unit 15, supervisor unit 16 and furthermore that of said signal encoder and time slot assigner circuits 12a-12n and said time slot selectro and signal decoder circuits 13a-13n being connected to said group A of central lines.
  • said central processor unit 14 may expediently be a microprocessor.
  • synchronizer unit 15 generates major synchronizer pulses, appearing on the first b, second g and third h synchronizer lines at a repetition rate (frequency) adjustable by program upon sending an appropriate microprocessor command to synchronizer 15 unit via said bunch E of central lines.
  • Said supervisor unit 16 is practically a programmable data input unit having max, n number of input lines which are connected to said group G of supervisor lines, comprising n number of separate supervisor lines.
  • each of said signal encoder time slot assigner circuits 12a-12n generates a pulse onto appropriate lines of said group G of supervisor lines assigned to a given signal encoder and time slot assigner circuit 12.
  • the supervisor unit 16 recognizes (by supervising the input lines) whether one or more of the signal encoder and time slot assigner circuits 12a-12n give a pulse onto the wires of the group B of internal lines and if more than one pulse is recognized an error message will be sent via said bunch E of central lines to said central processor unit 14.
  • Said signal encoder time slot assigner circuits 12 comprise a time slot assigner enabler circuit 20, a gating circuit 21 and a signal encoder circuit 22. Inputs/outputs of said time slot assigner and enabler circuit 20 are connected to said bunch E of central lines, representing a subset of said group A of central lines, while one of its inputs is connected (via said first synchronizer line b being part of said group A of central lines) to an input of said signal encoder circuit 22, a further input of the above circuit comes, from said third synchronizer line h, being part of said group A qf central lines.
  • Outputs of said time slot assigner and enabler circuit 20 are partly applied via the i time slot assigner line to an input of said gating circuit 21, partly connected to said group G of supervisor lines constituting a subset of said group B of internal lines. Further inputs of said signal encoder circuit 22 are connected partly to said second synchronizer line g being part of said group A of central lines, partly to said group C of input lines. Outputs of the above circuit are applied via group K of encoded signal lines to further inputs of said gating circuit 21. Outputs of said gating circuit 21 are connected to group B of internal lines.
  • Said signal encoder circuit 22 synchronized by the pulses arriving on said first and second synchronizer line b and g, respectively, periodically generates time code and sign of the data signal changes, further status code of auxiliary signals, characterizing data flow appearing on said group C of input lines, and gives these codes onto said group K of encoded signal lines.
  • Said time slot assigner and enabler circuit 20 being programmable via said bunch E of central lines and synchronized by said first and third synchronizer line b and h, respectively, periodically generates time slot assigner pulses corresponding to the logical channel being assigned to the given device and gives these pulses onto said time slot assigner line i.
  • Said gating circuit 21 gates codes arriving on said group K of encoded signal lines during pulses appearing on time slot assigner line i to said group B of internal lines. Concurrently with said time slot assigner pulse, appearing on the i time slot assigner line said time slot assigner and enabler circuit 20 gives also a pulse to on appropriate wire of said group G of supervisor lines, constituting a subset of said group B of internal lines.
  • Said signal encoder circuit 22 includes a counter 23, a first storage block 24, a second storage block 25, a first bistable multivibrator 52, a second bistable multivibrator 26 and a signal change indicator circuit 27.
  • Inputs of said counter 23 are one by one connected to said first and second synchronizer line b and g, furthermore, via the first synchronizer line b to an input of said first and second storage block 24 and 25 and in addition to one of the inputs of said first and second bistable multivibrator 52 and 26, respectively.
  • Outputs of said counter 23 are connected via a group L of data lines to data inputs of said first storage block 24.
  • Further inputs of said second storage block 25 are taken via a first group M of stored data lines from outputs of said first storage block 24 while outputs thereof are applied to a second group N of stored data lines, which represent a subset of said group K of encoded signal lines.
  • a further input of said first bistable multivibrator 52 is connected via an input line c representing a part of the group C of input lines to an input of said signal change indicator circuit 27, and a further input thereof is connected via a write data line f to an input of said first storage block 24 and to an output of said signal change indicator circuit 27.
  • An output of said first bistable multivibrator 52 is applied to a further input of said second bistable multivibrator 26.
  • An output of said second bistable multivibrator 26 is connected to said stored line k, which is a part of said group K of encoded signal lines.
  • Output values of said counter 23 will be incremented (the counter counts "up") as an effect of every OFF-ON transition appearing on said second synchronizer line g, however said counter 23 will be cleared as soon as a pulse appears on said first synchronizer line b.
  • Data outputs of said counter 23 appear on group L of data lines. If the logical state of a signal applied to said input line c changes, said signal change indicator circuit 27 generates a pulse on its output and applies it to said write data line f. This pulse appearing on the write data line f causes the sign of data change occuuing on the input line c (practically the signal state immediately following the transition) enter into said first bistable multivibrator 52. Thus the new signal state will be stored.
  • a further possible embodiment of the invented signal encoder circuit 22 will also be explained with reference to Fig. 6.
  • This embodiment of said signal encoder circuit 22 differs from that detailed above in that it comprises further a third and a fourth storage block 28 and 29, respectively.
  • Inputs of said third storage block 28 are connected to a bunch R of input lines (which is a subset of said group C of input lines), moreover other inputs thereof are connected to said write data line f and to said first synchronizer line b.
  • Outputs of said third storage block 28 are applied (via a third group 0 of stored data lines) to inputs of said fourth storage block 29.
  • a further input of said fourth storage block 29 comes from said first synchronizer line b and outputs thereof are connected to a fourth group P of stored data lines which is in turn a subset.of said group K of encoded signal lines.
  • data inputs of said third storage block 28 are connected to said bunch R of input lines being a subset of said group C of input lines and carrying auxiliary signals of the input data channel presented on group C of input lines.
  • To an input of said third storage block 28 is connected said write data line f, too.
  • Said third storage block 28 is loaded with actual data being present on its input when, a pulse arrives on said write data line f or on said first synchronizer b being connected to load inputs thereof. That is, said third group 0 of stored data lines carries information being characteristic of the state of auxiliary signals arriving on said group C of input lines and of signalchange on said inpul line c.
  • Said fourth storage block 29 will be loaded with data being present on said third group O of stored data lines as soon as a pulse arrives on said first synchronizer line b.
  • Said fourth group P of stored data lines connected to outputs of said fourth storage block 29 constitutes a subset of said group K of encoded signal lines.
  • Said time slot assigner and enabler circuit 20 will be explained with reference to Fig. 7.
  • Said time slot assigner and enabler circuit 20 comprises an address decoder unit 30, a time slot storage register 31, an enable register 32, a count register 33, a first gate circuit 34 and a second gate circuit 35.
  • Inputs of said address decoder unit 30 are connected via said bunch E of central lines to inputs of said time slot storage register 31 and to those of said enable register 32.
  • An output of said address decoder unit 30 is connected via a first selector line m to an input of said time slot storage register 31 another output thereof is applied via a second s elector line n to an input of said enable register 32.
  • Inputs of said count register 33 come partly from said first and third synchronizer line b and h, respectively, these lines being part of said group A of central lines, and partly via group T of time slot lines, from outputs of said time slot storage register 31.
  • Outputs of said countregister 33 are connected via a time slot line t to an input of said first and second gate circuit 34 and 35, respectively.
  • a further input of said first gate circuit 34 comes via a first enable line r from an output of said enable register 32, while an output of said first gate circuit 34 is connected to said time slot assigner line i.
  • a further input of said second gate circuit 35 is connected via a second enable line s to a further output of said enable register 32, while outputs of this circuit are connected to said group G of supervisor lines, which represent a subset of said group B of inernal lines.
  • Operation of said time slot assigner and enabler circuit 20 may be programme-controlled, that is said time slot storage 31 and said enable register 32 can be loaded with data via said bunch E of central lines.
  • Programmed instructions, intended to select and load said time slot storage 31 and enable register 32 are recognized by said address decoder unit 30 which generates a select pulse on said first selector line m or on said second selector line n, respectiveli if one of the above registers is to be loaded.
  • Pulses on said first selector line m load said time slot storage register 31 with data characteristic of the time slot assigned to a specific group C 1 -C n of input lines, while pulses appearing on said second selectro line n loads said enable register 32 with data permitting or inhibiting the codes characterizing the given input data to be periodically gated on said group B of internal lines.
  • Said count register 33 is periodically loaded with data appearing on outputs of said time slot storage register 31 and carried by said group T of time slot lines and said count register 33 will be loaded whenever a pulse appears on said first synchronizer line b. Every time a pulse arrives on said third synchronizer line h said count register 33 counts down (its contents will be decremented).
  • a pulse will periodically be generated, inparticular, exactly one pulse after each pulse appearing on said first synchronizer line b, and the interval between the first synchronizer pulse and the time slot pulse being determined by data stored in said time slot storage register 31. If enabled by the logical level being present on said output of said enable register 32 and on the first enable line r connected thereto then pulses given onto said time slot line t will appear on the output of said first gate circuit 34 and on said time slot assigner line i, too.
  • the time slot selector and signal decoder circuit 13 comprises a signal decoder circuit 36 and a time slot selector enabler circuit 37.
  • Inputs of said time slot selector and enabler circuit 37 are connected to said bunch E of central lines, being a subset of said group A of central lines and a further input is connected via said first synchronizer line b to an input of said signal decoder circuit 36 and a further input thereof to said third synchronizer line h.
  • An output of the above circuit is connected to a sampling line n, and via said sampling line u to an input of said signal decoder circuit 36.
  • Further inputs of said signal decoder circuit 36 are connected partly to said group B of internal lines and partly to said second synchronizer line g being part of said group A of central lines. Outputs of said signal decoder circuit 36 are applied to said group D of output lines.
  • Said time selector and enabler circuit 37 being programcontrolled via said bunch E of central lines periodically generates and gives a sampling pulse onto said sampling line n which sampling pulse corresponds to the time slot number assigned to the corresponding input channel.
  • Sampling pulses are. generated synchronously with pulses periodically arriving on said first synchronizer line b.
  • said signal decoder circuit 36 samples corresponding signals arriving on said group B of internal lines and regenerates output data signals of the respective channel from these samples using synchronizer pulses periodically arriving on said first and third synchronizer line b and h and these regenerated signals will be given onto said group D of output lines.
  • a possible embodiment of the invented signal decoder circuit 36 will be described with reference to Fig. 9 in detail.
  • Said signal decoder circuit 36 includes a time code store 38, a time counter 39, a first sign storage 40, a second sign storage 41 and a first gate 42.
  • Inputs of said first sign storage 40 are connected via said group B of internal lines to the inputs of said time code store 38, a further input is connected via said sampling line u with a further input of said time code store 38 while an output of said first sign storage 40 is applied to an input of said second sign storage 41.
  • Inputs of said time counter 39 are connected to outputs of said time code store 38 and a further input thereof is connected via said first synchronizer line b to a further input of said second siga storage 41 and another input to said second synchronizer line g while its output is applied to an input of said first gate 42.
  • a further input of said first gate 42 comes from an output of said second sign storage 42 and its output is led to an output line d being part of said group D of output lines.
  • said first sign storage 40 loaded with a data bit representing the sign of data to be transmitted.
  • a pulse arriving on said synchronizer line b clocks data appearing on said outputs of said time code store 38 into said time counter 39.
  • said second sign storage 41 will be loaded with a bit value being present on said output of said first sign storage 40. Every time a pulse arrives on said second synchronizer line g said time counter 39 counts down, i.e.
  • This embodiment of said signal decoder circuit 36 differs from the above that it comprises further a first auxiliary store 43, a second auxiliary store 44 and a second gate 45.
  • Inputs of said first auxiliary store 43 are connected to said group B of internal lines, another input thereof to said sampling line u and its outputs are applied to inputs of said second auxiliary store 44.
  • a further input of said second auxiliary store 44 is taken from said first synchronizer line b and outputs thereof are connected to inputs of said second gate 45.
  • a further input of said second gate 45 comes from said output of said time counter 39.
  • Outputs of said second gate 45 are applied to said bunch Q of output lines being a subset of said group D of output lines, A pulse arriving on said sampling line u loads said first auxiliary store 43 with data appearing on group B of internal lines and carrying sampled values of auxiliary signals of the given channel. Data appearing on said outputs of said first auxiliary store 43 is clocked in said second auxiliary store 44 by a pulse arriving on said first synchronizer line b. Said outputs of said second auxiliary store 44 carrying auxiliary signals of the given (transmitted) channel will be clocked in said second gate 45 by a pulse generated by said borrow output of said time counter 39. The outputs of said second gate 45 are connected directly to said bunch Q of output lines being a subset of said group D of output lines. In a concrete realization of the device said first gate 42 and second gate 45 practically can . be latch-type storage devices.
  • said time slot selector and enabler circuit 37 comprises an address decoder circuit 47, a tide slot storage 48, an enabler unit 49, a time counter 50 ar.i an output gate 51.
  • Inputs of said address decoder circuit 47 are connected to said bunch E of central lines, which is a subset of said group A of central lines, and via said " bunch B of central lines to inputs of said time slot storage 48 and to those of said enabler unit 49.
  • Outputs of said address decoder circuit 47 are connected via an addressing line v to an input of said time slot storage 48 and via a command line w to an input of said enabler unit 49, respectively.
  • Inputs of said time counter 50 are taken partly from outputs of said time slot storage 43 partly from said first and third synchroniser line b and h, respectively, both being part of said group A of central lines.
  • An output of said time counter 50 is applied to an input of said output gate 51.
  • a further input of said output gate 5 ⁇ comes from an output of said enabler unit 49 and an output thereof is • connected to said sampling .line u.
  • Said address decoder circuit 47 monitors instructions arriving on bunch E of central lines (being a subset of group A of central lines) an.d recognizes those addressing said time slot storage 48 and/or said enabler unit 49. If an instruction relates to said time slot storage 48, said address decoder circuit 47 generates a pulse onto said addressing . line v. If said enabler unit 49 is addressed, a pulse is given onto, said command line w by said address decoder unit 47. A pulse, arriving on said addressing line n clocks corresponding data
  • the invented procedure keeps the advantages of the known simple TDM systems as regards the BIT-LEVEL TRANSPARENCY of data transmission between channels to be interconnected. This feature may be of a great importance in such cases, when data have to be treated secretly. This characteristic is however important in other respects, too, i.e. data transmission and line switching can be carried out with uniform devices and uniform methods even if data formats are known but diverse. 2. As compared with simple, traditional TDM systems the invented procedure has the essential advantage that theoretically data samples should only be transferred between the channels to be Interconnected once per bit time,because the relative time of data changes occuring within a bit time is determined by the time code and embedded in the data samples.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Au cours de la procédure, il convient de décider laquelle des lignes de transmission de données en présence sera connectée et à quelle autre. Puis on affecte une tranche de temps à chaque chemin de connexion à établir. Ensuite, chaque ligne de transmission est échantillonnée dans la tranche de temps affectée à une interconnexion spécifique, et les valeurs échantillonnées sont données à la ligne correspondante, et après l'échantillonnage de toutes les lignes sélectionnées, on répète l'intégralité du processus. Les lignes de données doivent être échantillonnées au moment même où le signal se modifie sur la ligne, puis il y a lieu de mémoriser les données échantillonnées et une valeur de temps correspondant au moment relatif de la modification du signal. Lors de l'échantillonnage de toutes les lignes, les valeurs échantillonnées et mémorisées correspondantes seront successivement données aux lignes prédéterminées dans les tranches de temps affectées, tandis que de nouvelles valeurs possibles de signaux de ligne et des valeurs de temps caractérisant les modifications de signaux sont concurremment mémorisées pour la séquence périodique suivante de tranches de temps. Le dispositif ci-décrit comprend une unité de commande (11), des circuits codeurs de signaux et décodeurs de signaux (13a-13n), qui sont un à un connectés à un groupe de lignes centrales (A) et à un groupe de lignes internes (B). Un groupe de lignes d'entrée (C1-Cn) sont connectées individuellement à des entrées des circuits de codage de signaux et d'affectation des tranches de temps (12a-12n), et un groupe de lignes de sortie (D1-Dn) sont connectées l'une après l'autre à des sorties dudit sélecteur de tranches de temps et desdits circuits de décodage de signaux (13a-13n).
PCT/HU1986/000063 1985-11-29 1986-11-28 Procedure et dispositif pour la commutation croisee de lignes de transmission de donnees synchrones ou asynchrones, notamment pour la transmission de donnees en serie WO1987003447A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
HU4565/85 1985-11-29
HU456585A HU194465B (en) 1985-11-29 1985-11-29 Method and device for the matrix interconnection of synchronous and/or asynchronous digital data transfer lines, advantageously in the case of serial data transfer

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WO1987003447A1 true WO1987003447A1 (fr) 1987-06-04

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AU (1) AU6720187A (fr)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0312911A2 (fr) * 1987-10-21 1989-04-26 Advanced Micro Devices, Inc. Appareil et méthode de synchronisation maître/esclave

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1411873A (en) * 1972-03-23 1975-10-29 Siemens Ag Time division multiplex switching arrangements
EP0085226A2 (fr) * 1981-12-22 1983-08-10 Northern Telecom Limited Réseau de commutation pour un système multiplex à division dans le temps
GB2128450A (en) * 1982-10-04 1984-04-26 Hitachi Ltd Time-division switching unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1411873A (en) * 1972-03-23 1975-10-29 Siemens Ag Time division multiplex switching arrangements
EP0085226A2 (fr) * 1981-12-22 1983-08-10 Northern Telecom Limited Réseau de commutation pour un système multiplex à division dans le temps
GB2128450A (en) * 1982-10-04 1984-04-26 Hitachi Ltd Time-division switching unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0312911A2 (fr) * 1987-10-21 1989-04-26 Advanced Micro Devices, Inc. Appareil et méthode de synchronisation maître/esclave
EP0312911A3 (en) * 1987-10-21 1990-09-26 Advanced Micro Devices, Inc. Master/slave synchronizer

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Publication number Publication date
HU194465B (en) 1988-01-28
HUT42219A (en) 1987-06-29
EP0247131A1 (fr) 1987-12-02
AU6720187A (en) 1987-07-01

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