WO1987002155A1 - Reseau de communications pour communications par paquets entre multiprocesseurs - Google Patents

Reseau de communications pour communications par paquets entre multiprocesseurs Download PDF

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Publication number
WO1987002155A1
WO1987002155A1 PCT/US1986/002039 US8602039W WO8702155A1 WO 1987002155 A1 WO1987002155 A1 WO 1987002155A1 US 8602039 W US8602039 W US 8602039W WO 8702155 A1 WO8702155 A1 WO 8702155A1
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WIPO (PCT)
Prior art keywords
port
message
communication
processor
communication processor
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PCT/US1986/002039
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English (en)
Inventor
Alan Lynn Davis
Shane V. Robison
Kenneth Scott Stevens
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Schlumberger Technology Corporation
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Publication of WO1987002155A1 publication Critical patent/WO1987002155A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/28—Routing or path finding of packets in data switching networks using route fault recovery
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]

Definitions

  • the present invention relates to the field of special purpose processing units for use in computer systems and more specifically to communication processors for communicating between individual computers in a multicomputer data processing system.
  • the Von Neuman design consists of a central processing unit which is coupled to a memory.
  • the central processing unit is responsible for carrying out the various calculations specified by a program which is stored in the memory. The data used in these calculations is also stored in the memory.
  • the memory consists of a plurality of storage slots, referred to as words.
  • the central processing unit itself has a very small storage capacity. Typically, the central processing unit fetches the next instruction to be executed from the memory, then fetches any data required which is not already in the central processing unit, executes the instruction in question, and stores the result back in the memory.
  • the basic Von Neuman system is limited in speed by the speed of the central processing unit.
  • One prior art solution to the speed limitations of the basic Von Neuman design involves connecting multiple processing units to the same memory unit. Each of the processing units is connected to a common bus which links the processing units to the memory. Each processing unit runs independently of the others. Some form of bus arbitration is used to resolve conflicts between two processing units which seek to control the bus at the same time for the purpose of accessing the memory.
  • the program to be executed by the system is broken into a number of subprograms, each of which is executed by one of the processing units.
  • the ability to improve the speed of the system through this form of concurrent processing is limited by the need to use a common bus to link the memory to each processing unit.
  • the memory In the exemplary situation where 1000 of such data words are to be processed by this program, the memory must be accessed 100 times every time a word is processed. The data word must be fetched from memory. Then the 98 instructions of the program must be fetched which requires the memory to be accessed 98 more times. Finally, the result must be stored. In a shared bus system, the number of times memory must be accessed to apply this program to 1000 data words is 100,000. If the processing unit has its own memory, then the communication link need only be used to send the 98 instructions once in addition to the 1000 data words to the processing unit and the 1000 resulting data words back from the processing unit. Hence, the communication link need only be accessed 2098 times for the same computation which required 100,000 accesses in the shared bus system. This allows a larger number of processing units to share the same communication link. However, the number can not be made arbitrarily large, since sooner or later the ability of the communication link to service all the processing units will become limiting.
  • the super communication link processor can only handle a few clusters. This can be seen as follows: the super communication link has no greater capacity than one of the individual buses in a cluster, since if it were possible to make a super communication link with a greater capacity, that design could also be used in each cluster. Consider the case in which each processor in a cluster receives its work only through the super communication link.
  • the number of processors in the cluster is chosen such that the cluster bus is working at capacity; that is, it is saturated by the communication tasks needed to receive the work for each processor from the super communication link and to return the results of those tasks through the super communication link. But each piece of this data had to come from the super communication link; hence it also must be saturated by the load needed to service this one cluster.. Thus, in this case, the super communication link can service only one cluster. This results from the assumption that each processor in the cluster receives its work only from the super communication link. Hence, for a super communication link to service more than one cluster, each cluster must generate and "consume" most of the communication traffic on its internal bus. This requirement limits the use of such pyramid architectures.
  • a second problem inherent in the pyramided cluster approach is the need to introduce a new type of processor, the super communication link processor, as the system is expanded.
  • VLSI fabrication techniques have greatly improved the cost of highly repetitive functional elements such as those used to construct the individual processing units and memories within a cluster.
  • the cost of low volume parts used in the super communication link processor can be quite high.
  • the additional level of complexity also leads to an additional level of complexity in the software needed to drive the system. The software must now manage the division of the problem being solved into large pieces to be sent to each cluster as well as into smaller pieces which are to be allocated to each processing unit within a cluster.
  • each super communication link processor is a potential communication bottleneck.
  • messages a large volume of information
  • This exchange can occupy so much super communication link processor time that there is no time remaining for transmitting messages between other clusters attached to that super communication link processor. This can result in the other clusters running out of' work and standing idle, which reduces the system throughput.
  • a means of rerouting messages through alternate super communication link processors which are not saturated is needed. It is difficult to construct a convenient structure for providing such alternate routing in this type of pyramided architecture.
  • this type of pyramid structure is not sufficiently fault tolerant. As the number of processing units in a system is increased, the probability that one processing unit must be placed off-line due to malfunction increases. If the processing unit in question is a super communication link processor, all of the clusters it serviced must also be taken out of service.
  • the present invention consists of a communication network formed by a plurality of communication processors which are connected together in such a way that messages can be sent efficiently between any two processors in a multiprocessor data processing system.
  • the data processing system consists of a plurality of data processors which are preferably identical. Each data processor is coupled to a communication processor which is responsible for sending and receiving messages between itself and other communication processors which are coupled to other data processors.
  • the communication processors are organized into a two dimensional hexagonal array. Each communication processor communicates with the 6 communication processors adjacent to it through 6 ports. Each such port couples the communication processor in question to a corresponding port in one of the 6 communication processors adjacent to it.
  • a given data processor When a given data processor wishes to send a message to another data processor in the multiprocessor system, it places that message in its memory and then signals the communication processor coupled to it.
  • the communication processor has access to the data processor's memory.
  • the signal indicating that a message is ready to send includes the necessary information for the communication processor to locate the message in question in the data processor's memory. Once this signal is given, the data processor is free to continue its other computations.
  • the communication processor relieves the data processor of essentially all of the overhead involved in communicating with other data processors in the multiprocessor system.
  • the communication processor sends the message through the appropriate port to an adjacent communication processor. If the final destination of the message is the data processor coupled to the adjacent communication processor, that communication processor will cause the message to be stored in said data processor's memory. If the destination is not the data processor coupled to the adjacent communication processor to which the message was sent, the adjacent communication processor will relay the message to a third communication processor which is adjacent to it. The message will be so relayed until it reaches the communication processor coupled to the data processor which is its final destination.
  • the message routing algorithm used by each of communication processors automatically reroutes messages around communication bottlenecks created by a malfunctioning communication processor or by a local communication overload. If a message is to be sent to a communication processor and the most efficient route for sending that message is not available because of a local communication overload, the message will be automatically rerouted.
  • the communication processors on the edge of the hexagonal array do not have a port of an "adjacent" communication processor coupled to each of their ports.
  • the ports which lack such a coupling are connected to a routing switch which allows these ports to be coupled either to the corresponding ports of a communication processor on the opposite edge of the hexagonal array by an external signal path or to an external device or processor.
  • This coupling to the opposite edge of the hexagonal array reduces the transmission time for messages having destinations which are far from the data processor in which the message originates. It may be shown that this external signal path system provides the shortest path length for transmitting messages in the hexagonal array.
  • These edge ports also provide a means for communication with the world outside the multiprocessor system analogous to an input-output port on a conventional computer.
  • Figure 1 illustrates a communication network according to the present invention.
  • Figure 2 is a detailed view of the couplings between corresponding ports on adjacent communication processors.
  • Figure 3(a) shows a larger communication network constructed from 7 smaller hexagonal communication networks.
  • Figure 3(b) shows an alternate configuration for the larger communication network shown in Figure 3(a).
  • Figure 4(a) illustrates the routing of a message between non-adjacent communication processors in a communication network based on a hexagonal array.
  • Figure 4(b) illustrates the routing of a message between non-adjacent communication processors in a communication network based on a square array.
  • Figure 5 illustrates the signal path connections used to couple ports on opposite edges of the hexagonal array.
  • Figure 6(a) illustrates a method for determining which ports on the edge of the hexagonal array are to be coupled together.
  • Figure 6(b) shows the numbering of the ports on each communication processor.
  • Figure 7(a) and (b) each show a routing diagram for communication processors in a hexagonal array having three communication processors on each side of said array.
  • Figure 8 illustrates a coordinate system for locating a given communication processor in an infinite hexagonal array.
  • Figure 9 illustrates an adaptation of the coordinate system shown in Figure 8 to a hexagonal array having three communication processors on each side of said array.
  • Figure 10 is a block diagram of a communication processor used in the preferred embodiment of the present invention.
  • Figure 11 is a flow chart for the operations carried out by the port controller when a packet is sent.
  • Figure 12 is a flow chart for the operations carried out by a port when a packet is sent.
  • FIG 13 is a flow chart for the operations carried out by a port when a packet is to be received.
  • the present invention consists of a communication network for transmitting messages between data processors in a multiprocessor data processing system. Each data processor is connected to a communication processor which communicates with other communication processors in the network. It will be apparent to those skilled in the art that each of the data processors may be replaced by a cluster of data processors consisting of two or more processing units coupled to a memory.
  • a communication network having nineteen communication processors according to the present invention is illustrated in Figure 1. For clarity, the data processor or processors connected to each communication processor is not shown.
  • the communication network consists of a hexagonal array 20 of communication processors of which communication processor 22 is typical. Larger communication networks can be constructed by employing hexagonal arrays which have larger numbers of communication processors on each side.
  • Each communication processor is represented by a hexagon because it has 6 ports for communicating with neighboring communication processors. A message may be either sent or received over any of these ports. This is shown in detail in Figure 2.
  • the ports 24 in each communication processor are numbered from 1 to 6. Each port 24 is connected to a corresponding port 24 of an adjacent communication processor. Port 1 is connected to port 4 of an adjacent communication processor. Port 2 is connected to port 5 of a different adjacent communication processor. Port 3 is connected to port 6 of yet another adjacent communication processor, and so on.
  • the port connections used for communication processors which are on the edge of the hexagonal array will be described in detail below.
  • the communication processor itself is a concurrent processor which is capable of performing several tasks simultaneously.
  • Each of the ports operates independently of other ports.
  • messages may be sent or received at one time.
  • messages may transferred to and from the data processor memory while other messages are being sent and received by the ports.
  • a message is routed between communication processors by transferring the message to an adjacent communication processor which in turn passes it on to one of its adjacent communication processors, and so on, until the message reaches the communication processor connected to the data processor which is the message's final destination.
  • the routing algorithm used in this process does not require global information such as a map of the entire communication network to enable the algorithm to route messages.
  • Such information would have to be stored in a table whose size is dictated by the number of communication processors in the communication network. If the number of communication processors in the network is increased, the size of these tables must be increased. This would necessitate hardware modifications in all of the communication processors and is clearly undesirable. As will be described below, the present invention avoids such tables.
  • a data processor when a data processor wishes to transmit a message to another data processor in the hexagonal array, it transfers that message to its memory together with the destination of the message. It then signals the communication processor connected to it.
  • the communication processor connected to it has access to the data processor's memory. Said communication processor reads the message from the data processor's memory; hence the data processor need take no further actions to affect the transmission of the message.
  • the transmitting communication processor codes the message for transmission and assigns it to one of its ports. If the final destination of the message is a data processor connected to one of the adjacent communication processors, the port connecting the two communication processors is assigned to the message. If the final destination of the message is a more distant data processor, then a port which minimizes the transmission time is chosen in a manner as will be described in detail below.
  • a communication processor When a communication processor receives a message on one of its ports, it examines information contained in a message header which specifies the final destination of the message to determine if the message is to be delivered to a data processor connected to said communication processor. This header information is placed in the message by the communication processor which originally sent the message. If said data processor is the final destination, the communication processor stores the message in the memory of the data processor and informs the data processor that a message has arrived. If said data processor is not the final destination of the message, the communication processor retransmits the message as it would a message originating in the data processor connected to it.
  • This type of hexagonal array communication topology has several advantages over the prior art.
  • Communication networks of arbitrary size may be constructed either by using a single hexagonal array or by combining several hexagonal arrays.
  • Figure 3(a) illustrates one of the possible larger networks which may be constructed by combining seven smaller hexagonal arrays 32 through 38.
  • Each of these smaller arrays contains nineteen communication processors in this example.
  • the center communication processor of each array has been labeled with the number of the array. For clarity, the boundary of each array is delineated by a broken line. An arbitrary number of such arrays can be combined without the need to introduce any connecting elements into the communication network.
  • the special purpose communication processors used in prior art systems to combine groups of data processors are eliminated in the present invention.
  • FIG. 3(b) A second network similar to that shown in Figure 3(a) is shown in Figure 3(b). It consists of 7 arrays 32' through 38'. It differs from the network shown in Figure 3(b) in that array 33* is higher in the diagram than array 34'; whereas in the array shown in Figure 3(a), array 34 is higher than array 33. The significance of these types of combined arrays will be explained in more detail below.
  • a hexagon is the highest order regular polygon which may be used to tile a surface without leaving spaces between the polygons. Hence, a hexagon is the highest order polygon which efficiently utilizes the surface area of the chip.
  • the array must either be hexagonal, pentagonal, square, or triangular. Since there is no preferred direction for message propagation, the processor array should not have a preferred direction. This is equivalent to requiring that, in addition to tiling the entire surface of the chip,- the processor array must be symmetrical about two orthogonal axes in the plane containing the communication processor array. Triangular and pentagonal arrays lack this symmetry and hence are not suitable for the communication network.
  • FIG. 4(a) a portion of a hexagonal array according to the present invention is shown at 40.
  • the optimum route for this message is through communication processor 48.
  • This route requires that the message be transmitted two times, once by communication processor 42 and once by communication processor 48.
  • communication processor 48 is unable to receive a message because it is overloaded or because it has a malfunction, the message may be sent by either of two alternate paths.
  • the first such path is through communications processors 43 and 45, and the second such path is through communication processors 46 and 47.
  • Each of these alternative paths requires that the message be transmitted three times, i.e., one more time than over the optimum path.
  • FIG. 4(b) an analogous portion of a square array of communication processors is shown at 50.
  • a message which originates in communication processor 52 whose final destination is communication processor 54.
  • the only path over which it may be sent with a delay that is equal to the time needed to transmit it twice is the path through communication processor 56.
  • communication processor 56 If communication processor 56 is unable to receive a message because it is overloaded or because it has a malfunction, the message must be routed through communication processors 58, 60, and 62, thereby creating a transmission time equal to the time needed to transmit it four times.
  • the hexagonal array is superior to the square array in overload and malfunction situations, since the alternate paths to non-adjacent communication processors are shorter.
  • the communication processors which are on the edge of the hexagonal array do not have sufficient adjacent communication processors to couple to each of their ports.
  • the communication processors on the edge have only 3 or 4 adjacent communication processors to which they can be coupled.
  • Figure 5 shows a hexagonal array with nineteen communication processors (three communication processors on a side ) at 70.
  • Each of the communication processors 74 on the edge of the array 70 has two or three ports which are not coupled to an adjacent communication processor. A typical such port is shown at 72.
  • These ports will hereinafter be referred to as peripheral ports.
  • Each peripheral port is connected to a routing switch 76.
  • Each routing switch 76 has two routing ports 78 and 80. Each of.
  • the routing ports 80 is connected to a corresponding routing port 80 on a routing switch 76 on the opposite edge of the hexagonal array by a signal path of which 82 is typical.
  • the signal paths and routing switches 76 connecting the other one or two ports on each of the edge communication processors 74 have been omitted from Figure 5 for clarity.
  • a message leaving one of the peripheral ports on an edge communication processor 74 is wrapped around to the opposite edge of the hexagonal array. This reduces the time needed to transmit a message between communication processors which are far apart in the hexagonal array.
  • the choice of which peripheral ports are connected by a given signal path will be described in detail below.
  • the second routing port 78 on each routing switch 76 is used to couple the hexagonal array to the "outside world".
  • the routing switches 76 are controlled by data in the header information of each message. Messages which are to be transmitted to the "outside world" are coded with a predetermined header which specifies an internal destination which is recognized by the routing switch 76 receiving the message from an adjacent communication processor 74. Similarly, messages from an external device which are destined for a data processor connected to the hexagonal array are coded with a header identifying the data processor in question. When a switch 76 receives such a message, it routes it to the communication processor connected to it.
  • the choice of peripheral ports to be connected by a signal path 82 is dictated by two considerations. First, these connections often determine the time needed to transmit a message between two communication processors. It is important that this time be minimized.
  • peripheral ports may best be illustrated with reference to a communication network having nineteen communication processors in a hexagonal array with three such communication processors on each edge, as illustrated in Figure 5.
  • the method of determining the connections may be more easily understood with reference to the diagram shown in Figure 6(a).
  • This diagram shows a nineteen communication processor communication network 84 connected to six phantom communication networks 86 through 91.
  • Each of the phantom communication networks is a copy of the communication network 84.
  • Each of the communication processors in communication network 84 is labeled with a label from 0a to 18a which identifies its position in the communication network in which it appears.
  • the phantom networks 86-91 are labeled in the same way.
  • each communication processor has six ports which are labeled from 1 to 6 as shown in Figure 6(b).
  • a connection between any two communication processors may be specified by giving the labels of each of the ports which are connected together, and by giving the labels of the communication processors which contain each of the ports in question.
  • port 6 of communication processor 3a is connected to port 3 of communication processor 2a.
  • an interconnection between two edge processors in network 84 would be described, for example, as follows.
  • Port 6 of communication processor 9a in communication network 84 is connected to port 3 of communication processor 14a in phantom communication network 86. As described below, this corresponds to signal path 82 shown in Figure 5.
  • the corresponding peripheral port in communication network 84 to which it is to be connected by a signal path is determined as follows. Find the peripheral port in question in communication network 84 and determine the communication processor.and peripheral port to which it is connected in the appropriate phantom communication network 86, 87, 88, 89, 90, or 91. Connect said peripheral port to the peripheral port having the same communication processor and port labels in communication network 84.
  • port 6 of communication processor 9a in communication network 84 is connected to port 3 of communication processor 14a in phantom communication network 86. Therefore, a signal path is created, using routing switches 76, to connect port 6 of communication processor 9a in communication network 84 to port 3 of communication processor 14a in communication network 84. As mentioned above, this is the signal path which is shown at 82 in Figure 5.
  • This signal path connection scheme allows each communication processor to "imagine" that it is located in a large array without signal path connections. To decide on the routing of a message to be sent to a specific communication processor, it must only examine the communication processors around it in the large array diagram shown in Figure 6(a) until it finds the communication processor having a label matching the label of the communication processor to which the message in question is to be sent. It is apparent from an examination of Figure 6(a), that the communication processor need look no further than two communication processors away in network 84 to find any given label.
  • this signal path connection scheme allows a message to be transmitted between any two data processors in network 84 with a delay which is at most that needed by the communication network to transmit the message twice. This is clearly the minimum possible delay for a hexagonal array having three communication processors on a side.
  • a given communication processor must at most store that part of the diagram shown in Figure 6(a) which shows the locations of each communication processor which is within two communication processors of the communication processor in question.
  • This portion of said diagram referred to as a routing diagram, is itself a hexagonal array with the communication processor in question at its center.
  • the routing diagrams for communication processors 5a and 9a are shown in Figure 7(a) and Figure 7(b), respectively.
  • Each communication processor has the information contained in the relevant routing information stored in it.
  • the only thing which distinguishes one communication processor from another in the communication network 84 is the specific routing diagram stored in each communication processor.
  • both the hardware and software for each communication processor are identical. This greatly simplifies the construction of a communication network according to the present invention.
  • the routing diagram can be reduced to an algorithm whose storage requirements are independent of the size of the hexagonal array. 5
  • the above analysis was performed using a phantom hexagonal array diagram, shown in Figure 6(a), which was patterned after that shown in Figure 3(a).
  • FIG.b there is a second possible diagram of this form which was shown in Figure 3(b) . It
  • FIG. 25 in Figure 6(a) can be constructed showing the communication network in question together with six phantom copies of it.
  • the peripheral ports are connected by signal paths which connect each peripheral port to the port of the communication processor on the
  • Each communication processor would be within E-l communication processors of each other communication processor in the hexagonal array. It may be shown (see Schlumberger Palo Alto Research Report #47) that this is the minimum possible distance between communication processors.
  • the present invention is the most efficient communication network in terms of the number of times a message must be retransmitted to reach its final destination.
  • the signal paths and routing switches provide improved performance in larger networks constructed by combining several hexagonal arrays as shown in Figures 3(a) and 3(b).
  • the routing switches are used to make the connections between the individual hexagonal arrays.
  • a communication processor not contain global information which must be stored in a table whose size depends on the size of the hexagonal array. This is because, if such a table is required, the maximum size of the hexagonal array which may be constructed will depend on the available space in this table.
  • the routing diagram described above is such a table.
  • the present invention also provides a solution to this problem.
  • the present invention uses a labeling scheme for the communication processors which allows the information contained in said routing diagram to be reduced to an algorithm whose storage requirements are independent of the size of the hexagonal array.
  • a communication processor according to the present invention can be used in a communication network of any size, where the network is connected as a hexagonal array.
  • FIG. 8(a) A portion of an "infinite" hexagonal array is shown at 91'.
  • Each communication processor is assigned a label which consists of two numbers, (x,y) , which specify the location of each communication processor in a coordinate system which is analogous to coordinates in a Cartesian coordinated system. These two numbers are shown in each hexagon separated by a comma.
  • the axes of this coordinate system are shown at 92.
  • the coordinate system differs from a Cartesian coordinate system in that the axes are not orthogonal and in that a third axis, labeled D, is defined.
  • each axis corresponds to two ports. For example, a message sent from port 1 or port 4 will be propagated in a direction parallel to the D axis.
  • the ports are numbered as shown at 93 in Figure 8(b).
  • a communication processor can compute the optimum path to any other communication processor without the need for a routing diagram.
  • the communication processor which is sending a message will be referred to as the sender, and the communication processor which is to be the final destination of said message will be referred to as the receiver.
  • the sender first computes the angle of the line relative to the x-axis which joins the sender to the receiver. This angle is referred to as the receiver angle.
  • Each port is assigned a "port" angle which is equal to the angle of the line connecting the sender to the communication processor adjacent to the sender which is connected to said port.
  • the port angles are also calculated relative to the x-axis.
  • the port angle of port 1 is 60 degrees
  • the port angle of port 2 is 120 degrees
  • a list of the ports in order of preference is then computed by ordering the ports using the absolute value of the difference of the receiver angle and each port angle. For example, consider a message which is to be sent from the communication processor at (0,0) to the communication processor at (1,2).
  • the receiver angle (the angle of the line joining center of the communication processor at (0,0) to center of the communication processor at (1,2)) is 90 degrees.
  • ports 1 and 2 are preferred, since they each have port angles which differ from the receiver angle by 30 degrees.
  • Ports 6 and 3 are the next most preferred ports, since they each have port angles which differ from the receiver angle by 90 degrees, and so on.
  • the receiver angle would be 120 degrees and only one port, port 2 would be preferred.
  • the next most preferred ports would be ports 1 and 3 in this case, and so on.
  • the above described routing algorithm may be applied to a finite hexagonal array communication network according to the present invention.
  • a communication network according to the present invention based on a hexagonal array having three communication processors on each side is shown at 94 in Figure 9.
  • the boundaries of the hexagonal array are delineated by bold lines.
  • the relevant portions of the six phantom copies of the hexagonal array are shown outside these lines.
  • these phantom copies are used to simplify the calculation of the optimum routing when the signal paths joining opposite edges of the hexagonal array 94 are used for routing a message.
  • These phantom copies allow each communication processor to compute the coordinates of any other communication processor in the hexagonal array.
  • each communication processor must store a number specifying the size of the hexagonal array, so that the position of this discontinuity and the coordinates of the next communication processor beyond the discontinuity may be calculated.
  • a second difference between the finite hexagonal array and the infinite hexagonal array is that ' a given communication processor may be reached by traveling along a number of different directions.
  • the communication processor at (-2,-2) may be reached from the communication processor at (0,0) by proceeding along the positive y-axis, by proceeding along the negative D-axis or by proceeding along the positive D-axis to the communication processor at (1,1) and then along the line parallel to the positive X-axis.
  • the correct path is chosen as follows.
  • the sender computes the coordinates of the receiver which is within E-l communication processors of the sender, where E is the number of communication processors on a side of the hexagonal array 94.
  • the signal paths connecting communication processors on the edge of the hexagonal array 94 are chosen such that every communication processor is within E-l communication processors of every other communication processor.
  • the receiver's coordinates will only appear once within a distance of E-l communication processors from the sender.
  • the sender can assign a list of ports, in order of preference, to be used to send a message to any receiver in the hexagonal array using the algorithm described with reference to an infinite hexagonal array.
  • the sender calculates the re ⁇
  • the communication processor having the coordinates of the receiver which is within E-l communication processors of the sender. To do this, it calculates the position of each communication processor in the hexagonal array or in the six virtual copies thereof which has the same coordinates as the receiver. It then selects the communication processor whose position is within E-l communication processors of the sender. The sender then computes the angle of the line joining this communication processor to the sender and computes a list of ports, in order of preference, to be used in sending the message. The message is then sent to the adjacent communication processor connected to the port of highest preference. If there are two such ports, then the; message is sent by the first such port which is free. If this adjacent communication processor is unavailable, e.g. busy on another task or inoperative, the next highest preference port is used, and so on until the message is successfully transmitted to an adjacent communication processor.
  • the preferred embodiment of a communication processor according to the present invention is shown at 100 in Figure 10. It has four basic elements.
  • the first element is a buffer 102 which is used to store messages which pass through the communication processor.
  • the second element is a port controller 104 which supervises the transmission of messages through the third basic element, the ports 106.
  • the forth basic element is a direct memory access controller 108 which supervises the transfer of messages between the buffer 102 and the memory 110 of the data processor 111 connected to the communication processor in question.
  • long messages are divided into a plurality of small messages which are referred to as packets.
  • the division of a long message into a series of packets is carried out by the direct memory access controller 108, as will be described in more detail below.
  • Each packet contains a header which identifies the message to which it belongs and the final destination of the packet.
  • the header also contains the number of packets in the message and the position of the packet in question in said message.
  • the header also includes error checking information used by the ports 106 to verify that a message has been properly sent and received.
  • the buffer 102 is divided into a plurality of storage slots. Each storage slot is used to store one packet.
  • the size of a packet is chosen to be the length of the average message sent in the data processing system.
  • a packet stored in the buffer 102 may be transferred' to a port 106 over a bus 112 which is shared by the six ports 106 and the direct memory access controller 108. Conflicts over the use of the bus 112 are resolved by a buffer controller which is part of the buffer 102. The priority of the various operations carried out by the communication processor will be discussed in more detail below.
  • the bus 112 Since the bus 112 must service all six ports 106 and the direct memory access controller 108, the time needed to transfer a packet from the buffer 102 to a given port 106 or to the direct memory access controller must be small compared to the time needed to output a packet on a given port 106. If this is not the case, a packet may have to wait in the buffer 102 even when the port 106 to which it is destined is free.
  • the width of the bus 112 is large enough to transfer a packet in two bus cycles. This is about one tenth the time needed to output the packet through a port 106.
  • Each of the ports 106 contains an internal buffer which is sufficient to store one packet. Hence each port 106 can operate independently of the buffer 102 and the other ports 106.
  • a port 106 When a port 106 is used to transfer a packet from the buffer 102 to the an adjacent communication processor, it transfers the packet from the buffer 102 and stores said packet in its internal buffer. The port 106 then transmits the packet independently of other operations in the communication processor. Similarly, when a port 106 is to receive a packet from an adjacent communication processor, said port accumulates the packet in its internal buffer.
  • the buffer 102 contains a controller which is responsible for the allocation of storage space in the buffer. When a port 106 has received a packet which is be stored in the buffer 102 it requests buffer space from the buffer controller. Similarly, when a packet has been successfully transmitted to an adjacent communication processor, the port controller 104 signals the buffer controller which then makes the space occupied by the packet in question available.
  • a flow chart for the operations carried out by the port controller 104 is shown in Figure 11.
  • the port controller 104 cycles through the packets in the buffer 102 until it finds a packet which is ready to be sent.
  • the port controller determines the preferred port or ports for sending the packet.
  • the final destination of the packet is a data processor whose communication processor does not lie on a line parallel to one of the axes, there will be more than one optimum route to said communication processor. That is, the packet may be sent from more than one port without introducing a delay.
  • the port controller assigns the packet to the first such port which is free. If one of the preferred ports 106 is free, it signals the port in question to take the packet. If neither of the preferred ports is free, a counter is incremented and -29-
  • the port controller 104 then returns to cycling though the packets in the buffer 102 until it finds the next packet which is to be sent. If the port 106 to which the packet was assigned successfully completes the transmission of the packet, it signals the port controller 104. The port controller 104 then signals the buffer controller which frees the space previously occupied by said packet. If the port 106 in question reports a failure in transmitting the packet, the counter associated with the packet in question is incremented and tested as described above.
  • the packet should not be sent out the same port over which it was received. If this rule is not followed, the packet may be passed back and forth between the same two communication processors until a more optimum routing becomes available. This is referred to as "thrashing". In addition to delaying the movement of the packet to its destination, thrashing increases the communication load on the two communication processors between which the packet is passed.
  • Information specifying the port 106 over which the packet was received is stored with the packet in the buffer 102. This information is provided by the port 106 which received the packet in question. Thus the port controller has the necessary information to avoid this problem.
  • the third route passes through the communication processors at (1,-1), (2,0), and (2,1)
  • the fourth route passes through the communication processors at (2,-1), (2,0), and (2,1). Since there are three optimum routes possible if the packet is sent via the communication processor at (1,-1) , port 2 which connects the communication processor in question to the communication processor at (1,-1) is preferred over port 1 which connects the communication processor in question to the communication processor at (2,-1) .
  • Port 2 allows a greater degree of routing flexibility in subsequent routing decisions.
  • this "flexibility" information is used both in the determination of the optimum port over which the packet is to be sent and in the determination of an alternate port if the optimum port is unavailable.
  • the angle computation algorithm described above automatically takes this information into account.
  • the difference in the the angle between the line joining the communication processor at (1,-2) to the communication processor at (2,2) and angle of the line through port 2 parallel to the y axis is less than the difference between the angle of said line and the angle of the line through port 1 parallel to the D axis.
  • port 2 would be automatically chosen.
  • the availability of the alternate ports must be taken into consideration. Consider a case in which there are two alternate ports with the same path length, but different "flexibilities".
  • the critical value of the counter which measures the "staleness" of the packet represents a time which is greater than the time needed to retransmit the packet once on average. Hence it is better to send the packet via a slightly inferior route than to wait for the slightly better route.
  • the port controller could merely assign the packet to a randomly selected alternative port which is not the one over which the packet was received. This port could be chosen from those ports which do not involve sending the packet in a direction which puts it further from its final destination. Although such a random assignment algorithm is less efficient, it requires less hardware to implement and hence may be preferable for economic reasons.
  • a flow chart for operations carried out by a port 106 when the port controller requests it to transmit a packet is shown in Figure 12.
  • the port 106 receives a request to transfer a packet and it is busy, it sends a signal to the port controller 104 which is the same as the signal sent for an unsuccessful attempt to send a packet. If the port 106 in question is free, it signals the buffer controller which transfers the packet to the buffer in the port 106 in question. The port 106 then attempts to establish a communication link with the corresponding port 106 in the adjacent communication processor to which it is connected. If it fails, it signals the port controller 104. If it succeeds, it transmits the packet in question and waits for the receiving port 106 to signal that the packet was correctly received.
  • the port 106 in question increments a counter. If the count in said counter is less than a predetermined critical value, it sends the packet in question again. If said count is greater than said critical value, it signals the port controller 104 that it failed to complete the transmission. If the receiving port 106 acknowledges a successful transmission, the port 106 in question signals the port controller 104 that the packet was successfully sent. It then enters a wait state.
  • FIG. 13 A flow chart of the operations performed by a port 106 when an adjacent communication processor wishes to send it a packet is shown in Figure 13.
  • the port 106 in question is busy when it receives the request, it signals the sending port. This situation can arise when the port in question has not yet transferred a previously received packet from its buffer to the buffer 102. If the port 106 in question is free, it takes the packet in question. At the same time, it requests buffer space from the buffer controller in the buffer 102. Upon completion of the transmission, the port in question tests the packet for correct transmission using a conventional cyclic redundancy check. If the packet was not correctly transmitted, it signals the sending port. If the packet was successfully transmitted and space was available in the buffer 102, it transfers the packet to the buffer 102 to be stored at the location assigned by the buffer controller. If space was not available, it signals the sending port that the transmission failed.
  • the direct memory access controller 108 cycles through the packets stored in the buffer 102 until it finds the stored packet which has been waiting the longest for further processing and which has the communication processor in question as its final destination. It examines the header information in the packet to determine whether the message from which this packet was derived required more than one packet. If only one packet was used, the direct memory access controller 108 stores the message part of the packet in the memory of the data processor and signals the data processor that a message has arrived.
  • the direct memory access controller 108 includes a table which is used to reassemble messages which were divided into more that one packet. If the message in question had more than one packet, the direct memory access controller 108 consults this table to determine if this is the first packet to be received from that message. If it is the first packet, the direct memory access controller 108 starts an entry for this message in the table and allocates sufficient space in the memory of the data processor to store the entire message. The direct memory access controller 108 then stores the packet in question at the appropriate location in the memory block reserved for this message in the data processor's memory. It then searches for other packets in the buffer 102.
  • the direct memory access controller 108 makes an entry in the table indicating that this packet has been received and then stores it at the appropriate location in the memory of the data processor. If the packet in question was the last remaining packet needed to complete the message, the direct memory access controller 108 erases the table and signals the data processor that a message has been received.
  • the data processor When the data processor has a message to send, it signals the direct memory access controller 108, giving the location of the message in the data processor memory 110. The direct memory access controller 108 then fetches the message, assigns appropriate header information to the message, and divides it into packets. The packets are then stored in the buffer 102. A unique message label is included in the header information to enable the receiving communication processor to distinguish the packets of this message from packets from other messages. For example, this label may consist of the identity of the communication processor sending the message and a sequence number which is incremented each time a message is sent by said communication processor.
  • the priorities of the various tasks carried out by the communication processor and the allocation of space in the buffer 102 are chosen so as to minimize the possibility of a bottleneck.
  • the six ports 106 and the direct memory access controller 108 all share the same buffer 102 from which packets are retrieved for transmission and stored on arrival.
  • This shared buffer minimizes the number of internal busses and wires and reduces the amount of buffer space needed in each communication processor.
  • this architecture also results in potential problems of contention for the buffer as a shared resource.
  • Deadlock will occur if all of the buffer space becomes filled with messages which cannot be delivered because the adjacent communication processors are all too busy to accept packets.
  • Traffic patterns consist of outbound packets from the local data processor connected to the communication processor in question to a remote communication processor, inbound packets from a remote communication processor whose destination is the data processor connected to the communication processor in question, and intercommunication processor traffic consisting of packets originating in a remote communication processor which are being relayed by the communication processor in question on towards their final destinations. Both outbound packets and intercommunication processor packets route packets through the ports 106. Inbound packets must also flow through the direct memory access controller 108.
  • the buffer allocation algorithm used in the preferred embodiment is guaranteed not to create deadlock. This is accomplished by reserving sufficient free buffer space to allow packets to circulate across the communication network without deadlock, while allocating this buffer space in a manner which will also result in efficient packet flow across the hexagonal array. In the worse case, a delay in the packet transmission occurs.
  • the buffer 102 contains space for at least four packets. Simulations of systems with buffer space for differing numbers of packets indicate that the optimum buffer storage capacity in a hexagonal array having three communication processor on a side is 19 packets.
  • the buffer space may be used by any port 106 or the direct memory access controller 108 for traffic in any direction until there is only free space for 3 packets in the buffer 102 * At this point, incoming packets from the ports 106 must be tested to assure that they will not cause a deadlock to occur. Space for one inbound packet must always be free to assure that deadlock will not occur. Any incoming packet from a port 106 which would cause deadlock is refused.
  • the preferred embodiment reserves space for three more packets in order to increase efficiency.
  • the direct memory access controller 108 will no longer add packets to the buffer. In this case, the direct memory access controller 108 will only remove inbound packets from the buffer. If an inbound packet on one of the ports 106 is destined for the data processor connected to the communication processor in question and another packet so destined is already queued for direct memory access controller 108 transmission to the data processor, the inbound packet will be refused by the port 106.
  • Intercommunication processor packets are accepted so long as the acceptance of said packets will leave space in the buffer 102 for one inbound packet to the data processor connected to the communication processor in question. This strategy has the effect of lowering the priority of packet "producers" and increasing the priority of packet "consumers" when the communication network becomes overloaded locally.
  • the port controller 104 When packets are queued in the buffer 102 for delivery to adjacent communication processors, the port controller 104 continually attempts to reduce the number of packets in the buffer 102 by delivering them to their destination ports 106. This is done by matching the destination port 106 of each packet with an available port list. As explained above, if a desired port 106 is busy, a count is incremented for the packet in question. When the count exceeds a predetermined value, the port 106 assigned to that packet is changed to an alternate port 106 if possible. Reducing the number of queued packets has priority over accepting new packets for storage in the buffer 102. Hence the port controller 104 gives priority over the bus 112 to ports 106 which are ready to transmit a packet to an adjacent communication processor.
  • the direct memory access controller 108 has the highest priority when it is transferring packets from the buffer to the data processor connected to the communication processor in question.

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Abstract

Réseau de communications (70) formé par une pluralité de processeurs de communications qui sont reliés entre eux de façon que des messages puissent être échangés de manière efficiente entre deux processeurs dans un système de traitement de données à processeurs multiples. Chaque processeur de données est couplé à un processeur de communications (74) qui se charge de l'envoi et de la réception de messages provenant des autres processeurs de communications couplés à d'autre processeurs de données. Les processeurs de communications sont organisés en un réseau hexagonal bi-dimensionnel. Les processeurs de communications acheminent un message d'un processeur émetteur à un processeur récepteur à travers le réseau de communications. L'algorythme d'acheminement de messages utilisé par chaque processeur de communications réachemine automatiquement les messages de manière à contourner les éventuels goulots d'étranglement dans le réseau de communications provoqués par la défaillance d'un processeur de communications ou par une surcharge locale de communications.
PCT/US1986/002039 1985-09-27 1986-09-26 Reseau de communications pour communications par paquets entre multiprocesseurs WO1987002155A1 (fr)

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EP0341905A2 (fr) * 1988-05-13 1989-11-15 AT&T Corp. Calculateur ayant un système de mémoire intelligente
FR2638260A1 (fr) * 1988-10-26 1990-04-27 Onera (Off Nat Aerospatiale) Dispositifs de commutation et reseaux de communication de donnees pour systemes multiprocesseurs
EP0460599A2 (fr) * 1990-06-06 1991-12-11 Thinking Machines Corporation Processeur massivement parallèle comprenant un système de livraison de message basé sur le principe des files d'attente
EP0472879A2 (fr) * 1990-08-27 1992-03-04 International Business Machines Corporation Méthode et appareil pour la détection dynamique et le routage de trafic non uniforme dans des réseaux d'interconnexion parallèle multiniveaux bufferisés
EP0505780A2 (fr) * 1991-03-29 1992-09-30 International Business Machines Corporation Diffusion de priorité et transferts multiples pour un réseau à plusieurs étages non bufferisés
EP0505782A2 (fr) * 1991-03-29 1992-09-30 International Business Machines Corporation Réseau multifonction
EP0506135A2 (fr) * 1991-03-29 1992-09-30 International Business Machines Corporation Appareil pluri-émetteur/commutateur pour rapporter des statuts sur des réseaux à plusieurs étages non-bufferisé asynchrones
EP0505779A2 (fr) * 1991-03-29 1992-09-30 International Business Machines Corporation Appareil de commutation à double priorité pour réseaux simplex
GB2303524A (en) * 1995-07-19 1997-02-19 Fujitsu Ltd Software distribution network
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GB2213027B (en) * 1987-12-01 1992-03-04 Texas Instruments Ltd A digital electronic system
GB2213027A (en) * 1987-12-01 1989-08-02 Texas Instruments Ltd A digital electronic system
EP0341905A2 (fr) * 1988-05-13 1989-11-15 AT&T Corp. Calculateur ayant un système de mémoire intelligente
EP0779584B1 (fr) * 1988-05-13 1999-09-29 AT&T Corp. Appareil de stockage d'information pour un processeur hÔte
US5134711A (en) * 1988-05-13 1992-07-28 At&T Bell Laboratories Computer with intelligent memory system
EP0341905A3 (fr) * 1988-05-13 1992-01-22 AT&T Corp. Calculateur ayant un système de mémoire intelligente
EP0366520A1 (fr) * 1988-10-26 1990-05-02 Office National d'Etudes et de Recherches Aérospatiales (O.N.E.R.A.) Réseau de communication de données pour systèmes multiprocesseurs
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EP0460599A2 (fr) * 1990-06-06 1991-12-11 Thinking Machines Corporation Processeur massivement parallèle comprenant un système de livraison de message basé sur le principe des files d'attente
EP0460599A3 (en) * 1990-06-06 1993-03-03 Thinking Machines Corporation Massively parallel processor including queue-based message delivery system
EP0472879A2 (fr) * 1990-08-27 1992-03-04 International Business Machines Corporation Méthode et appareil pour la détection dynamique et le routage de trafic non uniforme dans des réseaux d'interconnexion parallèle multiniveaux bufferisés
EP0472879A3 (en) * 1990-08-27 1993-08-04 International Business Machines Corporation Method and apparatus for dynamic detection and routing of non-uniform traffic in parallel buffered multistage interconnection networks
US5654695A (en) * 1991-02-22 1997-08-05 International Business Machines Corporation Multi-function network
US5444705A (en) * 1991-02-22 1995-08-22 International Business Machines Corp. Dual priority switching apparatus for simplex networks
EP0505779A2 (fr) * 1991-03-29 1992-09-30 International Business Machines Corporation Appareil de commutation à double priorité pour réseaux simplex
EP0506135A3 (en) * 1991-03-29 1993-11-03 Ibm Multi-sender/switching apparatus for status reporting over unbuffered asynchronous multi-stage networks
EP0505782A3 (en) * 1991-03-29 1993-11-03 Ibm Multi-function network
EP0505779A3 (en) * 1991-03-29 1993-11-03 Ibm Dual priority switching apparatus for simplex networks
EP0505780A3 (en) * 1991-03-29 1993-11-03 Ibm Priority broadcast and multi-cast for unbuffered multi-stage network
EP0506135A2 (fr) * 1991-03-29 1992-09-30 International Business Machines Corporation Appareil pluri-émetteur/commutateur pour rapporter des statuts sur des réseaux à plusieurs étages non-bufferisé asynchrones
EP0505782A2 (fr) * 1991-03-29 1992-09-30 International Business Machines Corporation Réseau multifonction
US5680402A (en) * 1991-03-29 1997-10-21 International Business Machines Corporation Priority broadcast and multi-cast for unbuffered multi-stage networks
EP0505780A2 (fr) * 1991-03-29 1992-09-30 International Business Machines Corporation Diffusion de priorité et transferts multiples pour un réseau à plusieurs étages non bufferisés
GB2303524A (en) * 1995-07-19 1997-02-19 Fujitsu Ltd Software distribution network
US5822519A (en) * 1995-07-19 1998-10-13 Fujitsu Limited Method for transferring data to a plurality of modes connected in series by employing an intermediate mode and dividing the system into a plurality of virtual groups
US6018773A (en) * 1995-07-19 2000-01-25 Fujitsu Limited Method and apparatus for transferring information to a plurality of offices in series in a network
GB2303524B (en) * 1995-07-19 2000-05-17 Fujitsu Ltd Method and apparatus for transferring information

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EP0244443A4 (fr) 1989-06-21
CA1263760A (fr) 1989-12-05
EP0244443A1 (fr) 1987-11-11

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