WO1987001887A1

WO1987001887A1 - Digital-to-analogue and analogue-to-digital converters

Info

Publication number: WO1987001887A1
Application number: PCT/GB1985/000432
Authority: WO
Inventors: Eric Andrew Faulkner
Original assignee: Eric Andrew Faulkner
Priority date: 1984-09-14
Filing date: 1985-09-18
Publication date: 1987-03-26
Also published as: GB8522673D0; GB8423226D0; EP0236315A1; GB2164511A

Abstract

Digital-to-analogue converter (DAC) comprising means for splitting a digital number to be converted into a more significant part and a less significant part, two DAC means, a resistive chain connected between the outputs of the said DAC means and having 2Nnodes (where the less significant part has N digits), switches between each node and common output terminal, means for supplying the DAC means with the digit of the more significant part (of value A) and the digital value (A+1) respectively, and means for closing the switch at that node numbered from the DAC means to which the value A is fed corresponding to the value of the less significant part. The invention further provides an anologue-to-digital converter (ADC) employing similar DAC means.

Description

DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERTERS

High-speed data converters (i.e. converters for use in the speed-resolution range where capacitor-charge methods are too slow) are based on resistive networks which are traditionally derived either from the R-2R ladder (successive-approxiraation converters etc.) or from the nR chain (flash converters).

The present invention provides a system which overcomes the disadvantages of these methods in an important range of applications. The Digital-to-Analog Conversion method first to be described is based on a hardware structure consisting of two M-bit digital-to-analog converters operating as current-output devices, two operational amplifiers (OA), and a resistive chain consisting of 2^N resistors with an analog switch or a comparator connected to each node in the chain. In conjunction with suitable logic, this structure is the basis of an (M+N)-bit digital-to-analog converter (DAC) or analog-to-digital converter (ADC).

The basic DAC hardware structure is illustrated in Figure 1, where for convenience in drawing there are only 9 resistors in the chain, i.e. N=3. In a typical practical implementation there are 32 or 64 resistors, corresponding to N=5 or N=6. The logic which drives DACl and DAC2 is arranged so that (a) DACl receives only odd codes, (b) DAC2 receives only even codes, (c) the input codes to DACl and DAC2 are chosen from A and A+1, where A is the digital code consisting of the M most-significant bits of the digital input word. The logic which drives the output analog switches is arranged so that the N least-significant bits of the input word are decoded into the output switches counting either upward from the output of OA1 or upward from the output of OA2, depending on which is the lower in voltage.

We assume that the errors in DAC1 and DAC2 are less than a fraction 2^{( -M-1)}of full scale, so that the sequence of analog levels provided alternately by DAC1 and DAC2 is monotonic. The resistor chain then creates an inherently monotonic interpolation between the levels provided alternately by DACl and DAC2, with no discontinuity at all. at- the transition point where the tap point on the resistor chain changes from "full house" to zero and the output of DAC1 or DAC2 changes its value. Previously described methods of interpolating between the levels of a DAC have an inherent discontinuity at this point which leads to loss of monotonicity if the resistor values have errors corresponding to more than 2 of full scale. Although the above discussion has been in terms of the minimum requirements for monotonicity, in practice these requirements are likely to be greatly exceeded: in a typical implementation DACl and DAC2 may each consist of the 8 most significant bits of a nominally 14-bit DAC, and the resistors in the chain may have better than 1% accuracy.

In its applications as a method of concerting data from digital to analog form, the new system offers major advantages in those applications where the specification of differential linearity is far more stringent, expressed as a fraction of full scale, than the specification of absolute accuracy. (In this context the requirement of monotonicity is seen as a specification of differential linearity error equal to less than 0.5 least-significant bit.) These applications, where the error specification includes a "percentage of reading" added to the "percentage of full scale" but where the incremental steps are required to be reasonably uniform, are commonly occurring ones in the fields of high-resolution instrumentation and control. This situation has been obscured by the fact that conventional DAC implementations require to establish an unnecessarily high degree of absolute accuracy in their resistor networks in order to obtain an acceptable value of differential linearity. In the context of analog-to-digital conversion, it is obvious that the DAC structure already discussed, when connected to a comparator and incorporated in a feedback loop with successive-approximation logic or other appropriate logic, offers the same advantages in terms of differential linearity as it does when acting alone as a converter of digital data. However, it also offers special advantages in the area of very high-speed conversion, where the speed of a flash converter is required with resolution greater than that which (for reasons both of complexity and of comparator offset) can practically be obtained from a single flash converter. In the past, this problem has been dealt with by means of a two-stage flash converter, the output of the first converter providing the most significant part of the conversion and being fed into a highly accurate DAC the output of which is subtracted from the analog input signal to provide the input to the second flash converter. The major disadvantage of this method is that it is not inherently monotonic, i.e. the monotonicity depends critically on the matching of resistor values.

Figure 2 shows how the hardware of Figure 1, with comparators replacing the analog switches, can be used to implement a "double-flash" converter which is inherently monotonic apart from the effects of comparator offsets (which can in practice be made negligible). The input signal from a sample-hold is applied through resistors R1 and R2 to operational amplifiers OA1 and OA2, and also to a conventional flash converter, the output from which is fed to DAC1 or DAC2 depending on whether it is odd or even. The other DAC is given a code one least-significant bit greater than the output of the flash converter. The next step in the conversion is to check the outputs of the upper and lower comparators (i.e. the comparators attached to the outputs of OA1 and OA2); if these are both asserted or both non-asserted then an increment or decrement equal to 2 least-significant bits is made to the input of DAC1 or DAC2. When the output of the top comparator is not the output of the lowest comparator, the most-significant part of the output word is the lower of the codes at the inputs of DAC1 and DAC2, and the least-significant part of the output word is obtained by encoding the number of asserted comparators in the chain. Referring to Figure 3, the main operating DACs are DACl and DAC2. These are required to have a much higher degree of acuracy than that corresponding to their precision, and accordingly are shown in the diagram in conjunction with error-correcting DACs, DAC1A and DAC2A, which obtain their input from error table stored in non-volatile memory. The DAC outputs are fed into the summing junctions of operational amplifiers OA1 and OA2, where they counteract the effect of the input current caused to flow in resistors R1 and R2 by the analog inputr voltage. The resistor values are typically chosen in such a way that a change of 1 least-significant bit (LSB) in the digital input to DAC1 or DAC2 will cause a substantial swing at the output of OA1 or OA2, say 5 or 10 volt. The control logic operates in such a way that, for any given value of the analog input voltage, the outputs of OA1 and OA2 have opposite polarity with respect to ground and there is no more than 1 LSB difference between the digital inputs to DAC2 and DAC1. Under these conditions some of the comparators are asserted and some are not, and the overall digital output is made up of two words, the more significant word being the digital input to DAC1 or DAC2 (whichever is lower) and the less significant word representing the number of asserted comparators.

While the state of the comparators does in principle provide enough information to enable the control logic to find the correct digital inmputs for DAC1 and DAC2 by a successive-approxiraation routine, this procedure is for many purposes unacceptably slow and the figure shows a flash converter connected to the analog input voltage. This finds the correct value within 1 LSB, after which the control logic examines the state of the comparators to determine whether an increment or decrement of 1 LSB is required. It is now necessary to describe a feature of the control logic which is essential to the achievement of good differential linearity. It has already been stated that the logic ensures that, for any given value of the analog input, the outputs of OA1 and OA2 are of opposite polarity with respect to ground while at the same time the digital inputs to DAC1 and DAC2 differ by exactly 1 LSB. There is a third requirement (RULE 3) that has not yet been mentioned, and that is that certain codes are not allowed at the digital inputs to DAC1 and DAC2 according to the rule that NO CODE IS ALLOWED AT DACl WHICH IS ALSO ALLOWED AT DAC2. In conjunction with the other constraints, this means that one of the DACs is allowed only even codes while the other DAC is allowed only odd codes.

In order to understand the effect of RULE 3 we may consider the effect of an analog input voltage which is steadily increasing with time (ramp input). As with any interpolation scheme, we think in terms of major and minor transitions: in this case the major transition corresponds to a change in the inputs to the DACs, while the minor transition is a change in the output word of the comparator array. Interpolation schemes usually fail because of a mismatch between the last minor transition and the resulting major transition. However, the implementation of RULE 3 means that when a major transition occurs, the level primarily responsible for the output (i.e. the operational amplifier output nearest to zero) does not change at all, so that no discontinuity occurs.

There is an alternative way of implementing the new principle, in which the analog input signal is fed not into the summing junctions of the operational amplifiers but into the common input to the comparators. On the diagram, this implementation would be represented by removing resistors R1 and R2, and changing the key to read "comparator with one input connected to analog input voltage" where it now reads "comparator with one input grounded". Obviously the operational amplifier feedback resistors would now need to have changed values. While this alternative configuration is inferior to the one described above for the applications currently being envisaged, there may be applications in which it is to be preferred. Also, if the comparators in the diagram are replaced by analog switches (analog transmission gates) connected to an analog output terminal, and the analog input is removed and the digital output is replaced by a digital input, with obvious modifications the diagram describes a DAC with a high degree of differential linearity.

Claims

1. A digital-to-analogue converter (DAC) comprising means for splitting a digital number to be converted into a more significant part and a less significant part, twoDAC means, a resistive chain connected between the outputs of the said DAC means and having 2 nodes (where the less significant part has N digits), switches between each node and common output terminal, means for supplying the DAC means with the digit of the more significant part (of value A) and the digital value (A+l) respectively, and means for closing the switch at that node numbered from the DAC means to which the value A is fed corresponding to the value of the less significant part.

2. The converter as claimed in Claim 1 in which the DAC means are current output devices and operational amplifiers are connected to the respective outputs thereof to provide output voltages to the opposite ends of the resistive chain corresponding to the digital values of the inputs to the respective DAC means.

3. The converter as claimed in either one of the preceeding claims in which when A is odd it is supplied to one of the said DAC means and when A is even it is supplied to the other of the DAC means.

4. An anologue-to-digital converter (ADC) comprising two DAC means, a resistive chain connected between the outputs of the said DAC means, coraparitors connected to each node of the siad chain and asserted when the voltage at that node is above a reference level so that the asserted comparitors provide the less significant part of the output signal, means for supplying the input signal to be converted to a flash-type ACD means the output of which comprises the more significant part of the output signal and to both ends of the resistive chain, and means for supplying the DAC means with the output of the said ADC means (of value A) and the digital value (A+1) respectively.

5. The converter as cliaraed in Claim 4 in which the DAC means are current output devices and operational amplifiers are connected to the respective outputs thereof to provide output voltages to the opposite ends of the resistive chain corresponding to the digital values of the inputs to the DAC means.

6. The converter as claimed in Claim 5 in which the input signal is supplied to the inputs of the operational amplifiers through respective resistors.

7. The converter as claimed in any one of Claims 4 to 6 in which when A if od it is supplied to one of the said DAC means and when A is even it is supplied to the other of the said DAC means.

8. The converter as claimed in any one of Claims 4 to 7 in which control logic means is provided at the output oof the saidd ADC means to provide respective inputs to the DAC means which cause the voltages at opposite ends of the resistive chain to be respectively above and below said reference level.

9. The converter as claimed in any one of Claims 4 to 8 in which two auxiliary error-correcting DAC means are provided each associated with a respective one of the said DAC means and the outputs of which are added to the outputs of the said DAC means.

10. The converter as claimed in Claim 9 in which respective memory means each containing error tables are associated with each auxiliary DAC means to provide inputs thereto in accordance with the values of the inputs to the associated DAC means.

11. A digital-to-analogue converter substantially as described herein with reference to Figure 2 or Figure 3 of the accompanying drawings.