WO1986000443A1 - Processeur de donnees a points d'arret selectifs avec un temps systeme minimum - Google Patents

Processeur de donnees a points d'arret selectifs avec un temps systeme minimum Download PDF

Info

Publication number
WO1986000443A1
WO1986000443A1 PCT/US1985/000672 US8500672W WO8600443A1 WO 1986000443 A1 WO1986000443 A1 WO 1986000443A1 US 8500672 W US8500672 W US 8500672W WO 8600443 A1 WO8600443 A1 WO 8600443A1
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
breakpoint
address
vmdp
data processor
Prior art date
Application number
PCT/US1985/000672
Other languages
English (en)
Inventor
William C. Moyer
John E. Zolnowsky
David S. Mothersole
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Publication of WO1986000443A1 publication Critical patent/WO1986000443A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control

Definitions

  • This invention relates generally to data processors, and more particularly, to a data processor having breakpoint instruction capability ⁇
  • breakpoints are typically used to debug software errors in computers.
  • a breakpoint is literally a point in a software program where a break in the program is taken and data in memory is read to ascertain the status of the program at that point. From this information, a programmer may determine what is happening in the program at selected points. Initially, breakpoints were realized in processing systems utilizing card reading machines by physically inserting a card which was recognized as an illegal instruction at a predetermined location in the program and causing the program to be terminated and the memory contents written. If multiple breakpoints were desired, the illegal instruction card was moved by the programmer to another breakpoint and the program run again.
  • breakpoints When multiple breakpoints were used, the associated hardware increased proportionately.
  • the determination of where breakpoints were taken in a software program was made by closely monitoring the external bus activity and the instructions being executed by the processor. A determination of whether or not to take the breakpoint was made by the external hardware which monitors the number of times a memory location is accessed. After a predetermined number of accesses, the breakpoint is forced to occur.
  • the presence of an on-board instruction cache in a data processor prevents proper monitoring since no external bus activity may occur.
  • an object of the present invention is to provide a data processor having improved breakpoint instruction capability.
  • a further object of the present invention is to provide a data processor having improved selective breakpoint instruction capability with minimal overhead.
  • a data processor adapted to communicate operands with a peripheral device.
  • the data processor has an instruction register for storing an instruction to be executed by the processor.
  • Instruction execution control means execute instructions stored in the instruction register.
  • the instruction execution control means also receive an operand from the peripheral device and selectively store the operand in the instruction register in response to the execution of a breakpoint instruction.
  • the breakpoint instruction may be selectively chosen in a repetitive portion of a program without repetitively effecting an interrupt handler.
  • FIG. 1 is a block diagram of a virtual memory data processing system having the virtual memory data processor of the present invention
  • FIG. 2 is a block diagram of the virtual memory data processor of FIG. 1;
  • FIG. 3 is block diagram of the execution unit of the virtual memory data processor of FIG. 2;
  • FIG. 4 is a block diagram of the high section of the execution unit of FIG. 3;
  • FIG. 5 is a block diagram of the low section of the execution unit of FIG. 3;
  • FIG. 6 is a block diagram of the data section of the execution unit of FIG. 3;
  • FIG. 7 is a block diagram illustrating the relationship of the field translation unit of the virtual memory data processor of FIG. 2 to other functional units therein;
  • FIG. 8 is a block diagram illustrating a typical breakpoint control circuit of FIG. 1;
  • FIG. 9. is a flow chart of software micro-instructions which implement a breakpoint instruction.
  • FIG. 1 Shown in FIG. 1 is a virtual memory data processing system 10 wherein logical addresses (LADDR) issued by a virtual memory data processor (VMDP) 12 are mapped by a memory management unit (MM ⁇ ) 14 to a corresponding physical address (PADDR) for output on a physical bus (PBUS) 16.
  • LADDR logical addresses
  • VMDP virtual memory data processor
  • MM ⁇ memory management unit
  • PADDR physical address
  • Predetermined ones of the logical addresses may include breakpoint acknowledge cycles in response to a breakpoint instruction which are coupled to a breakpoint control circuit 17.
  • Breakpoint control circuit 17 selectively implements predetermined breakpoints.
  • An output of breakpoint control circuit 17 is coupled to physical bus 16.
  • the various logical access control signals (LCNTL) provided by VMDP 12 to control the access are converted to appropriately timed physical access control signals (PCNTL) by a modifier unit 18 under the control of MMU 14.
  • LNTL logical access control signals
  • PCNTL physical access control signals
  • memory 20 In response to a particular range of physical addresses (PADDR) , memory 20 will cooperate with an error detection and correction circuit (EDAC) 22 to exchange data (DATA) with VMDP 12 in synchronization with the physical access control signals (PCNTL) on PBUS 16. upon detecting an error in the data, EDAC 22 will either signal a bus error (BERR) or request VMDP 12 to retry (RETRY) the exchange, depending upon the type of error.
  • EDAC error detection and correction circuit
  • mass storage interface 24 In response to a different physical address, mass storage interface 24 will cooperate with VDMP 12 to transfer data to or from mass storage 26. If an error occurs during the transfer, interface 24 may signal a bus error (BERR) or, if appropriate, request a retry (RETRY) .
  • BERR bus error
  • RETRY request a retry
  • a direct memory access controller (DMAC) 28 will accept data from the VMDP 12 defining a data transfer operation. Upon being released to perform the operation, DMAC 28 will use appropriate PCNTL lines to periodically request VMDP 12 to relinquish control of the bus. Upon being granted control of the bus, the DMAC 28 will transfer a block of data within memory 20 or between memory 20 and mass storage 26. If an error is detected during any such transfer by either the EDAC 22 or mass storage interface 24, DMAC 28 will either abort or retry the transfer, depending upon whether BERR or RETRY was signaled.
  • DMAC direct memory access controller
  • MM ⁇ 14 In the event that the MM ⁇ 14 is unable to map a particular logical address (LADDR) into a corresponding physical address (PADDR) , the MM ⁇ 14 will signal an access fault (FAULT).
  • FAULT access fault
  • a watchdog timer 30 may be provided to signal a bus error (BERR) if no physical device has responded to a physical address (PADDR) within a suitable time period relative to the physical access control signals (PCNTL) .
  • BERR bus error
  • OR gates 32 and 34 will respectively activate the BERR and HALT inputs of VMDP 12.
  • VMDP 12 will abort the current bus cycle and, upon the termination of the RETRY signal, retry the cycle.
  • VMDP 12 may be externally controlled by judicious use of a HALT signal.
  • VMDP 12 In response to the activation of only the HALT input thereof via OR gate 34, VMDP 12 will halt at the end of the current bus cycle, and will resume operation only upon the termination of the HALT signal.
  • VMDP 12 In response to the activation of only the BERR input thereof during a processor-controller bus cycle, VMDP 12 will abort the current bus cycle, internally save the contents of the status register, enter the supervisor state, turn off the trace state if on, and generate a bus error vector number. VMDP 12 will then stack into a supervisor stack area in memory 20 a block of information which reflects the current internal context of the processor, and then use the vector number to branch to an error handling portion of the supervisor program. This is the operation VMDP 12 performs in response to a bus error input signal, except for a bus error signal provided by breakpoint control circuit 17 in response to a break point acknowledge cycle generated by VMDP 12, indicating that a breakpoint is to be taken. Bus errors received during a breakpoint acknowledge cycle cause VMDP 12 to begin exception processing for an illegal instruction format as described below.
  • VMDP 12 is identical to the operation of Motorola's MC68000 microprocessor. However, VMDP 12 differs from the MC68000 primarily in the amount of information which is stacked in response to the assertion of BERR.
  • the information stacked by the MC68000 consists of: the saved status register, the current contents of the program counter, the contents of the instruction register which is usually the first word of the currently executing instruction, the logical address which was being accessed by the aborted bus cycle, and the characteristics of the aborted bus cycle, i.e. read/write, instruction/data and function code.
  • VMDP 12 is constructed to stack much more information about the internal machine state.
  • the last instruction thereof will return control of VMDP 12 to the aborted program.
  • the additional stacked information is retrieved and loaded into the appropriate portions of VMDP 12 to restore the state which existed at the time the buss error occurred.
  • the supervisor may choose to perform the request access but utilize a different resource. If the faulted access was a read, the supervisor can store the accessed information in the appropriate location in the stack. To make it appear to the faulted instruction as if the non-existent peripheral had actually responded, the supervisor can set a flag in the stack indicating that the access has already been performed. Just before resuming execution of the faulted instruction, VMDP 12 can check the flag and, if set, can resume instruction execution as if the access had just been successfully completed. Thus, the faulted program will be unaware that the accessed resource is not actually present.
  • VMDP 12 The preferred operation of VMDP 12 will be described with reference to FIG. 2 which illustrates the internal organization of a microprogrammable embodiment of VMDP 12. Since the illustrated form of VMDP 12 is very similar to the Motorola MC68000 microprocessor described in detail in the several U.S. Patents cited hereafter, the common operational aspects will be described rather broadly. Once a general understanding of the internal architecture of VMDP 12 is established, the discussion will focus on the unique aspects which distinguish VMDP 12 from the MC68000,, and enable the former to support virtual memory.
  • the VMDP 12 is a pipelined, microprogrammed data processor.
  • each instruction is typically fetched during the execution of the preceding instruction, and the interpretation of the fetched instruction usually begins before the end of the preceding instruction.
  • each instruction is executed as a sequence of microinstructions which perform small pieces of the operation defined by the instruction. If desired, user instructions may be thought of as microinstructions.
  • each microinstruction comprises a microword which controls microinstruction sequencing and function code generation, and a corresponding nanoword- which controls the actual routing of information between functional units and the actuation of special function units within VMDP 12.
  • a prefetch microinstruction will be executed.
  • the microword portion thereof will, upon being loaded from micro ROM 36 into micro ROM output latch 38, enable function code buffers 40 to output a function code (FC) portion of the logical address (LADDR) indicating an instruction cycle.
  • FC function code
  • LADDR logical address
  • the corresponding nanoword requests bus controller 46 to perform an instruction fetch bus cycle, and instructs execution unit 48 to provide the logical address of the first word of the next instruction to address buffers 50.
  • bus controller 46 Upon obtaining control of the PBUS 16, bus controller 46 will enable address buffers 50 to output the address portion of the logical address (LADDR) .
  • bus controller 46 will provide appropriate data strobes (some of the LCNTL singals) to activate memory 20.
  • bus controller 46 enables instruction register capture (IRC) 52 to input the first word of the next instruction from PBUS 16.
  • IRC instruction register capture
  • another microinstruction will be executed to transfer the first word of the next instruction from IRC 52 into instruction register (IR) 54, and to load the next word from memory 20 into IRC 52,.
  • the word in IRC 52 may be immediate data, the address of an operand, or the first word of a subsequent instruction.
  • VMDP 12 executes a breakpoint acknowledge cycle and has the ability to selectively update IR 54 from data received during the breakpoint acknowledge bus cycle.
  • external breakpoint control hardware provides an instruction opcode. This data is then used as the instruction to be executed, is loaded into IR 54, and is decoded by an address 1 decoder 56 and an illegal instruction decoder 58 as described below. If the breakpoint is desired to be recognized, the external hardware provides no data, and simply asserts the BERR signal.
  • address 1 decoder 56 begins decoding certain control fields in the instruction to determine the micro address of the first microinstruction in the initial microsequence of the particular instruction in IR 54.
  • illegal instruction decoder 58 will begin examining the format of the instruction in IR 54. If the format is determined to be incorrect, illegal instruction decoder 58 will provide the micro address of the first microinstruction of an illegal instruction microsequence. In response to the format error, exception logic 60 will force multiplexor 62 to substitute the micro address provided by illegal instruction decoder 58 for the micro address provided by address 1 decoder 56.
  • the microword portion thereof may enable multiplexor 62 to provide to an appropriate micro address to micro address latch 64, while the nanoword portion thereof enables instruction register decoder (IRD) 66 to load the first word of the next instruction from IR 54.
  • instruction register decoder ILD
  • micro ROM 36 Upon the selected micro address being loaded into micro address latch 64, micro ROM 36 will output a respective microword to micro ROM output latch 38 and nano ROM 42 will output a corresponding nanoword to nano ROM output latch 44.
  • micro ROM output latch 38 specifies the micro address of the next microinstruction to be executed, while another portion determines which of the alternative micro addresses will be selected by multiplexor 62 for input to micro address latch 64.
  • more than one microsequence must be executed to accomplish the specified operation. These tasks, such as indirect address resolution, are generally specified using additional control fields within the instruction.
  • the micro addresses of the first microinstructions for these additional microsequences are developed by address 2/3 decoder 68 using control information in IR 54.
  • the first microsequence will typically perform some preparatory task and then enable multiplexor 62- to select the micro address of the microsequence which will perform the actual operation as developed by the address 3 portion of address 2/3 decoder 68.
  • the first microsequence will perform the first preparatory task and then will enable multiplexor 62 to select the micro address of the next preparatory microsequence as devleoped by the address 2 portion of address 2/3 decoder 68.
  • the second microsequence Upon performing this additional preparatory task, the second microsequence then enables multiplexor 62 to select the micro address of the microsequence which will perform the actual operation as developed by the address 3 " portion of address 2/3 decoder 68. In any event, the last microinstruction in the last microsequence of each instruction will enable multiplexor 62 to select the micro address of the first microinstruction of the next instruction as developed by address 1 decoder 56. In this manner, execution of each instruction will proceed through an appropriate sequence of microinstructions. A more thorough explanation of the micro address sequence selection mechanism is given in U.S. Patent No. 4,342,078 entitled "Instruction Register Sequence Decoder for Microprogrammed Data Processor" issued 27 July 1982 to Tredennick et al.
  • the nanowords which are loaded into nano ROM output latch 44 indirectly control the routing of operands into and, if necessary, between the several registers in the execution unit 48 by exercising control over register control (high) 70 and register control (low and data) 72.
  • the nanoword enables field translation unit 74 to extract particular bit fields from the instruction in IRD 66 for input to the execution 48.
  • the nanowords also indrectly control effective address calculations and actual operand calculations within the execution unit 48 by exercising control over AU control 76 and ALU control 78.
  • the nanowords enable ALU control 78 to store into status register SR the condition codes which result from each operand calculation by execution unit 48.
  • ALU control 78 is given in U.S. Patent No. 4,312,034 entitled "ALU and Condition Code Control unit for Data Processor” issued 19 January 1982 to Gunter et al. As can be seen in FIG. 3, the execution unit 48 in
  • VMDP 12 like the execution unit in the MC68000, comprises a high section 48A, a low section 48B, and a data section
  • execution unit 48 is so similar to the execution unit of the MC68000 as described in U.S. Patent No. 4,296,469, the common functional units will be described only briefly, followed by a more detailed description of the new elements which allow VMDP 12 to support virtual memory.
  • the high section 48A is comprised primarily of a set of nine high address registers A0H-A7 ⁇ for storing the most significant 16 bits of 32 bit address operands, a set of eight high data registers D0H-D7H for storing the most significant 16 bits of 32 bit data operands, a temporary high address register ATH, a temporary high data register DTH, an arithmetic unit high
  • AUH for performing arithmetic calculations on operands provided on the high section of address and data buses 80 and 82
  • a sign extension circuit 84 for allowing 32 bit operations on 16 bit operands, and the most significant 16 bits of the program counter PCH and address output buffers
  • the low section 48B is comprised primarily of a set of nine low address registers AOL-A7'L for storing the least significant 16 bits of 32 bit address operands, an arithmetic unit low AUL for performing arithmetic calculations on operands provided on the low section of address and data buses 80 and 82, a priority encoder register PER used in multi-register move operations, and the least significant 16 bits of the program counter PCL and address output buffers AOBL.
  • the data section 48C is comprised primarily of a set of eight low data registers D0L-D7L for storing 16 bit operands which may be the least significant 16 bits of 32 bit data operands, a decoder register DCR for generating 16 bit operand masks, an arithmetic and logic unit ALU for performing arithmetic and logical operations on operands provided on the data section of address and data buses 80 and 82, an ALU buffer register ALUB, an ALU extenstion register ALUE for multiword shift operations, and multiplexed data input and output buffers DBIN and DOB, respectively.
  • VMDP 12 has been described in terms of the hardware features which are common with the MC68000. VMDP 12 also responds to error conditions in a manner somewhat similar to the MC68000. Recall that MMU 14 will signal an address error by generating a FAULT signal, while the other peripheral circuits report bus errors by issuing a BERR signal. In either event, VMDP 12 will receive a BERR signal via OR gate 32. In response to the BERR signal, bus controller 46 will notify exception logic 60 of the error and then orderly terminate the faulty bus cycle. Exception logic 60 then provides multiplexor 62 with the micro address of the bus error exception handler microsequence to be forced into the micro address latch 64. At this point, the MC68000 would simply load the micro address provided by exception logic 60 into micro address latch 64 and control would pass to the exception handler microsequence to stack out the following information:
  • VMDP 12 internally saves additional information about the current state thereof, before loading the micro address of the exception handler microsequence. To accomplish this, VMDP 12 has several additional registers for capturing the necessary state information, and some additional access paths are provided to certain existing registers. For example, as shown in FIG. 2, VMDP 12 has a micro address capture latch 86 for storing the micro address in the micro address latch 64 at unit 74, a special status word internal (SSWI) register 88 is provided as shown in FIG. 7 to save the following:
  • SSWI special status word internal
  • R/W Read/Write R/W
  • FC Function Code for faulted access; now saves the following additional information: IF nanoROM bit NIRC (instruction fetch to IRC);
  • VMDP 12 loads the micro address provided by exception logic 60 into micro address latch 64 and begins executing the exception handler microsequence.
  • the initial microinstructions must clear the address calculation and output paths in execution unit 48 so that the stack address may be safely calculated and provided to MMU 14. Accordingly, several additional registers are provided in the execution unit 48 to store the existing address, data and control information: in the high section 48A shown in FIG. 4, three virtual address temporary high registers VAT1H-VAT3H are provided to facilitate capture of the output of AUH and the address in AOBH; in the low section 48B shown in FIG.
  • the exception handler microsequence then vectors to the error recovery routine in the supervisor program.
  • the supervisor program can determine the cause of the fault, and if appropriate, attempt to fix the problem. For example, an access to a logical address which has no corresponding physical address may simply require that a block of program/data be loaded from mass storage 26 into memory 20. Of course, other processing may also be performed before the faulted program is restarted.
  • the supervisor program in both the MC68000 and VMDP 12 executed a return from exception (RTE) instruction.
  • RTE exception
  • this instruction will be executed only if the exception was of the type which occurred on instruction boundaries.
  • the microsequence for this instruction could simply reload the status register SR and prog ' ram counter PCH-PCL from the stack, and then pass control to the instruction whose address is in the program counter.
  • this instruction is also used to return from access faults which typically occur during execution of an instruction. Accordingly, the initial microinstructions in this microsequence fetch the VOR word from the stack to determine the stack frame format.
  • the microsequence will proceed as in the MC68000. If, on the other hand, the long format is indicated, several other words are fetched from the stack to assure that the full frame is available in memory. If the frame format is neither short nor long, VMDP 12 will assume that the stack frame is either incorrect or was generated by an incompatible type of processor and will transfer control to a stack frame format error exception handler microsequence. If another fault is generated at this stage, indicating that a portion of the stack frame has been inadvertantly swapped out of memory 20, the same access fault handling procedure will be used to retrieve the rest of the stack.
  • the micro address contained in the micro address capture latch 86 is coupled to the FTU via a portion of the BC bus, as shown in FIG. 7.
  • revision validator 92 impresses on the available portion of the BC bus a code which uniquely indentifies the version of the microcode contained within VMDP 12.
  • This combined word is subsequently transferred into DOB in the data section 48C of the execution unit 48 for output via data buffers 94 to memory 20.
  • the MAL word is fetched from the stack and loaded into both IRC 52 and DBIN in the data section 48C of the execution unit 48.
  • MAL is transferred to FTU and coupled to the BC bus.
  • Revision validator 92 then .compares the version number portion of MAL to the internal version number. If they are not the same, revision validator 92 will signal branch control unit 96 to transfer control to the stack frame format exception handler microsequence. Otherwise, revision validator 92 will simply allow the microsequence to load the micro address portion of MAL into address 4 latch 98.
  • the microsequence will enter a critical phase where any fault will be considered a double fault and VMDP 12 will terminate processing until externally reset.
  • the rest of the information in the stack is fetched and either reloaded into the original locations or into the several temporary registers.
  • the contents of the micro address latch 64 which were captured by the micro address capture latch 86 will be loaded into address 4 latch 98.
  • the contents of AUH-AUL and SR restored from the temporary registers.
  • the last microinstruction in this instruction continuation microsequence restores the contents of AOBH, AOBL, FTU, and DOB, signals bus controller 46 to restart the faulted bus cycle using the information in SSWB 90, and requests multiplexor 62 to select the micro address in address 4 latch 98.
  • bus controller 46 will respond to the restart signal provided by the last microinstruction of the instruction continuation microsequence by examining a rerun bit RR in SSWB 90. If the supervisor has not set the RR bit in the stack, the bus controller 46 will proceed to rerun the faulted bus cycle under control of the other information in SSWB 90, and then signal exception logic 60 when the cycle has been successfully completed. If, on the other hand, the supervisor has set the RR bit, the bus controller 46 will not rerun the bus cycle, but will simply signal exception logic 60 that the cycle is complete. In response to the cycle complete signal, exception logic 60 will enable multiplexor 62 to output the micro address in address 4 latch 98 to micro address latch 64. The faulted instruction will then resume control of VMDP 12 as if the fault had never occurred.
  • VMDP 12 unlike the MC68000, is also capable of creating the illusion that the currently executing user program is executing in the supervisor state. This has been achieved by making all instructions which access the supervisor/user bit in status register SR into privileged instructions. Thus, whenever an attempt is made by the user program to modify or even read the supervisor/user bit, control will automatically revert to the supervisor. The supervisor will then be able to prepare and return a suitably modified image of SR to the user program. The user program, being insulated from the true SR, can be pretend that it is the supervisor. With the help of the true supervisor, this pseudo supervisor can control the execution of other user program. This capability to control accesses to both real and non-existent system resources from user programs, whether true user or pseudo supervisor, enables the user VMDP 12 to create a virtual machine environment.
  • FIG. 8 Shown in FIG. 8 is a block diagram of breakpoint control circuit 17 which functions to decode the presence of a breakpoint acknowledge cycle which is internally generated by VMDP 12 during execution of a breakpoint instruction.
  • the breakpoint instruction replaces the normal instruction opcode at the location in memory where a breakpoint is desired to be set.
  • Logical address signals, LADDR some of which indicate a breakpoint acknowledge cycle, are coupled to an input of a decoder 102. Due to the existence "of an on-board instruction cache containing breakpoint information in VMDP 12, the number of times a memory location is physically accessed may not be monitored by hardware external to VMDP 12 for purposes of identifying when a breakpoint is to be taken.
  • An output of decoder 102 couples a breakpoint acknowledge cycle signal to a first input of a counter 104 and a first input of a control circuit 106.
  • a counter read/write select signal is coupled from a second output of decoder 102 to both a second input of counter 104 and a second input of control circuit 106.
  • a third output of decoder 102 provides an opcode buffer read/write select signal to both a third input of control circuit 106 and to a first input of an opcode buffer circuit 108.
  • An output of counter 104 representing a signal indicating that a count is completed is coupled to a fourth input of control circuit 106.
  • a first output of control circuit 106 provides a data acknowledge signal, DSACK.
  • a second output of control circuit 106 provides a bus error signal, BERR, and a third output of control circuit 106 provides a drive opcode signal to a second input of opcode buffer circuit 108.
  • a multidirectional bus 110 is coupled between PBUS 16, a third input of opcode buffer 108 and a third input of counter 104.
  • an acknowledge cycle signal is coupled to counter 104 and control circuit 106.
  • the decoder breakpoint acknowledge cycle signal is provided by VMDP 12 in the form of a predetermined function code having a value such as "111" and predetermined address bits having predetermined values such as "0000".
  • Counter 104 is set to a predetermined count so that a breakpoint may be taken at a predetermined time. As a result, breakpoints may be selectively made after a predetermined number of repetitions of a portion of a program being executed by
  • control circuit 106 If counter 104 has not counted to the predetermined count, control circuit 106 provides a data acknowledge signal DSACK and a replacement instruction opcode to VMDP 12 rather than a bus error signal BERR.
  • VMDP 12 initializes counter 104 and control circuit 106 ⁇ via decoder 102 and PBUS 16. In this way, counter 104 determines the number of times a breakpoint will be ignored before being executed. Similarly, VMDP 12 initializes opcode buffer circuit 108 via PBUS 16 and an opcode buffer read/write select signal generated by decoder 102. An opcode representing the instruction which is being replaced by the breakpoint instruction is initially written into opcode buffer 108 in response to the read/write signal. When control circuit 106 provides a "drive opcode out" signal to opcode buffer 108, buffer 108 reads out the predetermined opcode to VMDP 12 via PBUS 16.
  • the opcode is associated with the instruction which VMDP 12 would be normally executing in the absence of a breakpoint instruction.
  • control circuit 106 After counter 104 has counted to the predetermined count desired for a breakpoint to occur, control circuit 106 provides a bus error signal which is coupled to OR gate 32 of FIG. 1 and effects an interrupt to occur in the manner previously described. An exception handler is effected and the breakpoint is processed.
  • FIG. 9 Shown in FIG. 9 is an instruction flow chart illustrating the breakpoint operation in micro-instruction form. In this manner, selective breakpoint operation is achieved without entering an exception handler every time a breakpoint instruction is encountered in repetitive iterations of a program being processed by a data processing system.

Abstract

Processeur de données (12) qui communique avec une unité périphérique (17) et qui place sélectivement des points d'arrêt avec un temps système minimum. Le processeur de données (12) utilise un registre d'instructions (52, 54, 66) pour mémoriser des instructions à exécuter. Des dispositifs de commande (36, 42, 48, 50, 70, 72) communiquent avec l'unité périphérique (17) afin de placer sélectivement un point d'arrêt dans un programme logiciel. Lorsque des répetitions du point d'arrêt sont rencontrées, un programme de gestion d'exceptions (60, 36, 42) n'est exécuté qu'au point d'arrêt voulu afin de réduire le temps système au minimum. Une partie de commande (36, 42) du processeur (12) reçoit sélectivement une instruction de renvoi et enregistre l'instruction de renvoi dans le registre d'instructions (52, 54, 66).
PCT/US1985/000672 1984-06-27 1985-04-16 Processeur de donnees a points d'arret selectifs avec un temps systeme minimum WO1986000443A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62506584A 1984-06-27 1984-06-27
US625,065 1984-06-27

Publications (1)

Publication Number Publication Date
WO1986000443A1 true WO1986000443A1 (fr) 1986-01-16

Family

ID=24504429

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1985/000672 WO1986000443A1 (fr) 1984-06-27 1985-04-16 Processeur de donnees a points d'arret selectifs avec un temps systeme minimum

Country Status (3)

Country Link
EP (1) EP0188437A1 (fr)
CA (1) CA1223079A (fr)
WO (1) WO1986000443A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0514042A1 (fr) * 1991-05-13 1992-11-19 International Business Machines Corporation Dispositif de point d'arrêt pour un système de traitement de données

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3731283A (en) * 1971-04-13 1973-05-01 L Carlson Digital computer incorporating base relative addressing of instructions
US3904860A (en) * 1972-12-14 1975-09-09 Siemens Ag Method for diagnosing the condition of data processors
US3937938A (en) * 1974-06-19 1976-02-10 Action Communication Systems, Inc. Method and apparatus for assisting in debugging of a digital computer program
US4041471A (en) * 1975-04-14 1977-08-09 Scientific Micro Systems, Inc. Data processing system including a plurality of programmed machines and particularly including a supervisor machine and an object machine
US4080650A (en) * 1976-07-28 1978-03-21 Bell Telephone Laboratories, Incorporated Facilitating return from an on-line debugging program to a target program breakpoint
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus
US4493027A (en) * 1981-05-22 1985-01-08 Data General Corporation Method of performing a call operation in a digital data processing system having microcode call and return operations

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3731283A (en) * 1971-04-13 1973-05-01 L Carlson Digital computer incorporating base relative addressing of instructions
US3904860A (en) * 1972-12-14 1975-09-09 Siemens Ag Method for diagnosing the condition of data processors
US3937938A (en) * 1974-06-19 1976-02-10 Action Communication Systems, Inc. Method and apparatus for assisting in debugging of a digital computer program
US4041471A (en) * 1975-04-14 1977-08-09 Scientific Micro Systems, Inc. Data processing system including a plurality of programmed machines and particularly including a supervisor machine and an object machine
US4080650A (en) * 1976-07-28 1978-03-21 Bell Telephone Laboratories, Incorporated Facilitating return from an on-line debugging program to a target program breakpoint
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus
US4493027A (en) * 1981-05-22 1985-01-08 Data General Corporation Method of performing a call operation in a digital data processing system having microcode call and return operations

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0514042A1 (fr) * 1991-05-13 1992-11-19 International Business Machines Corporation Dispositif de point d'arrêt pour un système de traitement de données

Also Published As

Publication number Publication date
CA1223079A (fr) 1987-06-16
EP0188437A1 (fr) 1986-07-30

Similar Documents

Publication Publication Date Title
US4635193A (en) Data processor having selective breakpoint capability with minimal overhead
US4566063A (en) Data processor which can repeat the execution of instruction loops with minimal instruction fetches
US4524415A (en) Virtual machine data processor
US4493035A (en) Data processor version validation
US4488228A (en) Virtual memory data processor
US4584640A (en) Method and apparatus for a compare and swap instruction
US4710866A (en) Method and apparatus for validating prefetched instruction
US5119483A (en) Application of state silos for recovery from memory management exceptions
US4933941A (en) Apparatus and method for testing the operation of a central processing unit of a data processing system
JPH02232737A (ja) パイプライン方式コンピューターシステムにおいてエラーを検出し訂正する方法及び装置
US4740889A (en) Cache disable for a data processor
US5003458A (en) Suspended instruction restart processing system based on a checkpoint microprogram address
CA1222323A (fr) Methode et appareil de verification de valeurs limitees signees et non signees
JP3707581B2 (ja) 自己整合スタック・ポインタを有するデータ処理システムおよびその方法
US4757445A (en) Method and apparatus for validating prefetched instruction
US5146569A (en) System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension
EP0509558B1 (fr) Système de traitement d'information avec moyen d'assistance répondant à des commandes de système globales
JPS6022772B2 (ja) 擬似障害発生制御方式
US4559596A (en) History memory control system
US4742449A (en) Microsequencer for a data processing system using a unique trap handling technique
CA1223079A (fr) Processeur de donnees a point d'arret reglable pour minimiser le temps systeme
WO1988007239A1 (fr) Appareil et procede servant a la synchronisation d'exceptions arithmetiques dans des unites d'execution en parallele a traitement ''pipeline''
US5243601A (en) Apparatus and method for detecting a runaway firmware control unit
CA1233271A (fr) Circuit d'invalidation d'antememoire pour processeur de donnees
EP0297890B1 (fr) Dispositif et procédé de signalisation de condition induite par des données

Legal Events

Date Code Title Description
AK Designated states

Designated state(s): JP KR

AL Designated countries for regional patents

Designated state(s): DE FR GB IT NL