WO1984003164A1

WO1984003164A1 - Video graphics system

Info

Publication number: WO1984003164A1
Application number: PCT/GB1984/000023
Authority: WO
Inventors: Brian Sibbald
Original assignee: Brian Sibbald
Priority date: 1983-02-05
Filing date: 1984-01-30
Publication date: 1984-08-16
Also published as: EP0138829A1; GB8303240D0

Abstract

The invention allows digital information to control a graphics display in which the reproduction of sloping and curved lines is enhanced. Video data from memory (12) is processed by circuitry (14) and serialiser (16) to form a serial video signal. Each pixel can be moved by a fraction of a pixel width by delaying the shift signal to serialiser (16) under the control of attribute data for that pixel stored in memory (12). One form of delay means is the tapped delay line (24) and multiplexer (26) shown.

Description

"Video Graphics System"

This invention relates to graphic video display apparatus, particularly but not exclusively for use in such fields as computer output. There are many known systems where digital information is read from memory and used to produce a graphic display on a raster-scanned c.r.t. Such systems are commonly based on defining the screen area as an array of picture elements (pixels) in some such standard as 256 lines x 256 pixels each. However, the quality of such a display is limited, especially in producing oblique lines and curved lines, since a visibly staircase-shaped line is produced. The quality can of course be improved by increasing the number of pixels per line, but only at the expense of a considerable increase in memory, and in any event this approach is limited by the switching speeds and video bandwidths available.

An object of the present invention is to provide an improved video graphics system which provides improved display quality in a simpler and cheaper manner.

According to the present invention a video display apparatus includes a video memory for video data, a serialiser arranged to translate video data from the memory into serial video signals defining serial pixels to be displayed, attribute memory means storing attribute data relating to each item of video data in the video memory, and shift means controlled by the attribute memory means to shift individual pixels on the display by a fraction of a pixel width defined by the stored attribute data for that pixel. The serialiser may suitably comprise a shift register connected to be parallel-loaded with data for a plurality of pixels (e.g. one screen line) , and the shift means may comprise means for controllably delaying shift pulses for said register.

An embodiment of the invention will now be described, by way of example only, with reference to 5 the drawings, in which:-

Fig. 1 illustrates a set of oblique lines formed by prior art techniques;

Fig. 2 similarly illustrates a set of oblique lines produced by the present invention; and _Q Fig. 3 is a block diagram of one system embodying the invention.

As shown in Fig. 1, in known systems using a standard pixel size 10, lines other than vertical and horizontal must be produced by best fit of standard __ζ size pixels at fixed locations, producing a jagged or staircase effect. The system of the present invention provides a much closer approximation to the desired line, as shown in Fig. 2, using the same size of pixel by virtue of shifting selected pixels horizontally in o increments (in this embodiment) of one-eighth of a pixel as will now be described.

Referring to Fig. 3, a memory 12 holds both video and attribute data. As is well known per se, the video data defines one or more desired *- display fields, for example as one addressable byte per pixel of the field, which can be called up by known video circuitry 14, converted to serial form by serialiser 16 and supplied as a video signal at 18 to the display, the memory 12 and video circuitry 0 14 being synchronised by clock circuit 20. Typically ^• the serialiser 16 is a shift register which can receive one video line of data in parallel and output this pixel by pixel in response to a video shift clock signal. In known systems, such video shift clock signal 5 would come directly from clock circuit 20.

The attribute data stored in memory 12 comprises one data word associated with each pixel; in this embodiment the attribute data word is of 3 bits and thus defines 8 digits of attribute. The attribute data is read from memory 12 and applied to a multiplexer 22, which includes circuitry to synchronise each pixel and its offset attribute. Shift clock pulses from the clock circuit 20 are applied to a delay circuit 24 which provides eight outputs at delay times equivalent to one-eighth of a pixel width. The multiplexer 22 acts to select a time delay defined by the attribute and pass this as a selectively delayed video shift clock signal to the serialiser 16. In this way the video data for each pixel can be delayed as defined by the respective attribute data to produce a selected shift on the screen.

This embodiment thus improves horizontal resolution by a factor of 8 but requires only a relatively modest increase in memory capacity.

The delay circuit 24 could suitably comprise a tapped delay line, or simply a tapped chain of shift registers. Other means for producing controlled delay of the video shift clock can readily be conceived. For example, the output of the clock circuit 20 could be supplied in parallel to a number (e.g. eight) of delay circuits having differing delay periods, and the output of one of these gated in response to the attribute data.

Additional circuitry can be employed to simplify the drawing of horizontal lines or the filling in of defined areas of the video image. Since we can offset the video image by fractions of a cell width we could end up with the situation where there is a gap between cells that is a fraction of a cell and therefore result in unsatisfactory video presentation. This problem can be overcome by adding circuitry that results in the last serialized video cell's intensity level (could also include colour) to be maintained until either a new cell is presented or a command is received to resort to normal video. This command could be a special character or attribute or combination and could also include the retrace signal for the video signal thus preventing "wrap-round" if required. The option of maintaining a video level until told to revert could also include:

(a) maintain the last sent cell level & colour; (b) maintain the inverse of the last cell level & colour;

(c) maintain a preset level & colour. Any combination of the above could be offered. The video signal signal path, for this purpose, may include attribute logic as seen at 28 in Fig. 3. By using multiple circuitry the system could be used for colour representations and the fractional offsets if overlaid on different, colours could lead to improved shading. The latter could also be applied to monochrome systems.

The invention thus provides a system which improves display quality with a minimal increase in memory and without any increase in video signal bandwidth.

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Claims

1. A video apparatus having a video memory, for video data, characterised by a serialiser arranged to translate video data from the memory into serial video signals defining serial pixels to be displayed, attribute memory means storing attribute data relating to each item of video data in the video memory, and shift means controlled by the attribute memory means to shift individual pixels on the display by a fraction of a pixel width defined by stored attribute data for that pixel.

2. Apparatus according to claim 1, in which the serialiser comprises a shift register connected to receive in parallel video data for a. plurality of pixels.

3. Apparatus according to claim 2, in which the shift means comprises means for controllably delaying shift pulses for said shift register.

4. Apparatus according to claim 3, in which said controllable delay means comprises a tapped delay circuit whose outputs are connected to a multiplexer to be multiplexed with attribute data.

5. Apparatus according to any preceding claim, including logic means connected to receive the serialiser output and responsive.to the attribute data to modify the serial video signal.

6. Apparatus according to claim 5, in which said logic means is arranged to maintain a predetermined video signal in the time interval between predetermined attribute signals.

7. A method of producing a graphic display from digital data, in which video data defining an array of pixels stored in a memory is read from memory and converted to serial form, characterised by storing attribute data relating to each pixel in a memory, and modifying the serial signal to shift each pixel on the display by a fraction of a pixel width defined by the attribute data for that pixel.

OMPI