WO1984003156A1

WO1984003156A1 - Test module for asynchronous bus

Info

Publication number: WO1984003156A1
Application number: PCT/US1983/001962
Authority: WO
Inventors: Shlomo Pri-Tal
Original assignee: Motorola Inc
Priority date: 1983-02-07
Filing date: 1983-12-12
Publication date: 1984-08-16
Also published as: JPS60500429A; EP0135505A1

Abstract

A test module for troubleshooting and diagnosing an asynchronous microprocessor bus (26) in real time under normal operating conditions. The test module operates in a system environment and at true operating speed until a fault occurs. Once a fault is detected, the circuit will halt the microprocessor and freeze the bus signals at fault detection time. Latches (10, 14, 18, 22) are connected to the asynchronous bus (26) under test and a test bus (28). A comparator (24) connected to the latches compares the data pattern under test to the test pattern, providing a continue signal when the data patterns are identical and a diagnose signal when the data patterns are not equal. The continue signal allows the microprocessors to continue to the next pattern and the diagnose signal initiates a diagnose sequence in the test microprocessor.

Description

-i-

TEST MODULE FOR ASYNCHRONOUS BUS

Background of the Invention

Field of the Invention

This invention relates to a circuit for trouble¬ shooting and diagnosing an asynchronous microprocessor bus.

Background Art

Three types of faults may occur in the asynchronous bus under test: a short, an open, or a short/open. A short occurs when two paths become inadvertantly connected. An open occurs when a path is disrupted. A short/open occurs when one path is disrupted and one side connects with another path.

The previously known method for testing microprocessor busses at true operating speed and in a system environment was by executing machine language routines that stored data patterns in memory devices, and then verifying them to be correct. The device under test included a microprocessor and an asynchronous bus. The testing of the device under test in a system environment was actually accomplished by the device under test itself. During a write cycle, data from the microprocessor was sent on the asynchronous bus to memory devices. During a read cycle, the data was taken from the memory devices. When the read cycle was complete, the data read was verified to be identical to the test pattern that was sent over the bus. However, since the validity of the write transfer was not verified until after the read cycle was completed, a faulty test signal for that cycle would have been removed from the bus. Thus, troubleshooting and diagnosing a faulty device was time consuming, required sophisticated test equipment, and prevented real time probe tests. Furthermore, the device under test, even when malfunctioning, was part of the test apparatus and therefore both controlled the test sequence and determined the validity of the test. In other words, the device under test was testing itself. Also, this previously known method required the device under test to execute a relatively large amount of machine code.

Thus, what is needed is a test module for trouble¬ shooting and diagnosing an asynchronous microprocessor bus that reduces troubleshooting time and cost, while providing for a more comprehensive test in a system environment and at true operating speed.

Summary of the Invention

Accordingly, it is an object of the present invention to provide a test module for troubleshooting and diagnosing an asynchronous microprocessor bus.

Another object of the present invention is to provide a test module for troubleshooting and diagnosing an asynchronous microprocessor bus in a system environment. Yet another object of the present invention is to provide a test module for troubleshooting and diagnosing an asynchronous microprocessor bus at true operating speed until a fault occurs.

Another object of the present invention is to provide a test module for troubleshooting and diagnosing an asynchronous microprocessor bus having a reduced trouble¬ shooting and diagnosing time.

Still another object of the present invention is to provide a test module for troubleshooting and diagnosing an asynchronous microprocessor bus wherein the device under test neither controls nor affects the test sequence.

Another object of the present invention is to provide a test module for troubleshooting and diagnosing an asynchronous microprocessor bus wherein the device under test does not determine the validity of the test. Yet another object of the present invention is to provide a test module for troubleshooting and diagnosing an asynchronous microprocessor bus wherein the validity of each transfer is verified before the transfer is allowed to be completed.

Still another object of the present invention is to provide a test module for troubleshooting and diagnosing an asynchronous microprocessor bus wherein the device under test will not be allowed to terminate faulty cycles, thus freezing the bus signals at fault detection time.

Another object of the present invention is to provide a test module for troubleshooting and diagnosing an asynchronous microprocessor bus wherein the device under test executes a reduced amount of machine code. In carrying out the above and other objects of the present invention in one form, there is provided a test module for testing an asynchronous bus and a first microprocessor having a bit pattern therein comprising a test bus including a test microprocessor having a test pattern therein. A first means is coupled to the test bus for sequentially latching the test pattern. A second means is coupled to the asynchronous bus for sequentially latching the bit pattern. A third means is coupled to the first and second means and to both busses for comparing the bit pattern to the test pattern wherein a continue signal is supplied to both busses when the patterns are identical and a diagnose signal is supplied to the test bus when the patterns are not identical. A fourth means is coupled to the first and second means and both busses for outputting the bit pattern when the diagnose signal is generated.

The above and other objects, features, and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawing.

OMPI Brief Description of the Drawing

The single Figure is a block diagram of a preferred embodiment of the present invention.

Detailed Description of the Invention

Referring to the single Figure, the test module of the present invention in shown which is suitable to be fabricated in monolithic integrated circuit form and includes address bus latches 10, address decoder 12, data bus latches 14, synchronous decoder 16, data latches 18, address decoder 20, fault latches 22 and comparators 24. Asynchronous bus 26 is connected to an asynchronous microprocessor (not shown). Both the asynchronous bus 26 and the asynchronous microprocessor comprise the device under test. Test bus 28 is connected to a test micropro¬ cessor (not shown) and may be either synchronous or asynchronous. Address bus latches 10 are connected to asynchronous bus 26 by address bus 29 for latching the bit pattern on the address bus 29. Data bus latches 14 are connected to asynchronous bus 26 by data bus 34, read/write line 36, and data valid line 38. The read/write line 36 defines the data bus transfer as a read or write cycle. Data valid line 38 signifies that the data on the data bus 34 is valid. Address decoder 12 is connected to asynchronous bus 26 by address bus 29, address valid line 30 and reset line 32. Address decoder 12 is also connected to address bus latches 10 by test address line 11 and to data bus latches 14 by test data line 13. Address decoder 12 will enable either address bus latches 10 or data bus latches 14 for feeding their bit pattern to fault latches 22 and comparators 24. The reset line 32 acts to reset and initiate a system initialization sequence. Data latches 18 are connected to test bus 28 by test data bus 46, write line 48, and test data valid line 40. Data latches 18 are further connected to comparators 24 by test pattern bus 54. Test data bus 46 transfers data from the test bus 28 to data latches 18. Write line 48 enables data latches 18 for receiving the test data.

Fault latches 22 are connected to test bus 28 by read line 60, fault pattern bus 62, and data valid line 64. Fault latches 22 are connected to asynchronous bus 26 by data valid line 38, address valid line 30, and read/write line 36. Fault latches 22 are also connected to address bus latches 10 and data bus latches 14 by pattern under test bus 68. The read signal on read line 60 enables the data to transfer from fault latches 22 to test bus 28. Address decoder 20 is connected to test bus 28 by address bus 56 and test address valid line 58. Address decoder 20 will enable either data latches 18 to latch the test pattern or fault latches 22 to interrogate the faulty pattern under test. Synchronous decoder 16 is connected to test bus 28 by test data valid line 40, to asynchronous bus 26 by data valid line 38 and address valid line 30 and to comparators 24 by compare line 70. A compare signal is generated when test data valid line 40 and data valid line 38 or test data valid line 40 and address valid line 30 are true.

Comparators 24 are connected to address bus latches 10 and data bus latches 14 by pattern under test bus 68. Comparators 24 are connected to test bus 28 by continue line 72 and diagnose line 74 and to asychronous bus 26 by continue line 72. Comparator 24 compares the data from pattern under test bus 68 to the test data from test pattern bus 54. When the data is identical, a continue signal is generated, thus allowing the microprocessor under test and the test microprocessor to continue and compare the next data pattern. When the data is not identical, a diagnose signal is generated that initiates a diagnose

f OMP sequence in the test microprocessor. Since asynchronous bus 26 has not received a continue signal, the faulty cycle will not be completed and the faulty signal on asynchronous bus 26 will be frozen at fault detection time. Asynchronous bus 26 is connected to test bus 28 by reset line 32 for initializing both microprocessors to start the test at the same pattern.

In operation, the bit pattern on the address bus 29 and data bus 34 are latched by address bus latches 10 and data bus latches 14, respectively. Address decoder 12 enables either address bus latches 10 or data bus latches 14 for feeding their pattern to fault latches 22 and comparators 24. The test pattern on the test data bus 46 is latched by data latches 18. Address decoder 20 enables either data latches 18 to latch the test pattern for feeding the pattern to comparators 24, or enabling fault latches 22 to interrogate the faulty pattern under test. When the pattern under test compares with the test pattern a continue signal on line 72 allows the microprocessors to continue and compare the next data pattern. When the patterns do not compare, the diagnose signal on line" 74 initiates a diagnose sequence in the test microprocessor, and since the continue signal is not generated, the faulty cycle will not be completed and the faulty pattern on asynchronous bus 26 will be frozen at fault detection time. Probe tests may then be conducted to determine the reason for the fault.

By now it should be appreciated that there has been provided a test module for troubleshooting and diagnosing an asynchronous microprocessor bus. This module provides for the testing of an asynchronous bus in real time under normal operating conditions. The test module operates in a system environment and at true operating speed until a fault occurs. The module controls the test sequence and determines the validity of the test. The machine code executed by the device under test is reduced.

Claims

1. A test module for testing an asynchronous bus and a first microprocessor having a bit pattern therein, comprising: a test bus including a test microprocessor having a test pattern therein; first means coupled to said test bus for sequentially latching said test pattern; second means coupled to said asynchronous bus for sequentially latching said bit pattern; third means coupled to said asynchronous bus, said test bus, and said first and second means for comparing said bit pattern to said test pattern wherein a continue signal is supplied to said asynchronous bus and said test bus when said test pattern and said bit pattern are substantially identical, and a diagnose signal is supplied to said test bus when said test pattern and said bit pattern are not substantially identical; and fourth means coupled to said first means, said second means, said test bus, and said asynchronous bus for outputting said bit pattern when said diagnose signal is generated.

2. The test module according to claim 1 wherein said second means comprises: a plurality of address latches coupled to said asynchronous bus and said third means; a first plurality of data latches coupled to said asynchronous bus, said third means, and said fourth means; and a first address decoder coupled to said asynchronous bus, said plurality of address latches, and said first plurality of data latches for enabling one of said plurality of address latches and said first plurality of data latches for feeding said bit pattern to said third means and said fourth means.

3. The test module according to claim 2 wherein said first means comprises: a second plurality of data latches coupled to said test bus and said third means; a second address decoder coupled to said test bus, said second plurality of data latches, and said fourth means for enabling one of said second plurality of data latches when said continue signal is generated and said fourth means when said diagnose signal is generated.

4. The test module according to claim 3 wherein said third means comprises: a comparator coupled to said plurality of address latches, said first plurality of data latches, said second plurality of data latches, said asynchronous bus, and said test bus, for supplying said continue signal to said asynchronous bus and said test bus when said bit pattern is substantially identical to said test pattern, and supplying said diagnose signal to said test bus when said bit pattern is not substantially identical to said test pattern; and a synchronous decoder coupled to said asynchronous bus, said test bus, and said comparator, and responsive to a bit pattern valid signal from said asynchronous bus and a test pattern valid signal from said test bus, for supplying a compare signal to said comparator.

5. The test module according to claim 4 wherein said fourth means comprises a plurality of fault latches for latching said bit pattern and feeding said bit pattern to said test bus when said diagnose signal is generated.

6. A method of testing an asynchronous bus and a first microprocessor having a bit pattern comprising the steps of: latching the bit pattern; latching a test pattern from a test bus including a second microprocessor; comparing the bit pattern to the test pattern; generating a continue signal when the bit pattern is substantially identical to the test pattern so that another bit pattern is compared to another test pattern; generating a diagnose signal when the bit pattern is not substantially identical to the test pattern; and outputting the bit pattern when the diagnose signal is generated.