WO1983003933A1

WO1983003933A1 - Logarithmic converter apparatus

Info

Publication number: WO1983003933A1
Application number: PCT/US1983/000624
Authority: WO
Inventors: Jay Mandel
Original assignee: Jay Mandel
Priority date: 1982-04-29
Filing date: 1983-04-29
Publication date: 1983-11-10
Also published as: EP0107721A1

Abstract

An improved logarithmic converter apparatus (100) for analog to digital to analog or both types of conversion including a logarithmic gain controlling network (120) which has stages (222-292) controlled to produce a unity gain or a fixed nonunity gain. Preferably, the stages of the logarithmic gain controlling network are controlled by a plurality of digital input signals and include a plurality of gain controlling stages, connected in series with the gain of each stage being the square or the square root of the gain of the preceding stage.

Description

LOGARITHMIC CONVERTER _.APPARATUS

Technical Field

The present invention relates to electrical signal processing apparatus and more particularly to a digitally controlled logarithmic attenuation network and to logarithmic digital to analog (D/A) converters and analog to digital (A/D) converters which provide a constant relative accuracy. Converters according to the invention, may also be utilized in conjunction with external circuitry such as known linear D/A or A/D conversion circuits to provide logarithmic (log) and antilogarithmic (antilog) function modules.

Background Art

Logarithmic A/D and D/A converters are particularly valuable for encoding analog signals having a dynamic range spanning several decades and decoding the encoded signals to regain the wide ranging analog signals. With such wide ranging signals as the audio signals to be recorded by a digital sound recording system or those involved in seismic testing, a constant relative accuracy of conversion, rather than the constant absolute accuracy of linear conversion systems.

OMPI is desirable. In other words, over the converter's range, it is desirable that the worst case conversion error of the system be a constant relative to the magnitude of the signal being converted, rather than a constant percentage of the range of the converter. Linear conversion techniques are well developed and well documented. Many forms of linear converters are known. Logarithmic conversion despite its potential benefits has not been comprehensively covered in theory or practice. Three classes of logarithmic converters are known or have been proposed. Survey of Logarithmic Analog to Digital Converters: Design and Experimental Results, S. Cantarano and G. V. Pallotino, Comptes Rendus des Journees D'Electronique 1973, p. 117 et seq. The first class can be viewed as the cascade connection of a logarithmic information converter, that operates on analog variables and produces analog variables which are logarithmically related to the analog input variables, and a linear A/D converter. In the second class, the logarithmic converter follows a linear A/D converter and translates a digital input into a logarithmically related digital output. In the third class, the logarithmic conversion and the A/D -conversion are performed by the same structure. This class of converter can theoretically achieve high performance; however, known converters of this class have produced unacceptable error severely limiting the practical usefulness where high accuracy conversion over a wide range is required.

Disclosure of Invention

The present invention provides effective and economical D/A and A/D conversion circuits in which the logarithmic and digital to analog or analog to digital conversions are performed by the same circuit. The invention achieves high performance and is particularly useful where high accuracy conversion is required. The circuits of the invention may be used alone, combined into an A/D or D/A conversion unit, or combined with various known linear converters to form improved log and antilog function modules.

According to one aspect of the invention, a successive approximation logarithmic A/D and D/A converter is provided. This A/D and D/A converter includes a digitally controlled logarithmic attenuation network (LAN), a successive approximation register (SAR) , a sign switching network when bipolar signals are being converted, a comparator and a buffer. A reference signal is applied to one input of the LAN. The LAN has a plurality of attenuation stages. In the A/D mode, the attenuation of each stage is controlled by digital signals from the SAR. In the D/A mode, each stage is controlled by the applied digital signal which is to be converted. Each attenuation stage provides either no attenuation (OFF state) or an ON state attenuation which is logarithmically related to the ON state attenuation of any immediately preceding or following stage. The output of the LAN is connected to the sign switching network and the output of that network provides one input of the comparator and an input of the buffer. The other input of the first comparator serves as the input terminal for analog signals which are to be converted to digital signals. The output of the first comparator is either inverted or fed directly to one input of the SAR depending on the sign of the signal to be converted. The SAR has a clock input and outputs for digital signals which control the attenuation stages in the A/D mode.

In converting an analog signal to a digital signal, the analog signal to be converted is applied to one input of the comparator. In response to clock signals, a first set of output signals is produced by the SAR and the sign of the signal is determined. Then, SAR output signals are produced which set a first attenuation stage, the maximum single stage attenuation, ON and the other attenuation stages OFF. The LAN produces an output signal equal to the reference signal attenuated by the attenuation of the first attenuation stage. Then, the LAN output signal and the analog signal are compared by the first comparator. The output of the first comparator is a signal indicative of whether the LAN output signal is larger or smaller than the analog signal. If the LAN output signal is larger, the SAR fixes its output so that the first stage is ON until conversion is complete. If the LAN output signal is smaller, the SAR fixes its output so that the first stage is OFF until the conversion is complete. Once the first stage is fixed, a second stage is preliminarily turned ON. The output of the LAN is again compared with the analog signal and the second stage is fixed in the ON or OFF state depending on the result of the comparison. This process continues until all the attenuation stages of the LAN are fixed. Once all the stages are fixed, the output of the SAR is a digital signal which is the digital equivalent of the analog signal.

In converting a digital signal to an analog signal, the digital outputs of the SAR no longer control the LAN. In the D/A mode, an applied digital signal which is to be converted controls the setting of the attenuation stages. The output of the LAN under these circumstances is an analog signal corresponding to the applied digital signal. The buffer buffers the analog signal output of the LAN.

In other aspects of the invention, A/D and D/A circuits are separately embodied and are also combined in log and antilog function modules. These other aspects are more fully described in the detailed description which follows.

Brief Description of Drawings

Fig. 1 is a block diagram of one embodiment of a logarithmic D/A converter according to the invention;

Fig. 2 is a block diagram of one embodiment of a logarithmic A/D converter according to the invention;

Fig. 3 is a schematic diagram of one embodiment of a logarithmic A/D and D/A converter according to the invention;

Fig. 3A illustrates one method of isolating one LAN stage from another and an alternative switching configuration for an LAN stage;

Fig. 4 is a circuit diagram showing in greater detail a sign conversion circuit suitable for use in the embodiments of Figs. 1-3;

Fig. 4A is a block diagram of a piecewise approximation logarithmic converter;

Fig. 5 shows a table containing illustrative bit values for an eight bit converter according to the invention and a prior art linear converter also having eight bits;

Fig. 6 is a block diagram of a log function module incorporating a logarithmic A/D converter according to the invention;

Fig. 7 is a block diagram of an antilog function module incorporating a logarithmic D/A converter according to the invention; and

Fig. 8 is a block diagram of an A/D converter according to the invention suitable for very high conversion rates. Modes for Carrying Out the Invention

Fig. 1 is a block diagram of a D/A converter 1 according to the invention. Converter 1 consists of a reference supply 10, a digitally controlled logarithmic attenuation network (LAN) 20 having attenuation stages 22-29, sign switching network 30, an output buffer 40 having an output 41, and digital signal inputs 51-59.

Each of the attenuation stages 22-29 produces in its ON state an attenuation which is logarithmically related to the ON state attenuation of any directly preceding or following stage. This attenuation is independent of whether any other stage is in the ON or OFF state. Each of the attenuation stages 22-29 is controlled by a digital signal applied to its respective input 52-59. The sign switching network 30 is controlled by the digital signal applied to input 51.

In converting a digital signal to an analog signal, converter 1 functions as follows. The sign bit and eight bits of a digital signal to be converted are applied to inputs 51-59. The application of the digital signal to the inputs 52-29 results in each of the attenuation stages being turned ON or OFF. Consequently, the overall attenuation of LAN 20 is determined. Supply 10 produces an output voltage or current, as desired, equal to the full scale of the converter 1. The output of supply 10 serves as one input of LAN 20. LAN 20 attenuates this signal and produces at its output an analog signal equal in magnitude to the analog equivalent of the digital singal applied at inputs 52-59. The output of LAN 20 serves as an input of sign switching network 30. Network 30 multiplies the output of LAN 20 by 1 or -1 depending upon the sign bit signal applied on input 51. The output of network 30 is buffered by a buffer 40. The output of buffer 40 is the analog equivalent of the digital signal to be converted. LAN 20 and network 30 will be discussed in greater detail in conjunction with discussions of Fig. 3 and 4 respectively.

Fig. 2 is a block diagram of an A/D converter 2 for converting bipolar analog signals. Converter 2 consists of a reference supply 10A, LAN 20A having attenuation stages 22A-29A, sign switching network 30A, comparator 50 and successive approximation register (SAR) 60 having a clock input 60A and digital outputs 60B and 61-69. Components 10A, 20A, 22A-29A and 30A correspond to the components 10, 20, 22-29 and 30 of Fig. 1. Converter 2 converts an analog signal to a digital signal as follows. The analog signal to be converted is applied through a resistor to a first input of comparator 50. The output of reference supply 10A includes an offset, which in the preferred embodiment is one half the least significant bit (LSB) of the converter 1 where the value of the most significant bit (MSB) in decibels (dB) equals half the range of the converter 1 in dB plus half the least significant bit in dB. This output is applied to an input of LAN 20A. The attenuation stages 22A-29A are controlled by the signals at SAR 60 outputs 62-69. Initially, output signals are produced so that all the stages 22A-29A are attenuating. Consequently, the output of LAN 20A is approximately 0. Network 30A is initially set up to amplify its input by +1 and since the output of network 30A serves as the second input of comparator 50 the second input of comparator 50 is initially a very small positive signal. If the analog signal to be converted is larger than the output of LAN 20A, then the output of comparator 50 is logical 0. If the analog signal is negative and consequently smaller than the very small positive output of LAN 20A, the output of comparator 50 is logical 1. The output of comparator 50 is fed through switch network 51, which initially connects the output of

OMPI comparator 50 directly to SAR 60 as shown in Fig. 2. By defining the conversion range of converter 2 to exclude signals smaller in magnitude than the output of LAN 20A when all the attenuation stages 22A-29A are turned ON, the initial output of comparator 50 will be indicative of the sign of the analog signal to be converted. Alternatively, the output of LAN 20A may be disconnected from the input of sign switching network 30A by adding a switch which is opened during the sign determination 61 phase so that the analog signal is compared with a 0 signal. The sign information is stored in SAR 60 and produced as an output signal at output 61 for the duration of the conversion process. The signal on output 61 controls switch network Si and sign switching network 30A. A stored 0 (1) indicates a positive (negative) analog signal is being converted. If the analog signal is positive, switch network SI stays as shown in Fig. 2 and network 30A continues to amplify its input by +1. If the analog signal is negative a 1 is stored, then switch network Si switches so that the output of comparator 50 is connected to SAR 60 by way of an inverter and network 30A is switched so that it multplies its input by -1 for all further comparisons of the current sample. By using sign switching network 30A and switch network SI as shown in Fig. 2, any offset of comparator 50 serves only to shift the DC level of all analog signals to be converted. This DC error may be readily eliminated. While certain benefits of positioning the network 30A as shown in Fig. 2 are realized, other positionings are possible.

Once the sign bit is stored in SAR 60, the stages 23A-29A are turned OFF and stage 22A is preliminarily turned ON. The supply signal attenuated by stage 22A is then amplified by network 30A and compared with the analog signal by comparator 50. If the analog signal is larger (smaller) than the output of

UlϊT network 30A, the output of comparator 50 is a 0 (1). If the analog signal is positive, this 0 (1) output is connected directly to SAR 60 and stored in a first bit register. If the analog signal is negative, this 0 (1) output is inverted so that a 1 (0) is stored in the first bit register of SAR 60. The information stored in the first bit register is produced as an output of SAR 60 on output 62 and controls stage 22A for the remainder of the conversion process. If a 0 (1) is stored in the first bit register, stage 22A will be OFF (ON) for the remainder of the conversion process. Next, stage 23A-is preliminarily turned ON. The above described process is repeated until all the stages 22A-29A have been set. Once this has occurred, the conversion is complete and a digital signal corresponding to the analog signal applied at the first input of comparator 50 is stored in the sign bit register and the eight bit register of SAR 60. When this condition is indicated by an output signal on output 60B, the digital signal may be read and stored using known external storage means. Once conversion of a first analog signal has been completed, the system is reset for conversion of a second analog signal. The conversion process steps occur in response to clock signals applied to input 60A of SAR 60. Further details as to LAN 20A and switching network 30A will be provided in the discussions of Figs. 3 and 4.

Fig. 3 illustrates in schematic form a logarithmic A/D and D/A converter 100 having a reference supply 110, a logarithmic attenuation network (LAN) 120, a sign switching network 130, a buffer 140, a comparator 150, inputs 152-159, and a successive approximation register (SAR) 160. Fig. 3 shows in detail one preferred embodiment for LAN 120 having stages 122-192, various logic circuitry for switching from the A/D to the D/A mode and vice versa, and switch network S10. The reference supply 110 produces a reference voltage equal to the full range of analog voltages to be converted by converter 100 plus an offset voltage. This reference voltage is supplied to an input of LAN 120. The LAN 120 shown in a preferred embodiment consists of a network of eight attenuation stages 122-129. Each of the attenuation stages 122-129 is formed by the interconnection of resistors and controllable switches.

While the values of the resistors for each attenuation stage 122-129 vary, the interconnection of resistors and switches in this embodiment is the same for each stage. Just as various designs for individual attenuation or amplification stages in linear A/D and D/A converters may be varied to achieve certain design criteria with respect to speed and accuracy of performance, each attenuation stage in converter 100 need not be an exact replica of the other stages. For example, stages may be isolated from one another by placing buffers between the stages. Isolating the stages removes the requirements of matching the tolerances and temperature characteristics of components in one stage with those of components in another stage. Such isolation is particularly important in systems with a large number of stages and components.

Fig. 3A illustrates one possible buffering arrangement. Fig. 3A shows stages 300, 302 and 303 and buffer 301. Each stage produces an output which is either equal to the signal applied at its input, or an attenuation of its input signal depending upon whether the stage is OFF or ON.

In stage 300, the resistances of resistors 304, 305 and 306 are chosen to produce such outputs and also to minimize the switch resistance effects of switches 307 and 308. This configuration reduces error due to switch resistance and leakage and decreases the settling time of the system. With switch 307 closed and switch 308 open, the output of stage 300 is the signal applied at the input of stage 300 less the attenuation of the stage. With switch 307 open and switch 308 closed, the output of stage 300 equals the signal applied at its input. Assuming a near zero source resistance at the input of stage 300, resistor 306 has a resistance equal to the parallel resistance of resistors 304 and 305.

High impedance buffer 301 is used to isolate stage 300 from the stages 302 and 303.. The settling time of buffer 301 is selected so that its output will settle within a rated settling time taking into consideration the changes of state from ON to OFF and vice versa of stage 300. Any DC error contributed by buffer 301 must be kept small enough so that the output of buffer 301 does not deviate from the desired output by more than 1 LSB or less.

Stage 302 is similar to stage 300. Stage 303 is a stage in which the resistance of resistor 320 is very much larger than the resistance of resistor 319, such as in a MSB stage. The configuration of switches 315, 316, 317 and 318 provides one way to deal with potential settling time problems associated with the capacitance of switch 315 and the high resistance of resistors 320. Switch 318 provides a low impedance path to ground so that rapid settling may be achieved.

Returning to discussion of Fig. 3, stage 122 will be discussed as illustrative of all the stages 122-129. Stage 122 consists of a resistor 221 connected in shunt with a controllable switch 222. A first port 225 of this interconnection of resistor 221 and switch 222 is connected to attenuation stage 123. The second port 226 connects to ground through a resistor 223 and a controllable switch 224. Both switches 222 and 224 are controlled by the digital signal applied to input 152. Switch 222 is closed when switch 224 is open and vice versa. One convenient source of controllable switches is the DG 186 switch manufactured by Siliconix. To achieve suitable speed and accuracy of performance in certain applications, other switching devices may be necessary. For applications requiring extremely high accuracy but low conversion rates, relays may be ideal. When switch 222 is closed and switch 224 is open, stage 122 produces no attenuation (OFF state) . When switch 222 is open and switch 224 is closed, stage 22 attenuates the connected through resistor 210 and closed switches 232-292 and voltage appearing at port 225 by a factor determined by the ratio of the resistance of resistors 221 and 210 and the equivalent resistance of resistor 223 (ON state), i.e., (R221 + R223 + R210)/ R223), ignoring on resistance contributions of switches 232-292. Each of the stages 122-129 has a pair of switches which are controlled by the digital signal applied to its respective digital control input 152-159.

The values of the resistors in LAN 120 are selected in order to achieve the following results:

1. The attenuation introduced by any individual attenuation stage is independent of whether any other stage is in the ON or OFF state, and

2. Each attenuation stage produces in the ON state an attenuation which is logarithmically related to the ON state attenuation produced by any preceding or following stage.

In the preferred embodiment, each attenuation stage will have one half the attenuation in decibels (dB) of the preceding stage. This preferred format allows digital code representation of any analog value within the range of operation of the converter without redundant code values and with constant accuracy in the sense that the worst case deviation of the coded value from the actual analog value to be encoded is a constant percentage of any analog valve within the entire range of operation of the converter. As an example of the above preferred arrangement, if stage 122 is designed to produce attenuation of 64 dB, i.e., the ratio of the output signal at port 226 to the reference signal at output of supply 110 is .00063 ^'when stage 122 alone is ON; then stage 123 would have an attenuation of 32 dB and the other stages 124-129 would have attenuations of 16, 8, 4, 2, 1 and 1/2 dB respectively. The values of resistance for the resistors 210, 221-291 and 223-293 are determined from the following relationships:

1. The resistance of resistor 210 (R210) is equivalent. to the resistance of the resistance of resistor 223 (R223) in parallel with the series resistance of resistors 210 and 221 or alternatively (R210 + R221)|| R223 = R210. Similarly, (R210 + R231-291) II R233-293 = R210.

2. The value for each of the resistors 221-291 is determined as follows:

R221-291 R210 x (10^N/20-l), where N is the desired attenuation for the stage in dB.

3. The value for each of the resistors 223-293 is determined as follows:

R223-293 = (R210 + R221-291/(10^N/20-l) , where N is again the desired attenuation for the stage in dB.

The attenuation for LAN 120 is determined by the signals applied to control inputs 152-159 which control whether the stages 122-129 are in their ON or OFF states. The output of LAN 120 serves as one input of the sign switching network 130. Sign switching network 130 functions similarly to networks 30 and 30A. The output of network 130 is applied to one input of the comparator 150 and also as an input to buffer 140 which buffers the analog signal output when apparatus 100 is operating in the D/A conversion mode. The other input of the comparator 150 is the analog signal which is to be converted into a digital signal by the A/D and D/A converter 100. The output of comparator 150 is connected to an input of SAR 160 through switching network S10. SAR 160 also has a clock input 160A, a reset output 160B and digital outputs 161-169. Output 160B produces an output signal when the A/D conversion process is completed and a new conversion can begin. Outputs 161-169 are connected through tristate buffers 610-690 to control inputs 151-159. Each of the tristate buffers 610-690 has as one of its inputs the output signal from one of the outputs 161-169. As its other input, each of the tristate buffers 610-690 has a control signal 70 which is high (logical 1) for A/D conversion and low (logical 0) for D/A conversion. When the control signal 70 is high, each of the tristate buffers 610-690 will have at its output the same output signal as occurs at the respective output of the SAR 161-169 connected to its input.

Control signal 70 also serves as the input of the inverter 71. Inverter 71 produces at its output an inverted control signal 70. This signal TO serves as one input of tristate buffers 71-79. The other input of each of the tristate buffers 71-79 is either a high (1) or a low (0) signal which is part of a digital signal to be converted on lines applied to inputs 711-791. Tristate buffers 71-79 function similarly to tristate buffers 610-690. When the inverted control signal 70 is low (A/D conversion) , each tristate buffer 71-79 will produce a high impedance output. When the signal TO is high (D/A conversion) , each tristate buffer 71-79 will have its output the same digital signal as applied to . inputs 711-791. The outputs of tristate buffers 71-79 - are connected to inputs 151-159 respectively. Consequently, in the D/A conversion mode, the digital coded signal to be converted applied on lines 711-791 controls the attenuation of LAN 120. From the preceding discussion, it is seen that control signal 70 controls whether the apparatus 100 will function in the A/D or D/A conversion mode.

Several examples will now be discussed to more fully explain the operation of apparatus 100. In these examples, it will be assumed that the stages 122-129 have individual attenuations ranging from 64 dB to 1/2 dB. First, A/D conversion will be discussed with the reference supply 110 supplying one volt to input port 121 and an analog voltlage to be converted of .7000. Fig. 5 shows the attenuation of each of the stages 122-129 and the output voltage signal that wil be produced by each stage when a one volt signal is applied at its input. The eight bit digital conversion code for an analog signal of .7000 volts may be theoretically computed as follows:

1) 20 log (.7000V/1)= -3.0980

2) -3.0980dB = [(Ox -64) + (Ox - 32) + (Ox -16) + (Ox - 8) + (Ox -4) + (lx -2) + (lx -1) + (Ox -1/2)] dB.

Hence, the digital code should be 00000110. The sign bit will be 1 since .7000 volts is a positive voltage.

Apparatus 100 achieves the above conversion in the following manner. The control signal 70 is set high for A/D conversion. The conversion cycle begins with the determination of the sign of the analog signal in a similar fashion to that discussed with regard to the operation of converter 2 of Fig. 2. Once the sign has been determined and the sign bit has been stored, the output 162 of SAR 160 is set high and outputs 163-169 low. Stage 122 is preliminarily in its ON state and stages 123-129 are in their OFF state. The one volt input from supply 10 is attenuated by 64 dB and the output of the LAN 120 is .00063 volts. Comparator 150 compares .00063 volts with .7000 volts producing a low output. This low output is stored in SAR 160 and a low output is produced at output 162 for the duration of the conversion sycle, i.e., stage 122 is OFF until a new conversion cycle begins. Next, with a low output at outputs 162 and 164-169, a high output is produced at output 163. As a result, stage 123 is the only stage ON and the LAN 120 produces an output of .02512 volts. This voltage is again lower than .7000 volts and comparator 30 again produces a low output which is stored in SAR 160. Consequently, a low output will be produced at output 163 for the duration of the conversion cycle. This cycle continues until stage 127 is turned ON. The output of LAN 120 with only stage 127 ON is .79433 volts. This voltage output is greater than .7000 volts and comparator 150 produces a high output which is stored in SAR 160 resulting in output 167 being fixed high, i.e., stage 167 is in the ON state, for the remainder of the conversion cycle. Next, stage 128 is turned ON. The output of stage 128 is .89125 volts. This output voltage serves as the input to stage 127 which attenuates the .89125 volts by 2 dB. The output of the LAN 120 is then .70795 volts. This voltage is again greater than .7000 volts and comparator 150 produces a high output. Consequently, output 168 is fixed at a high output for the duration of the conversion cycle. Then, the final output 169 is preliminarily set high turning stage 129 ON. The output of stage 129 is .94406 volts. This voltage serves as the input of stage 128 which attenuates the .84406 volts by 1 dB producing an output of .84139 volts. This .84139 volts is further attenuated by 2 dB by stage 127 resulting in a LAN 120 output of .66834 volts. The voltage of .66834 volts is less than .7000 volts. Consequently, comparator 30 produces a low output and the final output 169 is fixed at the low output level. With conversion complete an output appears at output 160B of SAR 160 indicating that valid data is available at the register outputs 161-169, and that a new conversion may be begun. The sign bit at output 161 is a 1 and the outputs 162-169 are 0, 0, 0, 0, 0, 1, 1 and 0 respectively. Thus the theoretically computed digital code is obtained.

To convert this digital signal to an analog signal, the apparatus 100 functions as follows. A low signal for D/A conversion is applied to input 70. The digital signals 1, 0, 0, 0, 0, 0, 1, 1 and 0 are applied to inputs 711-791 respectively. Consequently, the digital signals are applied to inputs 151-159, stages 127 and 128 are turned ON, and the other stages are turned OFF. The reference supply of one volt is attenuated by 2 dB by stage 127 resulting in a .79433 volts input to stage 128. Stage 128 produces further attenuation of 1 dB on its input resulting in an LAN 120 output of .70795 volts. This analog output voltage is buffered by buffer 140. For this example, the error in the conversion/reconversion process is .00795 volts or approximately 1% error. The range of a system following the principles of the invention is 2MSB-LSB and the error of this system is relative throughout this range. For example, with MSB of 64dB, a LSB of dB, a reference voltage of 1 volt and an offset voltage of .5 LSB in volts (.0292V), an encoded signal of 00000000 will result for analog signals x to be encoded within the range 1.0292V > x > .97163V. The worst case error occurs at either end of the range since 00000000 is decoded as 1 V. The worst case error is approximately +_ 2.8%. The encoded signal 11111111 results for analog signals X in the range .4340uV> x> .4097uV for a worst case error of i 2.8% from the decode value of .4217uV. The system error may be reduced by increasing the number of attenuation stages. While the above discussion concerns error inherent in the conversion system, it is noteworthy that any component error introduced or transmitted by a stage is attenuated by each of the following stages. While all the examples discussed

O -18-

above have involved eight conversion bits plus a sign bit, additional conversion bits may be necessary where additional accuracy is required. Where a large number of stages and bits, e.g. 20 bits., are used, the only significant error results from component errors and the like and not the theoretical limitations of the conversion system.

Fig. 4 shows a sign switching network 330 which may suitably be used to carry out the function of networks 30, 30A and 130 of Figs. 1, 2, and 3 respectively. Network 330 consists of input 331, control input 332, switch networks 335, 336 and amplifiers 337, 338 and 339. Network 330 multiplies the signal applied to input 331 by +1 or -1 depending on the control signal applied to control input 332. Switch network 335 is set up so that switch 335A is closed (open) and 335B is open (closed) when a high (low) signal is applied to input 332. Switch network 336, on the other hand, is set up so that switch 336A is open (closed) and 336B is closed (open) when a high (low) signal is applied to input 332. When a low (high) signal is applied to input 332, sign switching network 330 produces an output equivalent to the signal applied to input 331 multiplied by +1 (-1).

Fig. 4A illustrates a log conversion system 600 incorporating existing linear components to realize a piecewise approximation logarithmic conversion. This combined system may be advantageous as there are many linear digital networks currently available at low cost. By reducing the number of log stages and substituting stock linear networks costs may be reduced until such time as logarithmic devices have been more fully commercialized.

Fig. 4A shows linear D/A converter 610 connected to the input of buffer 620 and the output of buffer 620 connected to LAN 630. LAN 630 functions as previously described with respect to Figs. 1-3. Buffer 620 provides impedance buffering between D/A converter 610 and LAN 630. The linear D/A converter 610 produces a range of output signals ranging between the signals applied to reference inputs 603 and 604 depending upon the signals applied to address lines 605. In the preferred embodiment- the signal applied to reference input 603 is established at the desired full scale value of the system plus an offset if desired. The signal at input 604 is set at the value of the signal applied to input 603 minus the attenuation factor of the LSB of LAN 630.

The embodiment shown in Fig. 4A minimizes the error contributions of the converter 610 to the system error. The system error attributable to converter 610 equals E(1-J0x '/20 ) where E is the error for converter

610 standing alone and X is the value of the LSB of LAN

630. The range of converter 601 is approximately 2 x

MSB Of the LAN 630.

Fig. 5 shows a table containing illustrative bit values for an eight bit converter according to the invention and a typical linear converter known in the art. Several examples using the table will illustrate how the conversion error of a converter according to the present invention compares to that of a simple linear converter. In all these examples for the sake of simplicity, neither converter includes an offset. A logarithmic A/D converter according to the preferred embodiment discussed in conjunction with Fig. 3 will . convert an analog +.99000 volts signal as 00000000 or

1.0000 volts for a conversion error of approximately 1%.

The eight bit linear converter corresponding to the table values of Fig. 5 will convert a 99000 volt signal as 1 1 1 1 1 1 0 1 ( [ l x .5000] + [1 x .25000] + [1 x

.12500] + [1 x .06250] + [1 x.03125] + [1 x .01563] + [0 x .00781] + [1 x .00391] ) or .98829 volts for a conversion error of approximately .17%.

The eight bit logarithmic converter will convert a .00506 volt signal as 01011011 or .00532 volts for a conversion error of approximately 5%. This error would be 2.8% or less with a .5 LSB offset voltage. The eight bit linear converter will convert a .00506 volt signal as 00000001 or .00391 volts for a conversion error of approximately 23%. The eight bit logarithmic converter will convert a .00001 volt signal as 1 1 0 0 1 0 0 0 or .00001 volts for a conversion error of approximately- 0%. The eight bit linear converter will convert a .00001 volt signal as 0 0 0 0 0 0 0 0 or 0 volts because the small signal is out of the range of the linear converter. It has been shown earlier that the logarithmic converter has a constant worst case relative error over a wide range of operation. The linear converter, on the other hand, has a constant absolute error and a much narrower range of operation for the same complexity of circuit and the same number of bits. Further, the logarithmic converter can square its range of operation by adding an additional bit as the most significant bit or double its resolution by adding a new least significant bit. The smaller bits in the logarithmic converter may have lesser accuracy without degrading the converter system performance since each bit affects only a given percentage of any entire value to be encoded.

Figs. 6 & 7 illustrate in block diagram form log and antilog function modules incorporating converters 2 and 1 according to the present invention. Traditional log and antilog function modules are generally dependent on transistor current characteristics which are logarithmic. The limitations of this approach are familiar to those skilled in the art. Fig. 6 shows a log function module 400. Module 400 has an analog input 401 which serves as the input of a logarithmic A/D converter 2 corresponding to the converter shown in Fig. 2. Converter 2 has output lines

62-69 which serve as the input lines of a linear D/A converter 420. Converter 2, after sampling the input, produces a digital output ,on lines 62-69. This signal on lines 62-69 serves as the controlling input signal for a linear D/A converter 420 which produces an analog output signal at its output 421 which is the log of the input signal, i.e.. Output 421 = Log Input 401.

Fig. 7 shows an antilog function module 500.

Module 500 has an analog input 501 which serves as the input of a linear A/D converter 510. The digital outputs of converter 510 serves as the digital input on inputs 52-59 of a logarithmic D/A converter 1 corresponding to the converter of Fig. 1. The output at terminal 41 of converter 1 is the antilog of the input signal, i.e.. Output 401 = Antilog Input 501. For both systems, sample and hold circuits and low pass filters may be utilized as dictated by familiar sampling theorem considerations.

While all the LAN's discussed above have been described in terms of gain controlling stages consisting of attenuation stages, it is apparent that by appropriate modification gain stages could be used instead of attenuation stages. While the gain controlling stages are shown connected between the reference supply and one input of a comparator, these gain stages could be connected in other ways, for example, the gain stages might be connected between the analog input and the other input of the comparator.

Similarly, while the examples discussed involve voltage based systems, current based systems are also readily implemented.

Fig. 8 shows a logarithmic A/D converter 800 suitable for use where very fast conversion rates are required, for example, conversion at frequencies greater than 5 MHz. Converter 800 is a logarithmic parallel "flash" encoder system comprising a reference supply 801, an analog input terminal 798, a logarithmic resistance network 802 including resistors R1-R8, seven comparators 809-815, and a logic matrix 816 having digital output lines 817. The input applied to terminal 798 serves as one input of all the comparators 809-815. A second input to the comparators 809-815 is taken from various taps on resistance network 802. The resistance values of resistors R1-R8 are chosen so that the reference supply voltage produced by supply -801 is attenuated logarithmically, for example, attenuations of 2, 4, 6, 8, 10, 12 and 14 dB may be produced using resistors Rl = 205 ohms, R2 = 163 ohms, R3 = 130 ohms, R4 = 103 ohms, R5 = 82 ohms, R6 = 65 ohms, R7 = 52 ohms, and R8 = 200 ohms. The outputs of comparators 809-815 serve as inputs of logic matrix 816. Logic matrix 816 encodes the comparator output signals in a normalized binary bit form with codes ranging from 000 to 111.

OMPI

Claims

I claim:

1. A logarithmic gain controlling network having a plurality of serially connected gain controlling stages each of said stages comprising a controllable circuit which is controlled to produce unity gain or a fixed nonunity gain, the fixed nonunity gain of each stage of the logarithmic attenuation networks being logarithmically related to the nonunity gains of every other stage.

2. A logarithmic digital to analog converter comprising a logarithmic gain controlling network having a plurality of serially connected gain controlling stages each of said stages comprising a controllable circuit which is controlled to produce unity gain or a fixed nonunity gain, the fixed nonunity gain of each stage of the logarithmic attenuation networks being logarithmically related to the nonunity gains of every other stage, the number of said plurality of gain controlling stages corresponding to the number of bits in digital signals which are to be converted by the digital to analog converter, and a reference power supply having an analog output connected to the first of the plurality of gain controlling stages, whereby the digital signals to be converted control the gains of the gain controlling stages and the output of the reference power supply is modified by the logarithmic attenuation network so that the output of the last gain control stage is an analog signal corresponding to the digital signal to be converted.

3. A logarithmic analog to digital and digital to analog converter comprising a logarithmic gain controlling network having an input terminal for application of a reference signal, an output terminal for an analog output signal, a plurality of attenuation stages serially connected between the input and output, each of the attenuation stages comprising a controllable circuit having a control input to control the attenuation of the attenuation stage, means for producing a plurality of digital outputs in response to an applied control signal having a control input and a plurality of digital outputs, a comparator having a first input for application of an analog signal, a second input connected to the output of the logarithmic attenuation network, and an output connected to the control input of the means for producing a plurality of digital outputs, a plurality of digital signal input lines, and means to selectively connect either the plurality of digital outputs of the means for producing a plurality of digital outputs or the plurality of digital signal input lines to the control inputs of the plurality of attenuation stages.

4. The logarithmic gain controlling network of claims 1, 2 or 3 wherein the nonunity gains of the stages follow the relationship that each" stage produces an on state gain which is the square root of the on state gain of the next larger stage.

5. The logarithmic gain controlling network of claims 1, 2 or 3 wherein at least one of the controllable circuits comprises an interconnected network of resistors and controllable switches responsive to a digital control signal.

6. The logarithmic gain controlling network of claims 1, 2 or 3 further comprising a buffer stage connected between two of the plurality of serially connected stages.

7. The converter of claim 3 wherein the means for producing a plurality of digital outputs comprises a successive approximation register.

8. A piecewise approximation logarithmic digital to analog converter comprising a linear digital to analog converter having a plurality of digital data inputs, an input terminal and an output terminal; a plurality of serially connected gain controlling stages each of said gain controlling stages including a control terminal, an input terminal and an output terminal, the input of the first gain controlling stage being connected to the output terminal of the linear digital to analog converter and the input of each of the plurality of gain controlling stages other than the first being connected to the output terminal of the preceding stage; and a reference supply connected to the input terminal of the linear digital to analog converter, whereby when a digital signal comprising a plurality of data bits is applied to the plurality of digital data inputs of the linear digital to analog converter and to the controlling terminals of the plurality of gain control stages an analog signal corrresponding to the digital signal is produced at the output of the last gaining controlling stage.

9. The converter of either claim 3 or 8 further comprising a sign switching network connected between the output of the logarithmic attenuation network and the second input of the comparator and a switching network connected between the output of the comparator and the means for producing a plurality of digital outputs both of said networks having a control input connected to an output of the means for producing a plurality of digital outputs.

10. A logarithmic analog to digital converter comprising a logarithmic gain controlling network having an input terminal for application of a reference signal, an output terminal for an analog output signal, a plurality of logarithmic gain controlling stages connected between the input and output, each of the gain controlling stages having a control input register having a control input to control the gain of the gain controlling stage, a means for producing a plurality of digital outputs in response to an applied control signal having a control input and a plurality of digital outputs which are connected to the control inputs of the plurality of attenuation stages, and a comparator having a first input for application of an analog signal, a second input connected to the output o the logarithmic gain controlling network, and an output connected to the control input of the means for producing a plurality of digital outputs.

11. The converter of claim 10 wherein the means for producing a plurality of digital outputs comprises a successive approximation register.

12. The converter of claims 10 or 11 further comprising one or more controllable gain stages connected to the first input for application of an 'analog signal so that an analog signal to be converted is connected through said controllable gain stages to the comparator.

13. The logarithmic gain controlling network of claim 10 wherein the nonunity gains of the stages follow the relationship that each stage produces an on state gain which is the square root of the on state gain of the next larger stage.

14. The logarithmic gain controlling network of claim 10 wherein at least one of the gain controlling stages comprises an interconnected network of resistors and controllable switches responsive to a digital control signal.

15. The logarithmic gain controlling network of claim 10 further comprising a buffer stage connected between two of the plurality of serially connected gain controlling stages.

16. A logarithmic analog to digital converter comprising a logarithmic attenuation network consisting of a logarithmic resistance ladder with a plurality of taps, a plurality of comparators each having a first input connected to an analog signal input terminal, a second input connected to one of the plurality of taps on the logarithmic resistance ladder and an output, and a logic matrix for converting a plurality of input signals to digital output signals having a plurality of digital outputs and a plurality of inputs connected to the outputs of the plurality of comparators.