Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/20—Arrangements for cooling
  • H10W40/25—Arrangements for cooling characterised by their materials
  • H10W40/258—Metallic materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
  • H10W40/77—Auxiliary members characterised by their shape
  • H10W40/774—Pistons, e.g. spring-loaded members
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/877—Bump connectors and die-attach connectors

Definitions

• This invention relates to a cooling means for an integrated circuit chip device, and in particular to a method and means for sustaining low thermal contact resistance to achieve chip cooling.
• prior art heat dissipation techniques of IC chip devices can provide thermal control up to a maximum allowable chip temperature of 85°C without
• the mechanical configurations of prior art IC chip assemblies affect the value of the thermal contact resistance that may be attained.
• the contact interface provides a relatively high thermal resistance.
• the technical problems solved by this invention are the efficient dissipation of heat and temperature control in an integrated circuit chip device.
• a non- eutectic metal alloy is used to form a low thermal resistance bridging interface between the surface of the chip device and a heat sink.
• the alloy has a solidus-liquidus temperature range such that the solidus is slightly below the maximum operating temperature of the chip, and thus has the capability to reestablish and maintain the interface at a low thermal resistance
• OMFI if stressed during circuit operation, even with a low contact load at the interface of the chip device and the heat sink.
• the above cooling means is also used at other interfacial regions of the heat sink, dependent on design, to achieve very low thermal resistance.
• FIGS. 1A and IB are sectional views of an IC circuit semiconductor chip assembly, depicting the condition of the interface between the chip surface and the surface of a heat sink under a contact load, when the chip temperature is respectively less than and greater than the solidus temperature;
• FIG. 2 is a sectional view, partially cut away, of one illustrative heat sink technique in an IC chip assembly incorporating the invention at the chip inter ⁇ face;
• FIG. 3 is a plot of interface resistance relative to interface temperature, illustrating the thermal resistance reduction and maintenance characteristics at the chip interface with a constant interface contact load
• FIG. 4 is a sectional view, partially cut away, of another heat sink technique in an IC chip assembly incorporating the invention at both the chip and hat cover interfaces.
• an IC package comprises a semiconductor chip 10 that is bonded to a substrate 12 by bonding means 14, which may be solder ball connections, by way of example.
• a controlled load force F is applied, as designated by the arrow, by means of a spring 16, for example, to the chip 10
• OMPI y H to maximize the surface contact of the chip with a pivotable piston heat transfer element 18 of a high thermal conductivity material such as copper. Heat generated in the chip is conducted across the chip interface into the piston element and from the element to the surrounding structure essentially by gaseous conduction across the gap spaces 26.
• the surrounding hat structure 20 provides a cover and additional heat diffusing means for the IC package.
• a low temperature noneutectic bis ⁇ muth alloy 22 is bonded to the heat transfer element.
• the alloy used is com ⁇ flashally available Ostalloy, a product of Arconium Corp. of America.
• the alloy is composed of 51.45% bismuth, 31.35% lead, 15.20% tin and 2.0% indium, and is characterized by a solidus temperature T ⁇ of about 88°C, and a liquidus temperature T_ of about 112°C.
• An alternative low melting temperature alloy that may be used has a composition of 48.35% bismuth, 28.15% lead, 14.50% tin and 9.0% antimony, and has a solidus temperature of about 87°C and liquidus temperature of about 128°C. Still other compositions are also practical depending on desired thermal operating conditions of the IC device.
• the bismuth alloy 22 is deposited on the heat sink surface to a thickness of approximately 2 mils, and as illustrated in FIG. 1A, initially only makes actual contact with the surface of the chip 10 at spaced points between voids 24. With this initial condition of the alloy randomly contacting the cold chip surface over a small aggregate heat transfer area, the inter ⁇ face thermal resistance is relatively high, and heat transfer is relatively low.
• the temperature of the device is raised to the melting range of the alloy. As the temperature of the chip is increased to a temperature T_ greater than the solidus temperature
• T ⁇ / the bismuth alloy melts and conforms under viscous flow conditions by the action of the applied force F, to fill the void spaces 24, as depicted in FIG. IB.
• the resulting increased contact area and thus the thermal enhanced path between the chip and the heat transfer element through the alloy now filling the voids causes a .sharp decrease in thermal resistance at the interface and thus allows effective dissipation of the excessive heat.
• the above local conforming action of the thin alloy layer is confined to the interface region by the controlling action of surface tension forces.
• chip interface thermal resistances of 0.1 to 0.2°C per watt are obtained with contact loads of approximately 100 grams.
• the resistance levels obtained by means of this invention are approximately five to seven times lower than that realized with thermal grease.
• the process according to this invention is illus- trated in FIG. 3.
• the relatively high resistance R ⁇ at the time of assembly, is reduced to a low level R L by a reflow operation.
• the resistance remains at such low level R-. in the operating tem- perature range.
• the rise in resist ⁇ ance causes a temperature rise into the pasty range where the resistance and temperature both decrease rapidly back to their initial states.
• the maximum solidus temperature ⁇ UST S would be in the order of 1-3°C, while the solidus-liquidus ⁇ T S;L may be in the range of 15-25°C.
• the system is always in a solid state under normal operating conditions. Any excursions into the solidus-liquidus range for thermal resistance-temperature recovery constitutes a very small time period relative to the product life. Since the system is virtually always in the solid state, contact loads at the interface are low and adverse metallurgical phenomena are essentially eliminated. Also, once the initial low resistance value R ⁇ is obtained, any disturbances at the chip surface will cause momentary increases in resistance. These small resistance changes are removed in very short time periods. By means of the self-healing technique dis ⁇ closed, an extremely low thermal resistance level is maintained without the need for extra reflow steps. The disclosed technique ensures long-term maintenance of low thermal resistance at the chip interface, which is very significant as chip sizes decrease and power dissipation requirements rise. In addition to achieving low thermal resistance at the chip interface, as by application of the illus ⁇ trated heat sink technique in FIG. 2, this invention
• FIG. 4 An example of such a structure, where this invention is used at both the chip and hat interfaces, is illustrated in FIG. 4.
• a controlled load force F is applied diagon ⁇ ally, as designated by the arrow, by means of a spring 10 16, for example, to a pivotable piston heat transfer element 18.
• the 15 bismuth alloy 22 is deposited on each surface of the piston to a thickness of approximately 2 mils, and as illustrated in FIG.
• the temperature of the device is raised to " the melting range of the alloy.
• T c the melting range of the alloy.
• the bismuth alloy melts and under the action of the applied force component F v , fills the void spaces as described previously.
• the alloy melts at the hat interface.
• the process for the hat interface condition is the same as that for the chip contact.
• the relatively high resistances Renfin at the time of assembly, are reduced to low levels R_ by a reflow operation.
• the resistances Upon reducing the temperature below the maximum operating condition, the resistances remain at such low levels R-. in the operating temperature range. If disturbance of the interfaces occurs, the self-healing action of the alloy causes a rapid recovery of the low thermal resistances and temperatures in a manner discussed previously in connection with FIG. 3.
• the chip interface thermal resistances of 0.1 to 0.2°C per watt are obtained with contact loads of approx-
• the corres ⁇ ponding preferred hat interface thermal resistances are in the range of 0.01 to 0.02°C per watt.
• FIGS, 2 and 4 represent just two of a number of possible con ⁇ figurations for achieving and maintaining highly effective heat dissipation. With the structure of this invention, applications that require from 9-20 watts/chip heat dissipation are feasible.

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• Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Priority Applications (4)

Applications Claiming Priority (1)

Publications (1)

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ID=22161583

Family Applications (1)

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Cited By (5)

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Citations (6)

Family Cites Families (3)

• 1981
  • 1981-12-29 WO PCT/US1981/001754 patent/WO1983002363A1/en not_active Ceased
  • 1981-12-29 JP JP82500649A patent/JPS58501648A/ja active Granted
  • 1981-12-29 DE DE8282900586T patent/DE3176475D1/de not_active Expired
  • 1981-12-29 EP EP82900586A patent/EP0097157B1/en not_active Expired

Patent Citations (6)

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