WO1982002977A1

WO1982002977A1 - Memory cell having more than two voltage levels

Info

Publication number: WO1982002977A1
Application number: PCT/US1982/000136
Authority: WO
Inventors: Inc Motorola; Richard H Adlhoch
Original assignee: Inc Motorola
Priority date: 1981-02-25
Filing date: 1982-02-01
Publication date: 1982-09-02
Also published as: EP0072846A1; IT1186670B; IT8247842A0

Abstract

A read-only memory array having storage cells (10-13) capable of storing more than two logic states. The size of the devices used in the storage cells (10- 13) can all be of equal size. If the devices are connected in a source follower configuration, the voltage level associated with each memory storage cell can be controlled by selectively adjusting the threshold voltage of the device. In such a memory array, it is possible for all the devices to be of equal size and therefore they can be made of a minimum size which reduces the overall size of the memory.

Description

MEMORY CELL HAVING MORE THAN TWO VOLTAGE LEVELS

CROSS REFERENCE TO RELATED APPLICATIONS

Patent Applications Serial Numbers CR-81086 and CR-81087 are related copending applications by the same inventor, assigned to the same assignee, and filed on the same date as the present application.

BACKGROUND OF THE INVENTION

This invention relates, in general, to memory cells and more particularly, to a memory cell having more than two voltage levels and a method for making same. In the past, it has been customary for read-only memories using field effect transistors to have at most one transistor per bit. In such a case, if there was a transistor in the memory cell location, then a logic 1 was considered stored there. If no transistor existed in the memory storage location, then a logic 0 was considered to be stored in that location. Therefore, each storage location was only capable of storing one bit of information per storage cell location.

More recently, a read-only memory (ROM) cell has been proposed which is capable of storing more than two logic states. These new ROM cells control the number of states stored by varying the gain of the transistor. The gain can be preset by varying the size of the transistor or by changing the threshold of the transistor. Such a ROM cell has been disclosed in patent application Serial No. 972,619 filed December 22, 1978, for Jerry D. Moench, and assigned to the same assignee as the present application.

It has since been discovered that another highly advantageous ROM cell, which is beneficial in certain applications, can be derived from connecting the storage location transistor in a source follower configuration. As the threshold voltage of the transistor is shifted, the voltage appearing at the source of the transistor has the value applied at the gate of the transistor minus a threshold. One of the advantages of this newly discovered memory cell, which will be discussed in greater detail hereinafter , is that all of the transistors can be of the same physical size and every memory location can have, its own transistor.

Accordingly, it is an object of the present invention to provide an improved memory cell capable of storing more than two voltage levels.

Another object of the present invention is to provide a read-only memory array having a plurality of storage locations wherein each storage location contains a complete transistor.

Yet another object of the present invention is to provide a read-only memory array having a plurality of storage locations wherein each storage location has a field effect transistor of the same physical size, and wherein the memory cells are capable of storing more than two logic states.

A further object of the present invention is to provide a read-only memory array and method for making same wherein the memory array has a plurality of storage locations each having a field effect transistor connected in a source follower configuration and some of the field effect transistors have threshold voltages which are different from other of the field effect transistors.

SUMMARY OF THE INVENTION

In carrying out the above and other objects and advantages of the present invention, there is provided in one form thereof, a read-only memory array having a new and novel memory cell which is capable of storing more than two voltage levels. The memory array has a first field effect transistor connected in a source follower configuration in a first storage location, and at least a second field effect transistor connected in a source follower configuration and located in another storage location. The first and second field effect transistors are substantially the same physical size but yet have different threshold voltages. Since the transistors are connected in a source follower configuration, the voltage at the source of the transistor is the gate voltage minus the transistor's threshold voltage. Therefore, the threshold voltages of the transistors can be shifted in any suitable manner, such as by ion implantation or the like, so that the storage locations are capable of providing more than two choices of predetermined voltage levels.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates in schematic form a memory array using the present invention in one form thereof; FIG. 2 illustrates an abbreviated form of the memory array of FIG. 1 with additional output circuitry; and

FIG. 3 is a plan view of a portion of a memory chip showing programming mask locations.

The exemplification set out herein illustrates thepreferred embodiment of the invention in one form thereof, and such exemplification is not to be construed as limiting in any manner.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a portion of a read-only memory wherein only four storage locations are illustrated in order to keep the drawing from becoming overcrowded. Each of the four storage locations contains a field effect transistor 10, 11, 12, and 13, respectively. Only two bit lines 16 and 17 and two row select lines 21 and 22 are illustrated. It will be understood that the memory array contains many bit lines and row-select lines in addition to many storage locations. A difference between the memory array illustrated in FIG. 1 and the prior art memory arrays is that transistors 10/ 11, 12, and 13 can have different threshold voltages. Any convenient and well-known method of changing thresholds of field effect transistors can be used. By way of example, one such method is disclosed in an article entitled "MOS Threshold Shifting by Ion Implantation," by Thomas William Sigmon and Richard Swanson, Solid State Electronics, 1973, Vol. 16, pp. 1217-1232. Another such article is "The Adjustment of MOS Transistor Threshold Voltage by Ion Implantation," by M. R. MacPherson, Applied Physics Letters, Vol. 18, No. 11, June 1, 1971. Both of these articles are hereby incorporated herein by reference.

By using the methods proposed in the two articles, incorporated herein by reference, the threshold voltage of the transistors can be adjusted so that each memory location can have one of many different voltage levels to represent many different bits of information. However, it is believed that the optimum number of levels is four since having a memory location storing more than a four-state signal would increase the complexity of the sensing and readout circuitry of the memory. A four-state cell would double the read-only memory bit capacity since each storage location would be capable of storing two bits of information instead of one bit of information. Accordingly, in a preferred embodiment, the illustrated memory array will be referred to as a four-state memory cell.

Transistor 10 has a drain electrode connected to a voltage terminal 14 and a source electrode connected to bit line 16. The gate electrode of transistor 10 is connected to row-select line 21. Row-select line 21 is also connected to the gate electrode of transistor 11.

Transistor 11 has its drain electrode connected to voltage terminal 14 and a source electrode connected to bit line 17. Transistor 12 has its drain electrode connected to voltage terminal 14 and a source electrode connected to bit line 16. Transistor 13 has its source electrode connected to bit line 17 and its drain electrode connected to voltage terminal 14. The gate electrodes of transistors 12 and 13 are connected to row-select line 22. Any suitable voltage source or signal can be connected to voltage terminal 14 keeping in mind that such voltage must be equal to or greater than the voltage applied to the gate electrode.

The transistors in the memory array illustrated in FIG. 1 are connected in a source follower configuration and therefore the voltage appearing on a bit sense line will be the voltage applied to the gate electrode of the transistor minus its threshold voltage. Therefore, as a matter of example, if the threshold voltage of transistor 10 is 6/10ths of a volt, and the threshold voltage of transistor 11 is 1.8 volts, and if a 5 volt signal is applied to row-select line 21/ then the voltage appearing on bit line 16 would be 4.4 volts and the voltage appearing on bit line 17 would be 3.2 volts. In such a case, the voltage appearing on bit line 16 could be considered to be a binary 00 and the voltage level appearing on bit line 17 could be considered to be a binary 01. If the threshold of transistor 10 were adjusted to be 3.0 volts and the threshold voltage of transistor 11 were adjusted to be 4.2 volts, then when a 5 volt signal is applied to row-select line 21, the voltage level appearing on bit line 16 could be considered to be binary 10 and the voltage appearing oh bit line 17 could be considered to be binary 11. In this last example, with the threshold of 4.2, transistor 11 might appear to be an open circuit. However, in the preferred embodiment, it is preferred to have a transistor in each cell location and adjust the threshold to achieve the desired result as opposed to having an open (or incomplete) device in a certain storage location to represent a predetermined logic level or binary output. By having a transistor in each storage location and having all the transistors of equal physical sizes, then the parasitic capacitance 18 associated with bit line 16 will be the same as the parasitic capacitor 19 associated with bit line 17. By having the same parasitic capacitance on each of the bit lines, then the sensing and readout operation becomes easier to perform.

Bit line 16 is shown as coupled to a reference voltage illustrated as ground by transistor 23. Bit line 17 is coupled to ground by transistor 24. The gate electrodes of transistors 23 and 24 are connected to a pre-charge line. When a precharge signal enables transistors 23 and 24, then the bit sense lines of the memory array are all discharged to ground. A transistor 29 couples bit sense line 16 to an output line 32. Output line 32 goes to a sense amplifier (not shown in FIG. 1). Bit line 17 is coupled to output line 32 by a transistor 28. Transistor 29 has its gate electrode connected to column-select line 30. Transistor 28 has its gate electrode connected to column-select line 31. Output line 32 is coupled to ground by transistor 25 which has its gate electrode connected to the precharge line. During precharge, the parasitic capacitance associated with output line 32 is discharged to ground by transistor 25. Those persons skilled in the art will realize that in order to readout the memory location having transistor 10 that row-select line 21 and column-select line 30 must be selected. In the same manner, the storage locations connected to bit line 17 will be selected when their associated row-select line is enabled along with column-select line 31.

In FIG. 2 a read-only memory is shown in skeleton or abbreviated form having only two storage locations 40 and 40'. However, it will be understood that a typical memory array will have many more storage locations. Storage location 40 has a field effect transistor connected in a source follower configuration. The drain electrode of the transistor in storage location 40 is connected to voltage terminal 41 and its source is connected to bit line 44. Its gate is connected to row-select line 42. The source follower configured transistor in storage location 40' has its drain electrode connected to voltage terminal 41 and its source electrode connected to bit line 44. The gate electrode of the transistor in storage location 40' is connected to row-select line 43. Bit sense line 44 is connected to a sense amplifier 46. Sense amplifier 46 provides three outputs. The absence of a signal on the three outputs will be taken as implying one state of a possible four states existed in the selected storage location. Decoder 47 receives the three outputs from sense amplifier 46 and decodes the three outputs to provide bit 1 on output 48 and bit 2 on output 49 of a two bit binary output. A two bit binary signal is capable of four states.

A portion of a memory chip is shown in abbreviated form in FIG. 3. Shown in FIG. 3 is the location of four programming mask openings useful in modifying the threshold voltage of underlying transistors. In a preferred embodiment, bit lines 50 and 51 are metal, while row select lines 52, 53, 54, 55 and 56 are polysilicon lines commonly called poly lines. The source area of two adjacent transistors is located between lines 55', 56', 60' and 61'. Connection of this source area to bit line 50 is through preohmic 62. The area between row lines 54 and 55 basically defines the drains for the transistors having gate electrodes connected to row lines 54 and 55. The drains located between the row lines are interconnected. Area 61 and area 63 do not form electrodes for any of the transistors but serve as isolation regions between sources of the transistors located adjacent to these areas. Areas 65, 66 , 67 and 68 represent programming mask areas that may be used to modify the threshold voltages of transistors within the areas 65 through 68. Each programming mask will not necessarily have openings as represented by areas 65 through 68. In addition, it will be understood that if a programming mask area is not needed that the adjacent areas will extend up to the unneeded area. A space is illustrated between areas 65, 66, 67 and 68 only for purposes of clarity in the drawing. There are many more bit lines, row lines, and transistors in a memory array than those shown; however, the pattern repeats itself and therefore nothing is gained by illustrating an entire memory programming mask.

If the programming mask does not have an opening over a memory location, it means that the transistor in that memory location will have a first threshold voltage. A transistor located under an opening in the programming mask will have a second threshold voltage. To obtain additional threshold voltages a second programming mask is required, If the second programming mask has an opening over a transistor that was not modified by the first programming mask then a third threshold voltage is obtained for that transistor. If an opening in the second programming mask is over a transistor that was modified by the first programming mask, then a fourth threshold voltage is obtained. This procedure of using two different programming masks provides a memory which can store four different states in a given memory cell location.

By now it should be appreciated that there has been provided a read-only memory array having cells with more than two states wherein each memory location can have a transistor thereby providing equal capacitance on all the bit sense lines. Process variations which affect parasitic capacitances will not disrupt the operation of the read-only memory array since all parasitic capacitances would be affected somewhat equally. By having a transistor in each storage location there is no need to have a mask operation to provide complete transistors in one storage location while not providing complete transistors in yet other storage locations. Instead a mask operation can be used to shift the threshold voltage levels of preselected storage, locations. By using the same size transistors in all storage locations regardless of which voltage level is stored therein , the transistors can be made smaller thereby resulting in an overall smaller memory array. By having the transistors smaller, the circuit will tend to operate faster. Also, by having the capacitance of the bit lines constant, the circuit speed will be more constant and easily predictable. Since memory devices can all be made of a minimum size, they will draw a minimum amount of current and hence result in a memory array which requires less operating power.

Claims

1. A read only memory having a plurality of storage locations arranged in an array, comprising: a first field effect transistor having a drain, a source, and a gate electrode; at least one bit line coupled to the source of the first field effect transistor; and at least a second field effect transistor having a source coupled to the at least one bit line, the at least a second field effect transistor also having a gate and drain electrode, the drain electrodes of the field effect transistors being coupled to a voltage source terminal and the gate electrodes of the transistors being used to receive select signals, and further wherein the first field effect transistor and the at least a second field effect transistor are substantially the same physical size with different threshold voltages so that different voltage levels will appear on; the bit line from the different field effect transistors when enabled by a substantially equal amplitude select signal.

2. The read only memory of claim 1 wherein the different threshold voltages are achieved by ion implantation.

3. A memory array having a plurality of storage locations connected to bit lines wherein a majority of the storage locations each has a field effect transistor and each field effect transistor is of substantially equal size, the field effect transistors being connected in a source follower configuration and at least two of the field effect transistors having a different threshold voltage to allow storing at least two binary bits of information in each of the storage locations.

4. The memory array of claim 3 wherein each of the field effect transistors has a source electrode which is coupled to an associated bit line and each field effect transistor has a drain electrode coupled to a voltage potential terminal.

5. A method of providing a digital memory having a plurality of storage locations wherein some of the storage locations are capable of storing more than one digital bit of information, comprising: providing a field effect transistor in each of at least two of the storage locations; connecting the field effect transistors in a source follower configuration; and shifting threshold voltage of at least one of the field effect transistors so that in the source follower configuration the at least one field effect transistor will provide a lower voltage out of its storage location when the at least one field effect transistor is enabled.

6. The method of claim 5 wherein the shifting of threshold voltage is accomplished by ion implantation.

7. A read only memory having storage locations capable of storing more than one bit of information in at least one of the storage locations, the read only memory comprising: a first field effect transistor located in one storage location and having a first threshold voltage, the first field effect transistor being connected in a source follower configuration; a second field effect transistor located in another storage location and having a second threshold voltage and being equal in physical size to the first field effect transistor, the second field effect transistor being connected in a source follower configuration; and a third field effect transistor located in yet another storage location and having a third threshold voltage and being equal in physical size to the first field effect transistor, the third field effect transistor being connected in a source follower configuration, wherein a difference between the first, second, and third thresholds provides capability to store more than one bit of information in each of the storage locations.