Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers

Definitions

• the present invention relates to power amplifiers, and more particularly to pulse width modulated signals.
• the present invention relates to a power amplifier that efficiently amplifies (P WM signal).
• a so-called class D amplifier is known as a power amplifier that amplifies a signal. Since such a class D amplifier operates in the output stage transient converter ⁇ switching mode, there is little heat generation in the output transistor and it is suitable for small and large output. It is used as a power amplifier. Generally, the higher the switching frequency, the better the efficiency. Therefore, as a switching transistor, a field effect transistor that can operate at high speed is used. Hawk is used.
• the electric field effect type transistor for power amplification has a drawback that it is more expensive than the bipolar type transistor. _
• the bipolar transistor has a drawback in that efficient switching of power cannot be performed because the switching frequency cannot be set higher than the carrier storage effect.
• the first object of the present invention is to provide a power amplifier which eliminates the above-mentioned drawbacks.
• Another object of the present invention is to provide a power amplifier that uses a boiler-type transistor in the power amplification stage to perform efficient amplification. .
• the power amplifier is a pulse width modulation signal generation circuit proportional to the amplitude of the input signal, and the pulse width modulation signal is generated in accordance with the level of the input signal. Equipped with an amplitude modulation circuit that performs amplitude modulation and a power amplification stage that is driven by the pulse width modulation signal that has been amplitude-modulated as described above, it is possible to perform efficient power amplification.
• Figure 1 shows an example of a conventional: P WM power amplifier
• FIG. 2 to 4 are characteristic diagrams for explaining the operation of FIG. 1
• FIG. 5 is a circuit configuration diagram showing an embodiment of the present invention
• FIG. 6 is FIG.
• the signal waveform diagram for explaining the operation of Fig. 5 is shown in Figs. 7 and 8.
• FIG. 5 is a characteristic diagram for explaining the operation of FIG.
• Fig. 1 Prior to the description of the present invention, as an example of such a conventional power amplifier, an example of a grounding type emitter grounding as shown in Fig. 1 will be described. That is, in Fig. 1, [1] is the input signal source that generates the input signal S 2 of substantially a sine wave as shown in Fig. 6B, and (2) is the input signal source.
• a reference signal that generates a clock signal S i such as that shown in Figure A.
• Signal source (3) provides the input signal S 2 based on the clock signal S i.
• (5) to (8) are the transistors that make up the voltage amplification unit, and are the emitter-collector transistors of the final stage transistors (7) (8).
• a charge absorption diode (9) ttO) is connected in parallel to each of the terminals. In the unsaturated type, these diodes are connected between the base and the collector.
• the output signals of the transistors (7) (8) are then the filters (15) consisting of the coils (11), ⁇ ! 2) and the capacitors (13) 114). Through the speaker (16).
• tt7) and .8) are DC power supplies.
• collector currents I C7 and Ics flow, respectively.
• the base current lB7 and IBS when the current does not flow, the collector currents IC7 and Ics also flow at almost the same time.
• the collector current IC7 and the Ics force ⁇ overlap and flow part is generated as shown by the shaded area in Fig. 3. Flows from the transistor (7) to (8), which reduces efficiency.
• the base current For the base current, consider the collector current I c ( max) at high output. Because it is designed, there is too much base current at the time of medium output and it takes time to absorb the stored charge. For example, as shown in Fig. 2, in the past, the operating point at medium output was at the position of P'just before entering the saturation region, but at high output, it was at the position of P which was completely within the saturation region. Moreover, since the base current IBI at the operating point P is fixed and set to operate at the optimum bus setting, the base current IB2 is originally required for medium output. This is because an extra base current will flow due to the difference between the base currents IBI and IB2, and it will take time to absorb the stored charge.
• Fig. 4 shows the ffi force-loss characteristic of the conventional power amplifier set as described above
• the curved line a in Fig. 4 is the characteristic that represents the loss due to V CE (0N)
• the curve. b is
• the curve c is the characteristic that represents the loss due to the operating speed
• the curve c is the characteristic that represents the total of the former two losses.
• the present invention has been made in view of the above circumstances, and provides a power amplifier with low loss and high efficiency.
• FIG. 5 shows the circuit configuration of the present embodiment
• parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.
• a positive level shift circuit (2 and a negative level shift circuit) which shifts the input signal S 2 supplied from the input signal source (1) to the positive side and the negative side, respectively.
• a shift circuit (22) is provided so that the signals S s and S 6 which are shown by broken green in Fig. 6 can be taken out on the ffl force side of ⁇ .
• the output signals S 5 and S s are controlled by the P WM signal S 4 from the comparator (4) to open and close them, and the adder (25 ) And obtain at its output a signal S 7 as shown by the solid line in Figure 6E. Trimming
• the PWM signal S4 is amplitude-modulated by the positive and negative level-shifted signals S5 and S6 and is output to the output side of.
• this amplitude-modulated PWM signal S7 is selectively supplied to the base of the transistor (5 (6)) via the buffer circuit (26).
• the configuration is the same as in Fig. 1.
• the signal S2 is the integrator
• the signal from the reference signal source (2) is shown in Fig. 6A. It is integrated based on such a clock signal Si and converted into a sawtooth signal S3 as shown in Fig. 6C.
• This signal S3 is then fed to the comparator (4), where it is compared with the reference level, and on the side of the ffi force of the comparator (4), see Fig. 6!
• the PWM signal S4 as shown in () is generated.
• the input signal S2 from the positive input signal source (1) is also supplied to the level shift circuits 21) and (22), where the positive and negative level shift circuits are respectively provided. Accordingly, the output sides of the level shift circuits (21) and (22) are applied with the corresponding signals Ss and S6, respectively, as shown by the broken line in Fig. 6E. It is supplied to the circuit (23), (24).
• the switch circuit (231, (24) is controlled by the PWM signal S4 obtained on the ffi force side of the comparator (4) to open and close the switch to selectively select the input signals Ss, S6. That is, when the PWM signal S4 is positive, the switch circuit (23)
• the signal S 7 controls the transistors (), (6), and the corresponding base current is supplied to the final stage transistors (7), (8).
• the base current IB for saturation operation of the transistors (7) and (8) is the transistor current) and the collector current and current of (8).
• the base currents of the transistors (7) and (8) are changed by the signal S 7 that is amplitude-modulated from the P WM signal S 4 by the input signal S 2, and the above ) Try to satisfy the formula.
• Fig. 8 represents the loss due to VcE (ON).
• the characteristic, curve b, represents the loss due to switching speed, and curve c represents the overall characteristic of the two losses. Comparing Fig. 8 with Fig. 4, which shows the loss characteristics of the conventional circuit, it can be seen that the output-loss characteristic of this circuit is greatly improved.
• the P WM signal supplied to the base of the output stage transistor is further amplitude-modulated by the input signal, and the base current is changed within a predetermined range to always output. Since the operating point of the transistor of the stage is controlled so that it is just before entering the torso region, the loss due to VcE (ON) or the loss due to switching speed is caused. It is possible to obtain a high-efficiency power amplifier with low distortion and low distortion.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Amplifiers (AREA)

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• 1980
  • 1980-08-27 JP JP55118200A patent/JPS5742214A/ja active Granted
• 1981
  • 1981-08-25 AU AU75330/81A patent/AU550792B2/en not_active Ceased
  • 1981-08-25 EP EP81902371A patent/EP0058724B1/en not_active Expired
  • 1981-08-25 WO PCT/JP1981/000188 patent/WO1982000739A1/ja not_active Ceased
  • 1981-08-25 US US06/373,507 patent/US4476436A/en not_active Expired - Fee Related

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