WO1982000206A1

WO1982000206A1 - Dual trace electro-optic display

Info

Publication number: WO1982000206A1
Application number: PCT/GB1981/000105
Authority: WO
Inventors: Res Dev Corp Nat
Original assignee: Shanks I
Priority date: 1980-06-27
Filing date: 1981-06-19
Publication date: 1982-01-21
Also published as: GB2101786A; EP0054558A1; GB2101786B; JPS57500848A; CA1174388A

Abstract

Two signal traces are displayed simultaneously on an electro optic display such as a liquid crystal display. The display may be in cartesian format having m X electrodes and n Y electrodes in which case the X electrodes are in strip form whilst each Y electrode comprises two or more interleaved components Ya, Yb. Thus each XY intersection may be addressed by a zero voltage at XYa, or XYb with above threshold voltages elsewhere. A series of m different coded waveforms are generated and applied a different one to each X electrode. The two traces are sampled and converted to digital sample values. Coded waveforms are generated and applied to each Ya Yb electrode contemporaneously with those applied to the X electrodes; the codes being generated are selected from the m different codes and relate to the position of the Y electrodes and the sample value to be displaced. The coded waveforms may be binary codes such as pseudo random codes. A priority encoder allocates a priority to sample values of the two trace signals.

Description

DUAL TRACE ELECTRO-OPTIC DISPLAY

This invention relates to apparatus for displaying two waveforms or traces simultaneously.

Conventionally wavefoms are displayed on cathode ray tubes in which a stream of high energy electrons is swept across a phosphor screen where it impinges and causes a visible glow. It is possible to make such tubes very small e.g. down to about 3cm diameter or diagonal but their power consumption is still high for a truly nortable display. Also high voltages e.g. ~ 1 to 4kV are required and the accuracy and resolution of the information displayed may be degraded compared to a larger tube.

One type of electro-optic display that has the advantage of low power consumption and low operating voltage is the liquid crystal display device. This typically comprises a thin, e.g. 12 /um , layer of liquid crystal material contained between glass plates coated on their inner surfaces with el ectrodes at least one of which is transparent e.g. Stannic Oxide. These electrodes may be arranged in the form of strips with those on one plate orthogonal to those on the other plate, i.e. a matrix of row and column electrodes, so forming a plurality of intersections. The electrodes may also be arranged to display information in polar co-ordinate form or in any suitable set of curvilinear co-ordinates. By applying selected electric voltages to the electrodes the liquid crystal material at their intersection is caused to change its optical property e.g. to go from light scattering to clear or between transparent and opaque states. Each area of intersection may be termed an element. Thus with the application of suitable voltages at a plurality of intersections, elements can collectively display information, for example a waveform can be displayed. One method of applying the voltages is to use signals which differ from one another by a small phase difference and applying the same phase to a particular row and to particular column electrodes with different phases elsewhere. In thi3 method all intersections in a particular column are 'on' except that one at the particular row and column. This is described in co-pending U.S. Patent No. 1,559,074, U.S. Patent No. 4,127,848.

Another type of electro-optic display that can be addressed in matrix form is the a.c. electroluminescent display in which the application of an alternating voltage across a doped phosphor layer causes light emission.

A problem common to matrix addressing is that the intersections not required to display information must receive voltages suitable different from the intersections required to shew information. This problem is eased is the information required to be displayed is in the form of a single valued trace e.g. a sine waveform. In this case each row and column electrode can be addressed simultaneously with its appropriate waveform. However for a 127 x 128 element display this requires at least 128 different waveforms. In the invention described in U.K. Patent No. 1,559,074 a master waveform is divided into 128 waveforms whose minimum phase difference is 2π/l28. Alternatively a poly frequency (e.g. 128 different frequencies) or poly-pulse width (e.g. 128 pulse widths) may be used. In U.K. Patent Application No. 2,001,794 binary or multi-level coded waveforms are used. For a 128 x 128 display, 128 different waveforms are generated and applied simultaneously one to each row electrode and appropriate ones of these 128 waveforms applied simultaneously to the column electrodes. The codes may be for example binary numbers or pseudo random binary sequences of logic ones and zeros. To display two waveform traces simultaneously it is necessary to say use odd columns for one waveform and even columns for the second waveform, thereby reducing display horizontal resolution by a factor of two.

The display of two traces simultaneously using conventional, multiplexing techniques is not possible for large displays, e.g. a 100 x 100 matrix, with present materials since the ratio of the R.M.S. voltage at intersections that are ON to the R.M.S. voltage when OFF is too low e.g. about 1.09 for a 100 x 100 matrix display.

One way of displaying two traces simultaneously on a liquid crystal matrix display with two information elements per column, is described in U.K. Patent Application No. 79 15425, U.S. Serial No. 143,148.

In this specification alternate rows, e.g. even rows, are addressed with different coded waveforms V_i whilst the odd rows receive a steady voltage for a period T₁. During the next period T₂ (equal to T₁) odd rows receive V_i whilst even rows receive the steady voltage. This allows the addressing of two elements per column with the proviso that one element is at an even row whilst the other is at an odd row. For the occasions where a conflict occurs, i.e. two elements should occur at say an even row, a priority encoder decides which trace has priority and moves the element of the inferior trace up or down one row to an odd row.

An advantage of this method is improved appearance. A disadvantage of this method is that the ratio V_ON/V_OFF(RMS value) is

In contrast the ratio V_ON/V_OFF is U.K. Patent 2,001,794 is very much higher since in theory V_OFF is zero, but the appearance is reduced for dual trace display because alternate colums only are used for each trace. An object of this invention is to improve the appearance of a dual trace display, similar to that of U.K. Patent Application

No. 79 15,425, U.S. Serial No. 143,148, with an enhanced V_ON/V_OFF ratio.

As used herein a matrix display is defined as a display having a set of n electrodes and a set of m electrodes forming n x m intersections or elements whereby information to be displayed is obtained by altering the optical property of the display at a desired number of intersections, the alteration in the optical property being achieved by applications of appropriate voltage waveforms to the two sets of electrodes.

As used herein a threshold voltage is that R.M.S. voltage above which a desired observable optical effect occurs, e.g. liquid crystal becomes clear from a scattering state or transparent from an ppaque state or vice versa.

According to this invention a dual trace electro optic display comprises a display cell having a first m-set and a second n-set of electrodes arranged in an m, n matrix, each n electrode being formed by two interleaved components so that each m, n electrode intersection is formedby two separate and independently addressable part3, means for generating m different coded reference waveforms and for simultaneously applying a different one to each m electrode, means for sampling both trace signals and providing digital values of each sample, means for storing each digital sample, and means for selecting and generating ones of the m different codes for simultaneous. application to each n electrode component, the selected code being related to the position of the n electrode and the sample value to be displayed, the arrangement being such that the two traces are collectively displayed at selected electrode intersections where the applied voltage is zero or substantially below a threshold value with the other intersections receiving above a threshold value. for each n electrode one trace element is on one of the interleaved components and the second on the other The display may further comprise a priority encoder for allocating a priority to sample values of the two trace signals.

The m, n matrix may be in X, Y cartesian format, r, θ polar co-ordinate format, or other curvilinear form.

The interleaved electrodes may be of an inter digitated or a meander form with pads of rectangular, triangular, or other suitable shape connected by thin connecting sections. Furthermore each n electrode may be formed by more than two interleaved components.

The m electrode may be of strip form having a width sufficient to cover a pad of one of the components of an n electride or may be of sufficient width to at least cover two pads, one on each component of the n electrode

The means for generating a plurality of waveform may include a sample mpmory, e.g. a random access memory (RAK) , programmed memory e.g. a read only memory (ROM), a pseudo-random number generator, such as a shift register with exclusive OR or exclusive NOR feedback, or a binary code generator such as a binary counter whose outputs in the form of logic zeros and ones form different waveforms for each binary number generated, other forms of 2 level coding or multi-level coding are possible.

The two waveform traces may be sampled through a low pass filter and may be fed to a charge coupled device (CCD) whose filtered or unfiltered output is fed via a sample and hold circuit or directly into an analogue to digital converter (A/D converter). The two traces W₁ , V₂ signals may be read into the CCD (used as an analogue shift register) at a high rate, until the CCD is full, and read out at a slower rate compatible with standard low power low speed A/D converters. This mode of operation of the CCD is known as bandwidth compression. To obtain a Y shift to a displayed waveform W₁, W₂ an offset voltage may be applied to the A/D converter or a Y shift may be obtained by adding or subtracting a digital number to the output of the A/D converter. A X expansion (or contraction) may be obtained by applying a variable gain amplifier or attenuator before the A/D converter or by altering the full scale reference level of the A/D converter.

An X shift or expansion/contraction may be obtained by logic circuits which alters the start or sequence of the read-out of the sample memory used to define the signals to the second set of electrodes.

The waveform traces W₁, W₂ to be displayed may be e.g. sine waves or other continuous or piecewise continuous functions. Alternatively they may be discontinuous functions as for example when it is required to illustrate signal levels multiplexed from a plurality of sensors e.g. temperature or strain gauges. Each sensor output may have a specific position along the X axis of a display end the sensor output value along the Y axis. This may be arranged so that when all sensor outputs are at their correct value the display is all along the one horizontal line i.e. the error between desired and measured sensor outputs is displayed. Furthermore different coloured areas of the display may be associated with desired operating ranges so that if an error signal is displayed it will be coloured green if within certain limits, amber between this range and other limits and red if it lies outside both these ranges.

The invention will now be described, by way of example only, with reference to the accompanying drawings of which:-

Figure 1 is a diagrammatic view of a matrix display; Figure 2 is a sectional view of a liquid crystal cell; Figure 3 is a view of parts of Y or column electrodes used in Figure 2 to an enlarged scale; Figure 4 is a view of column electrodes having a different layout to that of Figure 3; Figure 5 is a block diagram showing a matrix display and drive voltage circuits;

Figure 6 is a circuit diagram for a priority encoder shown in Figure 5; Figure 7 is a block diagram of an alternative circuit to that shown in Figure 5; Figure 8 is a circuit diagram for a priority encoder shown in Figure 7; Figures 9, 10 are different forms of Y electrodes that may be used in place of those shown in Figures 3, 4.

Figure 1 shows in diagrammatic form a matrix display arranged in cartesian co-ordinates. It has X₁ to X_m row electrodes and Y₁ to

Y_n column electrodes, voltage V_i (i is an integer 1 to m) is applied continuously to each X electrode and selected ones of V_i are applied to the Y electrodes continuously. Information is collectively displayed by the circled XY electrode intersections where the voltage difference is zero, the OFF state, with all other intersection receiving a voltage above threshold, the ON state.

The voltage 7. may be binary coded waveforms having a common period T divided into N bits each bit having a logic zero volts or a logic one of positive voltage. This gives 2 possible waveforms with a minimum difference between two waveforms V_i and V

The waveforms may be of period T divided into L bits (L > N) in which case 2^L waveforms are possible. If 2^N out of 2^L waveforms are chosen such that each waveform is at least p bits different from the others. The minimum difference between V_i and V_j is then

Alternatively the waveforms may be pseudo random binary coded wave— forms. These have the property that

Figure 2 shows a cross section through a matrix XY liquid crystal cell 1 with Figure 3 showing details of the Y or column electrodes in detail. The cell 1 comprises two glaβs plates 2, 3 carrying spaced electrodes 4, 5 arranged in a matrix format and formed by conventional photolithographic processes. The X or row electrodes 4 are stripes of uniform width whilst each Y or column electrode 5 is in the form of two Y_a, Y_b interdigitated structures spaced apart and electrically isolated from one another. Each Y_a, Y_b structure is shown to be a series of rectangular pads 11, 12 joined by a thin connecting link 13, 14. The column electrodes 4, 5 may be of aluminium or silver to act as a diffuse reflector at the rear of the cell. Alternatively the Y electrode 5 nay be of tin oxide or' indium tin oxide possibly with the thin connecting link parts 13, 14 metallised, e.g. with silver, gold, or aluminium, deposited by vacuum evaporation techniques. As shown the width of each X row electrode 4 is sufficient to lie across one nad 11, on a Y_a electrode and onepad 12 on a Y electrode. A spacer ring 6 maintains the plates 2, 3 about 8 tia apart, an epoxy resin glue fixes the plates 2, 3 and spacer 6 together. The plates are coated with a thin layer of a surfactant e.g. lecithin, to give homeotropic alignment of the liquid crystal molecules (i.e. the director) at the surfaces. Between the plates 2, 3 is a cholesteric liquid crystal material 7 incorporating a dichroic dye. Suitable materials are: E18 (nematic) with about 4% CB 15 (cholesteric) (both materials are obtainable from 3.D.H. Chemicals Ltd.,. Poole, Dorset) and one or more of the following pleochroic dyes:

Such a cell operates by the dyed phase change effect in which the liquid crystal material changes from a light absorbing (OFF) state to a light transmissive (ON) state on application of an above threshold voltage.

The display may be observed 8 by light transmission using natural, fluorescent or an electric light 9 behind the display or by projecting an image of the display 1 onto a magnifying lens or mirror or a reflecting screen. "Alternatively a reflector 10 may be placed against the outer surface of plate 3 (or the inner surface roughened and βilvered as described in U.K. Patent No. 2,028, 529A) and the display observed by reflected light.

The display of Figures 2, 3 may also use a nematic e.g. E18 or E18 and 150 C15 (B.D.H. Chemicals Ltd) long pitch cholesteric mixture as a twisted nematic cell or Schadt & Eelfrich cell.

The twisted nematic cell comprises a thin e.g. 12 um thick, layer of nematic liquid crystal material contained between two glass plates which have been unidirectionally rubbed to align the liquid crystal molecules and arranged with the rubbing directions orthogonal and so that the director in the centre of the layer has a finite tilt. This results in a twisted molecular structure which rotates plane polarised light whose E vector lies parallel or perpendicular to the optical axis of the liquid crystal at the surface of the cell in the absence of an electric field and when a voltage (preferably a.c. 25Hz-100kEz) above a threshold (typically 1 volt for a 12 am thick layer) is applied the molecules are re-orientated and the layer ceases to rotate plane polarised light. The cell is placed between polarisers with their optical axes parallel or crossed so that light transmission or extinction is obtained by switching the voltage on or off. Small amounts e.g. 1% of a cholesteric material may be added to the liquid crystal material, also small amounts of a dichroic dye may be added in which case the twist angle may be zero and one or both polarisers is omitted from the display.

As an alternative to rubbing, the plates may have magnesium fluoride or silicon monoxide deposited by a technique known as oblique evaporation with an angle of incidence of an evaporating beam to the plates of around 5 and/or 30 as described in U.S. Patent Specification No. 1,454,296.

A liquid crystal cell responds to the RMS value (rather than the instantaneous value) of a wavefora providing the period is shorter than the sum of the cell turn ON and turn OFF time. If the waveform period is longer the liquid crystal can turn ON and OFF within one waveform period. For a twisted nematic cell this typically means that the waveform fundamental frequency is greater than 25 Hz.

When a twisted nematic liquid crystal display is used the polarisers may be coloured differently in different parts of the display. Apparatus for applying waveforms to a matrix display will now be described with reference to Figures 5, 6.

As shown a liquid crystal cell 1 has X Y electrodes arranged in cartesian co-ordinate format with each Y column electrode in two parts, as detailed in Figure 3 or 4, and each X row electrode as shown in Figure 3 or 4. For example the cell 1 may be a 128 column by 126 row matrix giving 128 x 126 x 2 electrode intersections. Such a cell 1 requires a different code 7. for each row plus at least one code to allow no information to be written on any selected column.

All row electrodes 4 are connected to a row or reference waveform generator 20. This may be a shift and store bus register fed from a programmed memory, binary counter, or pseudo random coda generator such as a shift register with modulo two feedback. The function cf the generator 20 is to generate a different code 7. for each X_i. electrode under the control of a timebase and timing circuitry controller 21 itself controlled by a master clock 22.

All column electrodes 5 are connected to a column waveform generator and selector 23. Its function is to select ones of the codes V_i for application to each Y_a, Y_b electrode independently, the selected code being related to the value of waveform sample to be displayed. Control is from the time controller 21.

Details of code V_i generation are known e.g. from U.K. Patent

No. 2,001,794A, and Displays, April 1979, pp. 33-41, Shanks et al.

Signals W₁ , W₂ to be displayed are fed serially through variable level amplifiers 24, 25 sample and hold circuits 26, 27, A/D convertors 23, 29, a priority encoder 30, and memory 31 into the column waveform selector 23. A trigger circuit 32 i3 connected between the amplifiers 24, 25 and sample and hold circuits 26, 27. All components are controlled by the timing controller 21. Information is loaded as follows: The signals W₁, W₂ to be displayed are amplified, or attenuated, independently as required by the amplifiers 24, 25. The trigger circuit 32 is armed by the time controller 21 so that when an appropriate trigger point is reached by a chosen waveform W₁ or W₂ the trigger circuit 32 fires and signals the time controller 21 to clock the sample and holds 26, 27,

A/D converters 28, 29, priority encoder 30 and memory 31 until the memory is full. No further information is entered until updated information is required whereupon the above sequence is repeated.

As previously noted each X electrode 4 crosses a pad 11, 12 fbrom a Y_a andY_b electrode. Since information i3 displayed by a-mlying the same code V_i to both an X and a Y electrode and since each X electrode receives a different code only one OFF element per Y_a or Y_b electrode is possible. This means that, to display two OFF elements per column, one element is formed by a Y_a electrode and the other by a Y_b electrode. It follows that there may be occasions when two samples should be displayed at positions along the same Y_a , or Y_b electrode. Since this is not possible it is desirable to give priority to one sample value and move the other one position (a ½ row electrode width) up or down. Priority can be accorded in a number of ways: W₁ or W₂ may have priority for alternate columns, or for alternate frames, or one may have continual priority. (Less satisfactorily, V. may be displayed only on Y_a elements and W₂ only on Y_b elements in which case no priority encoder, 30, is required.)

This is achieved for the circuit of Figure 5 by the priority encoder having inputs from the A/D converters 28, 29 and having an output to the memory 31. The priority encoder 30 checks to see if two sample values at each column would both occur on a Y_a or Y_b column elements. If so it shifts one of the sample values one column element up or down in a manner related to the quantisation noise from the A/D converter. Figure 6 shows details of a priority encoder 30 when used with 8-bit numbers of which only 7-bits are used for the display 1. It comprises a first and a second 8-bit full adder 38, 39 having two sets of 8-inputs A_O to A₇ and B_O to B₇. Inputs A_O to A₇ on the first adder 38 are from outputs Q_O to Q₇ from the A/D converter 28 representing sample values from W₁. Likewise inputs A_O to A₇ on the second adder 39 represent W₂. of the adders inputs B_O to B₇ only B₁ are used and are connected to OR gates 40, 41. An exclusive

NOR gate 42 has two inputs, one connected to the A/D converter 28, Q₁ output and the other to the other A/D converter 29 output Q₉ for the purpose of checking whether both the trace samples fcrmed by the numbers on A. to A₇ of the adders 38, 39 are simultaneously odd or even. The exclusive NOR gate 42 output is connected through an inverter 43 to both OR gates 40, 41 and thence to the adders inputs B₁, B₁. These OR gates 40, 41 have an input connected to the least significant bit of their associated adders 8 bit word input. First and second AND gates 44, 45 each have three inputs, and an output which is connected to the CARRY irsut C_in of the first and second adder 38, 39. The first and second AND gates 44, 45 have one input connected to the least significant bit of the

8-bit input to their associated adder; another input connected in common to the exclusive NOR gate 42 output and another input connected to input signals O ∅. Innut signals ∅ and ∅ are also connected to the OR gates 40, 41 and are selected by means (not shown) to determine which of W₁ or W₂ is to be dominant during each sample period.

The first adder 38 has an "8-bit output on outputs F_O to F₇. The least significant bit F_O is left unconnected whilst bits F₁ to F₇ are connected to a 7 x 2:1 multiplexer 46 having a 7-bit output Q_O to Q₆. The second adder 39 has its outυuts C ₁ to C ₇ connected to the multiplexer 46. This multiplexer 46 is controlled through input C by the output of F₁ and a signal Z (a square wave of frequency twice the conversion rate provided by the timebase circuitry) through an exclusive NOR gate 47 to determine which of the intputs F or G pass to the output Q. The multiplexer 46 outputs Q_O to Q₆ form the outputs of the priority encoder 30 shown in Fiaure 5. Table 1 shows the priority encoder 30 for all combinations of the two least significant bits in the two 8-bit words to the adders 38, 39 reresentin both trace samles.

H = W₁ and W₂

The 7 bit numbers from the priority encoder are received by the data inputs of the memory 31 asd stored.

In operation the traces W₁, W₂ to be displayed are sampled 26, 27, digitised 28, 29 and placed in appropriate positions in the memory 31 as determined by the priority encoder 30. The coded reference X waveforms are generated 20 and applied simultaneously to each X row electrode 4, a different code on each electrode 4. The column generator 23 reads each store position in the memory 31 and generates one of the 7_i different codes for each Y_a , and Y_b electrode, the code generated being related to the Y position and to the value of the sample. As a result two traces. W₂ , W₂ are collectively displayed at XY_a , XY_b electrode intersections where zero voltage occurs, i.e. the same code 7. is applied to both X and Y_a or Y_b electrodes.

Figures 7, 8 show an alternative form of apparatus. Signals W₁ , W₂ are fed through amplifiers 24, 25, a 2:1 multiplexer 33, a sample and hold circuit 34, an analogue to digital (A/D) converter 35, a priority encoder with latch 36, to a memory 31. Other components are similar to those of Figure 5 and are given like reference numerals.

Signals W₁ , W₂ are variable amplified, or attenuated as required by amplifiers 24, 25, and fed seα_uentially through the multiplexer 33. Thereafter W₁ , W₂ are sampled 34, digitised in the A/D converter 35, allocated priority in the priority encoder 36 and read sequentially into the memory 31. Control of the trigger 32, multiplexer 33 sample and hold 34, A/D converter 35, priority encoder 36 and memory 31 is by the time controller 31 .

The priority encoder 36 is similar to that of Figure 6 with the addition of a latch because the traces W₁ , W₂ samples enter the priority encoder sequentially. Figure 8 shews details of the priority encoder 36 when used with multiplexed 8-bit numbers of which only 7-bits are used for the display. During the first half of the sample period, W₂ is output from the A/D converter 35 and held in the 8-bit latch 37 by means of the signal Y from the timing controller 21. The latch 37 holds this value of W₂ during the second half of.the sample period during, which the A/D converter 35 outputs the correspondingW₁. value from the other channel. The priority encoder uses this W₁ value and the latched W₂ value in the same way as before and during this second half of the sample period the signal Z (which is now a pulsed waveform from the time controller 21 ) goes high then low (or vice versa) to output W₁ and W₂ in appropriate sequence to be written into appropriate locations in the memory 31. Once the memory is loaded operation of Figure 7 is the same as for Figure 5.

The circuit of Figure 7 may be modified by arranging the priority encoder 36 after the memory 31.

Figure 9 shows in schematic form a column electrode arranged in a meander configuration. As shown four components are used to form one column electrode so that four traces may be displayed. Each comnonent Y_a , Y_b. , Y_c , Y_d, of the Y electrodes Y_a, Y_b , Y_c, Y_d, has a rectangular pad 50, 51, 52, 53 arranged in a column with interconnecting βtrips 54, 55, 56, 57. The X row electrodes are wide enough to overlie four pads 50, 51, 52, 53. ¥ith the meander type of configuration more or less than four such components may be used for each column.

Figure 10 shows column electrodes arranged in two parts Y_a , Y_b in a meander configuration with reduced separation between adjacent columns. EachY_a, Y_b comnonent comorises rectangular pads 58, 59 with thin interconnecting strips 60, 61.

Claims

Claims: -

1. A dual trace electro optic display comprising a display cell having a first m-set and a second n-set of electrodes arranged in an m, n matrix, each n electrode being formed by at least two interleaved components so that each m, n electrode intersection is formed by at least two separate and independently addressable parts, means for generating m different coded reference waveforms and for simultaneously applying a different one to each m electrode, means for sampling both trace signals and providing digital values of each sample, means for storing each digital sample, and means for selecting and generating ones of the m different codes for simultaneous application to each n electrode component, the selected code being related to the position of the n electrode and the sample value to be displayed, the arrangement being such that the two traces are collectively displayed at selected electrode intersections where the applied voltage is zero or substantially below a threshold value with the other intersections receiving above a threshold value, for each n electrode one trace element is on one of the interleaved components and the 3econd on the other.

2. A display according to claim 1 wherein the two interleaved components of each n electrode ire interdigitated.

3. A display according to claim 1 wherein each n electrode is formed of at least two components arranged in a meander form.

4. A display according to claim 2 wherein the interdigitated electrodes comprice rectangular pads with thin interconnecting sections.

5. A display according to claim 2 wherein the interdigitated electrodes comprise triangular pads with thin interconnecting sections.

6. A display according to claim 1 and further comprising a priority encoder for allocating a priority to sample values of the two trace signals.

7. A display according to claim 1 wherein the display cell is a liquid crystal display cell.

8. A display according to claim 7 wherein the liquid crystal cell is arranged to provide a progressive molecular twist across the liquid crystal material layer.

9. A display according to claim 7 therein the liquid crystal cell includes a cholesteric liquid crystal material.

10. A display according to claim 7 wherein the liquid crystal material includes a dye.

11. A display according to claim 1 wherein the m different codes are binary coded waveforms.

12. A display according to claim 11 vherein the binary coded waveforms are, for at least a portion of their sequence, pseudo random codes.

13. A display according to claim 1 wherein the means for sampling both trace signals includes means for reading in samples at a first rate and read out at a second and slower rate.

14. A display according to claim 1 wherein the means for selecting and generating codes for application to each n electrode component includes a programmed memory whose inputs are the digital value of each sample.

15. A display according to claim 1 wherein the means for sampling the two traces signals includes charged coupled devices,

16. A display according to claim 1 wherein the two trace signals are sampled simultaneously.

17. A display according to claim 1 wherein he two trace signals are sampled sequentially.