Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
  • G11C11/419—Read-write [R-W] circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/408—Address circuits
  • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Definitions

• the present invention pertains to semiconductor integrated circuits and more particularly to a circuit for reducing the effect of capacitive coupling between bit lines and unselected row lines in a memory circuit.
• each of the memor cells is accessed by applying a high voltage to a row li that drives an access transistor for the addressed memor cell.
• the row line is activated by a decoder circuit which is driven in response to a multi-bit memory addres signal.
• the row line selected by the address is driven to a high level by the decoder circuit.
• the capacitive coupling between these bit lines and the floating row lines causes these floating row lines to be capacitively charged positive. This positive voltage can turn on the access transistors for the memory cells connected to the floating row lines. This inadvert activation of memory cells can destory the data state stored therein. Thus, when these memory cells are later accessed, erroneous data can be read out.
• a quiet line flip-flop for a semiconductor memory for reducing capacitively coupled noise on a group of row lines.
• the quiet line circuit includes means for precharging a first node to a first state in response to a precharge signal where the first node corresponds to the group of row -lines.
• Further circuit means are included for providing a conductive path between each of the row lines and a low voltage node when the first node is charged to a first state.
• Further circuitry is provided for opening the conductive path between the lines and the low voltage node when at least one of the lines is forced to a voltage above a preset voltage.
• FIGURE is a schematic illustration of quiet line flip-flop used in conjunction with a group of row lines in a semiconductor memory.
• a representative embodiment of the circuit of the present invention is illustrated in the FIGURE.
• a quiet line flip-flop 10 is used in conjunction with a group of row lines 12 and 14 within a semiconductor memory.
• Row line 12 receives a driver signal RDl which charges the row line to a high state thereby turning on a memory cell 16 which transmits and receives data through a bit line 18.
• the row line 14 likewise receives a row driver signal RD2 which activates a memory cell 20 for transferring data states through the bit line 18.
• the row driver signals RDl and RD2 are generated in response to a memory address as described in co-pending patent application Serial No. , filed to R. Proebsting.
• the quiet line flip-flop 10 includes a discharge transistor 22 which has the gate terminal thereof connected to the row line 12, the source terminal thereof connected to a common ground node 24 and the drain terminal thereof connected to a precharge node 26.
• the gate terminal of a discharge transistor 28 is connected to row line 14, the source terminal thereof is connected to ground and the drain terminal thereof is connected to node 26.
• a row hold down transistor 30 has the drain terminal ' thereof connected to the row line 12 and the source terminal thereof connected to the common ground -node 24. The gate terminal of row hold down transistor 30 is connected to node 26.
• a second row hold down transistor 32 has the drain terminal thereof connected to row line 14, the source terminal thereof connected to the common ground node 24 and the gate terminal thereof also connected to node 26.
• a precharge transistor 34 is connected to receive a precharge signal P at the gate terminal thereof, the source terminal thereof is connected to node 26 and the drain terminal thereof connected to a power terminal 36 which receives the supply voltage Vcc Stray capacitive coupling between the bit line 18 and the row line 12 is indicated by capacitor 40. Stray capacitive coupling between the bit line 18 and the row line 14 is indicated by capacitor 42.
• the precharge signal P is replaced by a connection 46 from the gate terminal of transistor 34 to the power terminal 36 which receives the supply voltage V . When the connection 46 is in place there is effectively provided a resistive path between V and node 26.
• transistors 22 and 28 When transistors 22 and 28 are turned off, node 26 is charged through transistor 34 and transistors 30 and 32 are turned on. But when either of transistors 22 or 28 is turned on, the voltage on node 26 is pulled sufficiently low to turn off transistors 30 and 32. In this condition there will be a current flow path through transistor 34 and the one of transistors 22 and 28 which is turned on. When the voltage on the row line holding transistor 22 or 28 on is removed, both of transistors 22 and 28 are rendered nonconductive and node 26 is again -charged through transistor 34 to . turn on transistors 30 and 32.
• the row lines 12 and 14 are two row lines within a large array of row lines.
• a voltag can be capacitively coupled into the row lines 12 and 14 by the stray capacitance indicated by capacitors 40 and 42.
• This capacitively coupled voltage can inadvertently turn on the memory cells 16 and 20 and destroy the data states stored therein.
• the circuit 10 is precharged by signal P befor the start of each memory cycle.
• the signal P goes to a high voltage state which drives transistor 34 conductive and precharges node 26 to a high voltage level.
• the high voltage level on node 26 turns on transistors 30 and 32
• the quiet line circuit 10 thus must be deactivated when it is desired to charge one of the row lines 12 or 14.
• the transistors 30 and 32 are fabricated to provide a low enough impedance to limit the voltage on the row lines due to capacitive coupling, but to have a high enough impedance to be overcome by the row driver signals.
• the signals RDl and RD2 drive the row lines with a typically lower impedance than that of the transistors 30 and 32.
• Prior quiet line flip-flops have been provided in semiconductor memories, but such circuits have included individual precharge nodes for each of the row lines.
• the use of precharge nodes for each row line often causes the quiet line flip-flop to become the limiting factor in how closely spaced the row lines can be configured. If the spacing of the row lines is increased, this results in a substantial increase- in circuit area.
• the circuit of the present invention provides a quiet line circuit for a plurality of closely spaced row lines and can be implemented such that the overall memory arra area is reduced. A reduction in the area used in an integrated circuit offers many advantages including greater yield and lower production costs.
• the quiet line flip-flop 10 shown in the FIGURE is disabled when the voltage level on either of the row lines reaches the threshold voltage of its discharge transistor.
• the voltage level at which the node 26 is discharged can be preset to any desired value by the use of well known circuit techniques.
• the circuit of the present invention can be utilized in any application where it is desired to hold a plurality of lines at ground to eliminate undesired electrical noise. But when it is desired to drive one of the lines to a high voltage state, the circuit is deactivated to permit such action.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Static Random-Access Memory (AREA)
• Dram (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

Family

ID=22154383

Family Applications (1)

Country Status (3)

Cited By (1)

Citations (8)

• 1980
  • 1980-06-02 JP JP81500476A patent/JPS57501003A/ja active Pending
  • 1980-06-02 WO PCT/US1980/000675 patent/WO1981003570A1/en not_active Application Discontinuation
  • 1980-06-02 EP EP19810900233 patent/EP0052101A1/en not_active Withdrawn

Patent Citations (8)

Non-Patent Citations (2)

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