WO1981003240A1 - Lift-off process - Google Patents
Lift-off process Download PDFInfo
- Publication number
- WO1981003240A1 WO1981003240A1 PCT/US1980/000544 US8000544W WO8103240A1 WO 1981003240 A1 WO1981003240 A1 WO 1981003240A1 US 8000544 W US8000544 W US 8000544W WO 8103240 A1 WO8103240 A1 WO 8103240A1
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- WIPO (PCT)
- Prior art keywords
- layer
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- over
- masking
- masking layer
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
Definitions
- This invention relates to a method of depositing thin films, particularly thin metallic films useful in the fabrication of integrated circuits.
- Present trends in the formation of vacuum deposited thin metallic film commonly use chemical etching in the presence of etch-resistant masking layers to provide the selected pattern. This is the traditional photoengraving or photolithographic etching technique.
- photoengraving or photolithographic etching technique is the traditional photoengraving or photolithographic etching technique.
- the art is rapidly approaching a point where such photolithographic etching of deposited film may be impractical for providing the minute resolution required for the fine line work of metallization in such large scale integrated circuitry.
- the disclosed method includes the use of an organic polymeric material deposited on the integrated circuit substrate and an overlying layer of an inorganic material deposited on the integrated circuit substrate and an overlying layer of an inorganic material, preferably metal, having openings in the selected pattern. Openings are formed in the polymeric material by reactive sputter etching utilizing the metallic mask as a barrier. The openings in the polymeric layer are aligned with and laterally wider than the corresponding openings in the metallic maskin-g layer as a consequence of the reactive sputter etching step. Thus, the edges of the openings in the metallic masking layer overhang the edges of the openings in the underlying polymeric layer.
- the thin film to be deposited is then applied over the structure and on the surface of the substrate exposed by the openings in the polymeric material.
- the metallic masking layer and the thin film above the masking layer "lift off” to leave the thin film deposits in the selected pattern on the substrate without "edge tearing" of the desired deposited thin film as the unwanted portions of the thin film are lifted off.
- the invention concerns a method of forming a conductive pattern on a semiconductor substrate, including the steps of depositing a first layer of material having a first etch rate characteristic on the semiconductor substrate, and applying a masking layer having a second etch rate characteristic different from the first and forming a pattern of apertures over the first layer.
- An etching solution is then applied to the body over the masking layer so that the first layer is etched at the apertures to the underlying layer or substrate, thereby creating an undercut underneath the masking layer.
- a metal film is then deposited over the layers so as to create a discontinuous step over the edge of the masking layer, and a dissolving solution is applied which is capable of dissolving the first layer.
- Figures la-Id are diagrammatic cross-sectional views of the structure at successive steps during its fabrication in accordance with the preferred . embodiments of the present invention.
- Figures la-Id show the formation of the composite mask in accordance with the method of the present invention as well as the utilization of this composite mask for lift-off purposes.
- Figure la shows a silicon-on-sapphire configuration that is useful in describing the lift-off technique according to the present invention.
- the figure shows a silicon island on a sapphire substrate.
- the substrate is prepared by first growing a SiO 2 layer 150 to 1500 ⁇ in thickness over the silicon.
- a relatively thin layer of polysilicon (either n- or p+, or undoped) is then applied over the oxide layer by techniques known in the art.
- the polysilicon layer may typically be 0.1 to 0.5 ⁇ m in thickness.
- the polysilicon layer is optional, and is merely used here to illustrate an embodiment of the invention in which there is an underlying layer beneath the composite defined by the present invention.
- a layer of adhesion promoters is provided to promote adhesion of the resist of the polysilicon.
- the wafers are first coated with collodial alumina, rinsed in water, dried, and finally coated with HMDS (hexamethyldisilane).
- Figure lb shows the silicon-on-sapphire composite with a resist/polyimide composite overlying the polysilicon layer.
- the sequence of steps is as follows. First the polyimide is applied, baked for five minutes in an IR lamp, and spun at 7,000 rpm for approximately 30 seconds. Following spinning there is a baking step at 60 minutes in an IR lamp, another baking for 60 minutes at 70oC in an N 2 oven, and a last step of baking 60 minutes at 170oC in a N 2 oven. HMDS is then spun on, followed, by spinning on a positive resist (e.g. HPR204 or ZA1350J). The positive resist is then baked 30 minutes at 70oC in a N 2 oven.
- a positive resist e.g. HPR204 or ZA1350J
- the resist is then exposed by means of a mask to form a desired pattern of apertures on the surface of the composite. Normally 5 to 20% more exposure is required for the present composite than for a single layer of positive resist.
- the resist is then developed using normal operating procedures, following which the polyimide is etched. There are basically two options for etching the polyimide: overdeveloping the resist so that the developer etches the polimide, or an O 2 plasma etch. As a result of the etching of the polyimide, a composite structure is formed such as shown in the cross-sectional view in Figure 1b. It is noted that the polimide must undercut the resist layer such that a negative, (or inward sloping) resist polyimide profile is formed, such as shown in the figure.
- Aluminum may then be evaporated over the surface of the composite so that the thickness of the aluminum formed on the surface is less than or equal to .33 of the total resist-polyimide thickness.
- a discontinuity in the aluminum layer is formed at the negative slope edge of the stencil so that a first portion of the aluminum lies over the resist while a second portion discontinuous from the first portion lies on the surface of the polysilicon.
- MoSi 2 could be used as well .
- the next step is the lift off procedure which is shown in Figure 1c.
- the entire composite shown in Figure lb is soaked in a Dupont thinner or 1-methyl-pyrrolidone for 30 minutes.
- the resist layer and the polymer layer dissolve and while dissolving "lifts off” the portion of the aluminum or MoSi 2 layer which overlies the resist layer.
- a region of MoSi 2 left after the lift-off is shown.
- the wafer and the thinner are placed in an ultrasonic bath for 10 minutes.
- the resulting structure is shown in Figure 1c in which the aluminum or monysilicon is formed on the surface of the polysilicon layer.
- Figure 1d shows a cross-sectional view of the composite structure according to the present invention after removal of the exposed polysilicon layer, leaving the fine-line MoSi 2 and polysilicon pattern on the surface of the SiO 2 layer.
- the semiconductor process according to the present invention can be implemented with various semiconductor technologies and different combinations of known process steps, and that the preferred embodiments illustrated here are merely exemplary.
- the thickness of the layers, depth of penetration of the various zones and regions, and in particular the configuration and distance between the various layers and zones, as well as the concentrations of dopant species, and/or their concentration profiles, can be chosen depending upon the desired properties.
- the present invention is also not restricted to the specific semiconductor materials and circuits described.
- semiconductor materials other than silicon for example A III -B v compounds, or even other solid state materials, such as magnetic bubble domain material may be used.
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- Manufacturing & Machinery (AREA)
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Abstract
A method of forming a conductive pattern on a semiconductor substrate including the steps of depositing a first layer of material having a first etch rate characteristic on an underlying layer of the substrate, and applying a masking layer having a second etch rate characteristic different from the first and forming a pattern of apertures over the first layer. An etching solution is then applied to the body over the masking layer so that the first layer is etched at the apertures to the underlying layer or substrate, and thereby creating an undercut underneath the masking layer. A metal film of a suitable thickness is deposited over the layers so as to create a discontinuous step over the edge of the masking layer. Finally, a dissolving solution is applied which is capable of dissolving the first layer so that the first layer is removed as well as lifting off the metal layer overlying the masking layer, thereby leaving a pattern of metal on the substrate.
Description
LIFT OFF PROCESS
Background of the Invention
This invention relates to a method of depositing thin films, particularly thin metallic films useful in the fabrication of integrated circuits. Present trends in the formation of vacuum deposited thin metallic film commonly use chemical etching in the presence of etch-resistant masking layers to provide the selected pattern. This is the traditional photoengraving or photolithographic etching technique. However, with the continued miniaturization of semiconductor integrated circuits to achieve greater component density and smaller units in large scale integrated circuitry, the art is rapidly approaching a point where such photolithographic etching of deposited film may be impractical for providing the minute resolution required for the fine line work of metallization in such large scale integrated circuitry. An alternative method for forming such metallization is commonly denoted by the term "expendable mask method", "lift-off method", or "stencil method". U. S. Patent No. 3,873,361, issued March 25, 1975 to Havas et al , entitled "A Method of Depositing Thin Film Utilizing a Lift-Off Mask" discloses a lift-off method for depositing thin films which avoids the "edge-tearing" problem and is suitable for use where the lateral widths of the spacing between adjacent deposited metallic lines of the order of 0105 to 0.25 mils. The disclosed method includes the use of an organic polymeric material deposited on the integrated circuit substrate and an overlying layer of an inorganic material deposited on the integrated circuit substrate and an overlying layer of an inorganic material, preferably metal, having openings in the selected pattern. Openings are formed in the polymeric material by reactive sputter etching utilizing the metallic mask as a barrier.
The openings in the polymeric layer are aligned with and laterally wider than the corresponding openings in the metallic maskin-g layer as a consequence of the reactive sputter etching step. Thus, the edges of the openings in the metallic masking layer overhang the edges of the openings in the underlying polymeric layer. The thin film to be deposited is then applied over the structure and on the surface of the substrate exposed by the openings in the polymeric material. When the polymeric material is removed by application of solvent, the metallic masking layer and the thin film above the masking layer "lift off" to leave the thin film deposits in the selected pattern on the substrate without "edge tearing" of the desired deposited thin film as the unwanted portions of the thin film are lifted off.
Other relevant background patents include U. S. Patent No. 4,004,004 which is concerned with a method of lift-off using a three layer system (resist, resin, and resist), and U. S. Patent No. 4,035,206, which discloses a two-layer lift-off system in which the lowest layer is an anodically oxidizable metal .
Summary of the Invention
Briefly, and in general terms, the invention concerns a method of forming a conductive pattern on a semiconductor substrate, including the steps of depositing a first layer of material having a first etch rate characteristic on the semiconductor substrate, and applying a masking layer having a second etch rate characteristic different from the first and forming a pattern of apertures over the first layer. An etching solution is then applied to the body over the masking layer so that the first layer is etched at the apertures to the underlying layer or substrate, thereby creating an undercut underneath the masking layer. A metal film is then deposited over the layers so as to create a discontinuous step over the edge of the masking
layer, and a dissolving solution is applied which is capable of dissolving the first layer. The first layer is thereby removed and the metal layer overlying said first layer is lifted off, thereby leaving a pattern of metal on the substrate. The novel features which are considered as characteristic for the invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
Brief Description of the Drawing
Figures la-Id are diagrammatic cross-sectional views of the structure at successive steps during its fabrication in accordance with the preferred . embodiments of the present invention.
Description of the Preferred Embodiment
Figures la-Id show the formation of the composite mask in accordance with the method of the present invention as well as the utilization of this composite mask for lift-off purposes.
Figure la shows a silicon-on-sapphire configuration that is useful in describing the lift-off technique according to the present invention. The figure shows a silicon island on a sapphire substrate. The substrate is prepared by first growing a SiO2 layer 150 to 1500 Å in thickness over the silicon. A relatively thin layer of polysilicon (either n- or p+, or undoped) is then applied over the oxide layer by techniques known in the art. The polysilicon layer may typically be 0.1 to 0.5 μm in thickness. The polysilicon layer is optional, and is merely used here to illustrate an
embodiment of the invention in which there is an underlying layer beneath the composite defined by the present invention.
Over the polysilicon layer a layer of adhesion promoters is provided to promote adhesion of the resist of the polysilicon. The wafers are first coated with collodial alumina, rinsed in water, dried, and finally coated with HMDS (hexamethyldisilane).
Figure lb shows the silicon-on-sapphire composite with a resist/polyimide composite overlying the polysilicon layer. The sequence of steps is as follows. First the polyimide is applied, baked for five minutes in an IR lamp, and spun at 7,000 rpm for approximately 30 seconds. Following spinning there is a baking step at 60 minutes in an IR lamp, another baking for 60 minutes at 70ºC in an N2 oven, and a last step of baking 60 minutes at 170ºC in a N2 oven. HMDS is then spun on, followed, by spinning on a positive resist (e.g. HPR204 or ZA1350J). The positive resist is then baked 30 minutes at 70ºC in a N2 oven. The resist is then exposed by means of a mask to form a desired pattern of apertures on the surface of the composite. Normally 5 to 20% more exposure is required for the present composite than for a single layer of positive resist. The resist is then developed using normal operating procedures, following which the polyimide is etched. There are basically two options for etching the polyimide: overdeveloping the resist so that the developer etches the polimide, or an O2 plasma etch. As a result of the etching of the polyimide, a composite structure is formed such as shown in the cross-sectional view in Figure 1b. It is noted that the polimide must undercut the resist layer such that a negative, (or inward sloping) resist polyimide profile is formed, such as shown in the figure.
After the etching of the polyimide there is a post bake of the resist.
A high temperature post bake is not recommended for adhesion since it might deform the lift-off profile. It is therefore recommended that temperature less than 100°C be used for the post bake of the resist.
Aluminum may then be evaporated over the surface of the composite so that the thickness of the aluminum formed on the surface is less than or equal to .33 of the total resist-polyimide thickness. A discontinuity in the aluminum layer is formed at the negative slope edge of the stencil so that a first portion of the aluminum lies over the resist while a second portion discontinuous from the first portion lies on the surface of the polysilicon. In place of aluminum, MoSi2 could be used as well .
The next step is the lift off procedure which is shown in Figure 1c. The entire composite shown in Figure lb is soaked in a Dupont thinner or 1-methyl-pyrrolidone for 30 minutes. The resist layer and the polymer layer dissolve and while dissolving "lifts off" the portion of the aluminum or MoSi2 layer which overlies the resist layer. In Figure 1c, a region of MoSi2 left after the lift-off is shown. After the lift-off takes place, the wafer and the thinner are placed in an ultrasonic bath for 10 minutes. The resulting structure is shown in Figure 1c in which the aluminum or monysilicon is formed on the surface of the polysilicon layer. Figure 1d shows a cross-sectional view of the composite structure according to the present invention after removal of the exposed polysilicon layer, leaving the fine-line MoSi2 and polysilicon pattern on the surface of the SiO2 layer.
It will be obvious to those skilled in the art that the semiconductor process according to the present invention can be implemented with various semiconductor technologies and different combinations of known process steps, and that the preferred embodiments illustrated here are merely
exemplary. The thickness of the layers, depth of penetration of the various zones and regions, and in particular the configuration and distance between the various layers and zones, as well as the concentrations of dopant species, and/or their concentration profiles, can be chosen depending upon the desired properties. These and other variations can be further elaborated by those skilled in the art without departing from the scope of the present invention.
The present invention is also not restricted to the specific semiconductor materials and circuits described. For example, it may be pointed out that semiconductor materials other than silicon, for example AIII-Bv compounds, or even other solid state materials, such as magnetic bubble domain material may be used.
Without further analysis, the foregoing will so fully reveal the gist of the present invention that others can, by applying current knowledge, readily adapt it for various applications without omitting features that, from the standpoint of prior art, fairly constitutes essential characteristics of the generic or specific aspects of this invention, and, therefore, such adaptations should and are intended to be comprehended within the meaning and range of equivalence of the following claims. What is claimed is:
Claims
1. A method of forming a conductive pattern on a semiconductor substrate comprising the steps of: depositing a first layer of material having a first etch rate characteristic on said substrate; applying a masking layer having a second etch rate characteristic different from the first and forming a pattern of apertures over said first layer; applying an etching solution to the body over said masking layer so that the first layer is etched at said apertures to said substrate, and thereby creating an undercut underneath the masking layer; depositing a metal film of a suitable thickness over said layers so as to create a discontinuous step over the eάga of the masking layer; and applying a dissolving solution which is capable of dissolving said first layer so that said first layer is removed as well as lifting off the metal layer overlying said masking layer, thereby leaving a pattern of metal on the substrate.
2. A method as defined in Claim 1, further comprising the step of depositing an underlying of material on said substrate prior to depositing said first layer.
3. A method as defined in Claim 2, wherein said underlying layer of material is a polysilicon layer.
4. A method as defined in Claim 1, wherein said first layer of material comprises a single layer of a polymeric material.
5. A method as defined in Claim 1, wherein said masking layer of material comprises a single layer of resist.
6. A method as defined in Claim 1, wherein said metal film comprises aluminum applied by evaporation.
7. A method as defined in Claim 1, wherein said metal film comprises MoSi2
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP19810900532 EP0051598A1 (en) | 1980-05-08 | 1980-05-08 | Lift-off process |
| PCT/US1980/000544 WO1981003240A1 (en) | 1980-05-08 | 1980-05-08 | Lift-off process |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| WOUS80/00544 | 1980-05-08 | ||
| PCT/US1980/000544 WO1981003240A1 (en) | 1980-05-08 | 1980-05-08 | Lift-off process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1981003240A1 true WO1981003240A1 (en) | 1981-11-12 |
Family
ID=22154335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1980/000544 WO1981003240A1 (en) | 1980-05-08 | 1980-05-08 | Lift-off process |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP0051598A1 (en) |
| WO (1) | WO1981003240A1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3822467A (en) * | 1972-04-28 | 1974-07-09 | Philips Corp | Method of manufacturing a semiconductor device having a pattern of conductors and device manufactured by using said method |
| US4004044A (en) * | 1975-05-09 | 1977-01-18 | International Business Machines Corporation | Method for forming patterned films utilizing a transparent lift-off mask |
| US4035206A (en) * | 1974-09-18 | 1977-07-12 | U.S. Philips Corporation | Method of manufacturing a semiconductor device having a pattern of conductors |
| US4131496A (en) * | 1977-12-15 | 1978-12-26 | Rca Corp. | Method of making silicon on sapphire field effect transistors with specifically aligned gates |
| US4218283A (en) * | 1974-08-23 | 1980-08-19 | Hitachi, Ltd. | Method for fabricating semiconductor device and etchant for polymer resin |
| US4228212A (en) * | 1979-06-11 | 1980-10-14 | General Electric Company | Composite conductive structures in integrated circuits |
-
1980
- 1980-05-08 WO PCT/US1980/000544 patent/WO1981003240A1/en unknown
- 1980-05-08 EP EP19810900532 patent/EP0051598A1/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3822467A (en) * | 1972-04-28 | 1974-07-09 | Philips Corp | Method of manufacturing a semiconductor device having a pattern of conductors and device manufactured by using said method |
| US4218283A (en) * | 1974-08-23 | 1980-08-19 | Hitachi, Ltd. | Method for fabricating semiconductor device and etchant for polymer resin |
| US4035206A (en) * | 1974-09-18 | 1977-07-12 | U.S. Philips Corporation | Method of manufacturing a semiconductor device having a pattern of conductors |
| US4004044A (en) * | 1975-05-09 | 1977-01-18 | International Business Machines Corporation | Method for forming patterned films utilizing a transparent lift-off mask |
| US4131496A (en) * | 1977-12-15 | 1978-12-26 | Rca Corp. | Method of making silicon on sapphire field effect transistors with specifically aligned gates |
| US4228212A (en) * | 1979-06-11 | 1980-10-14 | General Electric Company | Composite conductive structures in integrated circuits |
Non-Patent Citations (1)
| Title |
|---|
| IBM Technical Disclosure Bulletin, Volume 20, No. 3, issued 1977 (Armonk, New York), FREDERICKS et al., Polysulfone Lift-Off Masking Technique, see page 989 * |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0051598A1 (en) | 1982-05-19 |
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