Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
  • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
  • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
  • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
  • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
  • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
  • H10D84/65—Integrated injection logic

Definitions

• This invention relates to the field of bistable integrated circuits and, in particular, to the design of a shift register using bistable circuits on an IC chip.
• each cell may contain a number of gates, each comprising several transis ⁇ tors, the area required for this large number of transistors and the circuit interconnections therefor may be excessive.
• the cost of an IC chip is usually a direct function of its size.
• the basic "D" flip-flop element or cell When implemented with I 2 L logic, the basic "D" flip-flop element or cell, with no set or reset inputs requires seven I- ⁇ L gates. In addition to the gate count, another important characteristic of the D flip-flop is that it has three propagation delays between the time the Clock input goes to a one level and the time the Q output reaches the proper value. The Clock input must remain high during this period. In I 2 L logic, the propagation delay of a gate is inversely proportional to the current drain of the gate over a wide operating range. It can be shown that the current drain of the flip-flop, operating at a clock fre- quency f c , is 42Kf c where K is a constant determined by the fabrication method.
• a cell for 'a shift register which includes a multiplicity of cascade- connected storage elements or cells and a clock which provides two clock signals, one the complement of the other.
• Each cell includes four NAND logic gates connected as two binary R-S flip-flops. The two flip-flops are alternately energized by the clock signals which are used to switch the current into the gate injectors. Since only two gates per cell are receiving injection current at one time, and there is only one propagation delay per phase of the clock signal, the current requirement is only one tenth that of prior shift registers using I 2 L logic.
• Fig. 3 is a schematic diagram of the gate of Fig. 1 with multiple input signals on the single input.
• Fig. 4 is a logic representation of Fig. 3.
• Fig. 5 is a schematic diagram of a bistable cell in accordance with the present invention.
• the gate may be considered as a merged pair of NPN 10 and PNP 12 transistors, in which the base 14 of the PNP transis ⁇ tor is common with the emitter 14 of the NPN transistor and both are coupled to ground.
• the collector 16 of the PNP 12 is also the base 16 of the NPN 10.
• a current applied via terminal 17 to the emitter 18 of the PNP 12 causes that transistor to act as a current source for the NPN 10, sup ⁇ plying current to the base 16 of the NPN. Coupled to the base 16 is a control terminal 20.
• terminal 20 is grounded (logic zero input)
• the current being supplied by the PNP 12 is diverted to ground and the NPN 10 is then left in a non-conducting state in which the collectors 22, 24 and 26 are floating; i.e., have no current sinking capability.
• the base 16 of the NPN 10 is floating; i.e., a logic one input, the current supplied by the PNP 12 flows into the base 16 of the NPN 10, which then becomes a current sink for any circuit connected to the NPN collectors 22, 24 or 26.
• Fig. 3 the gate of Fig. 1 is shown with the capa- bility of coupling multiple devices to the base/collector 16. If all of the input devices are non-conducting (logic level one outputs) the input voltage at the control terminal 20 rises to a one level and the outputs 22, 24 and 26 are
• Fig. 3 may be represented logically as an inverting AND or NAND gate as shown in Fig. 4.
• Fig. 5 is a schematic diagram of a bistable circuit in accordance with the invention and including four NAND gates 30, 32, 34 and 36, each in itself comparable to the NAND gate of Fig. 3.
• Each cell of the shift register would be represented by the circuit of Fig. 5.
• gates 30 and 32 form one memory flipflop element and gates 34 and 36 form a second memory element.
• the two memory elements are alternately energized during the two phases of the clock signal by switching the current into the PNP devices of the gate (the gate injectors) in accordance with the clock signal. That is, the clock signal waveform is a square wave and when the clock level is high, injector current is fed to gates 30 and 32 while gates 34 and 36 have greatly reduced injector currents.
• gates 30 and 32 are again energized by the application of injector current and gates 34 and 36 are switched to the low current mode. New information is then fed into the first memory element of the cell and the cell (not shown) coupled to terminals 46 and 48 will shift in the data from the second memory element (gates 34 and 36) because of the pre-charged conditions on terminals 46 and 48.
• the signal appearing on the collectors of the NPN 10 of gate 34 also appears on a cell output terminal 49, and may be coupled to any desired device or circuitry.
• Fig. 6 also includes a schematic diagram of a differential amplifier 50 having a square wave clock signal input to a terminal 52. As is known, the signals on the collectors of the differential amplifier transistors would then be C and C, these complementary clock signals being coupled to the terminals 17A, 17B of each cell 28.
• the circuit described herein- above is much simpler to lay out in integrated circuit form since the clock signals C and U are routed through the injector supply lines and no separate clock lines are required to be routed through the IC. With fewer gates required per shift register cell and simpler interconnec- tions required, the cell of the invention is considerably smaller and therefore cheaper to construct than any other known shift register cell. It is also to be noted that the cell of Fig. 5 may have application in other circuits besides the shift register. Thus, there has been shown and described a circuit for an I L bistable cell or shift register cell which requires

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Logic Circuits (AREA)
• Shift Register Type Memory (AREA)

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Cited By (1)

Citations (10)

• 1980
  • 1980-07-07 JP JP50186480A patent/JPS56500870A/ja active Pending
  • 1980-07-07 WO PCT/US1980/000895 patent/WO1981000332A1/en not_active Ceased
  • 1980-07-07 BR BR8008718A patent/BR8008718A/pt unknown
• 1981
  • 1981-02-09 EP EP19800901563 patent/EP0032154A4/en not_active Withdrawn

Patent Citations (10)

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