Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit

Definitions

• the present invention relates to an ultra-fast digital-analog converter. It finds an application in electronics, for example in the field of signal processing and more particularly in digital-analog conversion at high speed and in amplitude modulation at several levels and at high speed.
• a digital-analog converter is a circuit which, to an ordered set of binary elements a k , matches an analog quantity E, according to the relation:
• index k denotes the rank of the elements which varies from 0 to n-1 and the coefficient Eo a reference quantity.
• analog quantity is of an electrical nature (current or voltage).
• the generators are capable of delivering currents I 0 , I 1 , ... I k ... I n-1 whose values are of the form:
• the binary elements a k of the digital signal to be converted determine the state (opening or closing) of the circuit switches.
• a null element controls the opening of the corresponding switch and an element equal to 1 its closing.
• the total current I s delivered by such a circuit is therefore of the form: is : an expression which is very similar to that of relation (1).
• the current generators that are most often encountered in this application are represented in FIG. 2. They include a transistor 14, a diode 16, a resistor 1B of value R k and two resistors 20 and 22 of values R 1 and R 2 .
• the circuit is completed by two power connections brought to voltages V cc and V EE .
• the useful current is the current I k of the collector of the transistor,
• the operation of this circuit is as follows.
• the diode 16 is used to compensate for the base-emitter offset voltage of the transistor 14.
• the voltage V E at the terminals of the resistor 18 is then equal to the voltage V e at the terminals of the resistor 22. If we neglect the basic current compared to the collector current, we can write:
• the present invention relates to such a converter, but which has an increased speed compared to the converters of the prior art which have just been described.
• the current generators and the switches are produced in a particular way, according to the technique known as “with coupled emitters” (or abbreviated ECL for “Emitter-C ⁇ upled Logic”).
• ECL with coupled emitters
• ECL emitter-C ⁇ upled Logic
• Bipolar logic circuits can be divided into two basic categories, depending on their mode of operation.
• One includes saturated logic (resistance logic and "RTL” transistor, diode logic and “DTL” transistor, transistor logic and “TTL” transistor), and the other, unsaturated logic, coupled in mode current (logic with current mode “CML”, logic with coupled transmitters “ECL”, logic with coupled transmitters controlled by current "ECCSL”),
• the present invention uses a type of circuit belonging to the second category, namely the ECL type.
• a type of circuit belonging to the second category namely the ECL type.
• Such a logic circuit is shown in FIG. 3 in the case of a quadruple NO. OR. He understands :
• a purely logical first stage formed by 4 logical parts (30 0 , 30 1 , 30 2 , 30 3 ), each having two inputs respectively (E oa , E ob ) (E 1a , E 1b ), (E 2a , E 2b ) and (E 3a , E 3b ) and an output respectively (Sn, S 1 , S 2 , S 3 ), and
• a second stage, of current amplification formed by 4 transistors 32 0 , 32 1 , 32 2 and 32 3 , each having a base b, an emitter e and a collector c, the base of a transistor being connected to the output of the preceding logic gate.
• the circuit shown also has a first supply line 34, brought to a voltage V cc1 , this line being connected to all the collectors c of the transistors 32, a second supply line tation 36 brought to a second voltage V cc2 and a third line 38 brought to a voltage V EE .
• the two voltages V cc1 and V c c2 are obtained by separate sources (not shown) to prevent the large variations in current which appear on the output of the circuit from being reflected on the input circuits which are particularly sensitive to interference.
• the logic gates are of the NOR type (in Anglo-Saxon terminology "NOR"). If E a and E b designate the logic states of the two inputs of one of these gates, the emitter of the corresponding output transistor delivers a signal equal to ⁇ . E, where the bar indicates the logical complementation operation and the point the AND operation.
• the present invention takes advantage of the exceptional properties exhibited by ECL circuits with regard in particular to speed, in order to produce an ultra-fast digital-analog converter. This is a new application of these circuits which, until now, have only been used as logic circuits.
• the invention uses a logic circuit of the ECL type of this kind, the logic functions not naturally being necessarily of the NOR type.
• the converter of the invention is further characterized in that it comprises:
• resistors connected to the emitters of the output transistors, the resistance connected to the transistor of rank k having the value R / 2 k , all these resistors being connected in parallel to the line V EE ,
• each bit of the digital signal to be converted is applied, according to its rank k, to the input of the logic gate connected to the transistor of the same rank k, the analog conversion signal then being constituted by the current flowing in the load line.
• FIG. 1 already described, represents the block diagram of a digital-analog converter
• FIG. 2 also already described, represents a current source used in the converters according to the prior art
• FIG. 3, also described, represents the block diagram of an integrated logic circuit of ECL type, - FIG. 4 represents the block diagram of a converter according to the invention,
• FIG. 4 shows an embodiment of a converter according to the invention from a particular logic circuit of the trade.
• the converter shown in FIG. 4 uses an integrated circuit 40 which is a quadruple NOR gate formed by 4 elementary NOR gates 42 0 , 42 1 , 42 2 and 42 3 , each having two inputs, one of which is denoted E , which is common to all the gates, and the others of which, denoted E 0 , E 1 , E 2 , and E 3 receive the binary elements a 0 , a 1 , a 2 a3 of the number to be converted.
• the integrated circuit 40 also includes 4 transistors 44 0 ,
• the integrated circuit 40 also has two output pins 48, 50, the first connected through a resistor 52 of value r 0 , to a voltage source 53 of value V cc1 and the second, to a voltage source 55 of value V cc2 .
• pin 48 is connected to a line 54 through a capacitor 56 which has the function of blocking the direct current component.
• Line 54 has a characteristic impedance which is equal to the value r 0 of the resistor 52 and it is closed on a load resistor 58 whose value is equal to r 0 .
• a current I flows in line 54 and a voltage V s appears across the load resistor 58.
• the capacitor 56 has the effect of blocking the DC component.
• the current I ultimately has the value:
• FIG. 5 represents an exemplary embodiment of a converter with three binary elements according to the invention which uses a logic circuit of the trade, in this case the MC 1664 circuit of the MOTOROLA Company.
• This circuit which still carries the reference 40, is a quadruple OR, which can be preferred to the quadruple NOR-OR of the preceding figure, which exhibits the defect of having a logic level 0 which depends slightly on the input voltage.
• Three inverting gates 62 0 , 62 1 and 62 2 receive the three binary elements a 0 , a 1 and a 2 of the number to be converted.
• FIG. 5 also presents the particularity of using potentiometers 60 1 , 60 2 and 60 3 arranged in series with the emitter resistors 46 1 , 46 2 and 46 3 to compensate for any dispersion of the logic levels provided by the four logic gates.
• V s 0.22 (4a 2 + 2a 1 + a 0 ) (10)

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Analogue/Digital Conversion (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

Family

ID=9224486

Family Applications (1)

Country Status (6)

Cited By (1)

Citations (3)

Family Cites Families (4)

• 1979
  • 1979-04-19 FR FR7909880A patent/FR2454726A1/fr active Granted
• 1980
  • 1980-04-15 JP JP50082980A patent/JPS56500397A/ja active Pending
  • 1980-04-15 GB GB8037097A patent/GB2065401B/en not_active Expired
  • 1980-04-15 DE DE803041442T patent/DE3041442T1/de active Granted
  • 1980-04-15 WO PCT/FR1980/000059 patent/WO1980002348A1/fr active Application Filing
  • 1980-04-17 CA CA000350110A patent/CA1155227A/fr not_active Expired

Patent Citations (3)

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