Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Definitions

• This invention generally relates to semicon ⁇ ductor memory devices and more specifically to static random-access memory systems having both volatile and nonvolatile binary data storage capability.
• ROMs read only memories
• RAMs random access memories
• SAMs serial access memories
• ROMs are so designated because they are typically employed where a fixed bit pattern is re ⁇ quired, such as for a firmware or microcode program in a data processing system.
• PROMs programmable read only memories
• EPROMs erasable PROMs
• EAROMs electri- cally-alterable read-only memories
• EEPROMs electrically erasable PROMs
• PROMs have the characteristic that they can be written one time only to a selected bit pattern which thereafter becomes fixed.
• EPROMs can be electri- cally programmed to a preselected bit pattern, but they typically require ultraviolet light shined on the de ⁇ vice to erase the stored bit pattern. This usually requires the EPROM device to be removed from the cir ⁇ cuit in which it is used.
• EEPROMs can be electrically erased and re-programmed in the circuit environment i,n
• CCDM and BDM systems typically involve single or multiple serial data loops with access to data stored at any particular location typically requiring serial shifting of each bit of data to a location where it can be accessed for reading or writing.
• Semiconductor SAM systems are thus typically employed where large amounts of data need to be stored but very rapid access to any particular data bit is not required.
• Static RAM systems typically employ bistable multivibrator or flip-flop circuits with the stored bit value determined by which of its two bistable states the circuit is in.
• Dynamic RAMs typically employ a cell arrangement in which the stored bit value deter- mined by the presence or absence of a voltage stored on a semiconductor capacitor structure. Since static RAMs employ bistable devices, the bit content of each cell is retained without refreshing and the readout of the bit content is non-destructive. Dynamic RAMs on the other hand typically require periodic refreshing of the information stored on the capacitor although the read ⁇ out may be either destructive or non-destructive de ⁇ pending on the cell design.
• RAMs are inherently non- volatile, including EPROMs and EEPROMs, due either to the ROM cell design or to the electrical characteristics of the devices employed in each ROM cell.
• RAMs are generally volatile devices, i.e. , the bit content of the memory is typically lost if electric power to the RAM is removed or lost.
• the invention set forth herein falls generally into the field of RAMs in which non-volatile semicon ⁇ ductor memory devices are employed in each RAM cell to provide backup non-volatile data storage capability.
• static RAM cells can be provided with non-volatile backup data storage capability by adding non-volatile, threshold-alterable devices of the transistor or capacitor variety to the RAM cell. These cells will be referred to as volatile/non-volatile RAM cells or simply V/NV RAM cells.
• V/NV RAM cells incorporating non-volatile transistors are disclosed in the following exemplary references: Mark et al. ⁇ . S. Patent 3,636,530; Lock- wood U. S. Patent 3,676,717; an article by Frohman- , Bentchkowsky, entitled "The Metal-Nitride-Oxide-Silicon (MNOS) Transistor — Characteristics and Applications", PROCEEDINGS OF THE IEEE” , Vol. 58, No. 8, August 1970 (Page 1218); Uchida et al. ⁇ . S. Patent 3,950,737; and Uchida ⁇ . S. Patent 4,044,343.
• MNOS Metal-Nitride-Oxide-Silicon
• V/NV RAM cells employ- ing non-volatile transistor backup devices have been employed in non-volatile counter circuits manufactured by various companies for electronic artillery fuse applications and for other general purpose uses. They are also employed in several V/NV RAM integrated circuits (ICs) commercially available from several companies.
• V/NV RAM cells using non-volatile capacitor elements are disclosed in the following exemplary prior art references: Ho et al. U. S. Patent 3,662,351; the above-mentioned Aneshansley application Serial No. 947,927; and Schuermeyer et al. U. S. Patent 4,091,460.
• V/NV RAM cells employing non ⁇ volatile capacitors require fewer active semiconductor devices than do V/NV RAM cells employing non-volatile transistors.
• V/NV RAM cells having fewer active devices per cell occupy less "real estate" on an IC chip
• Another advantage of such cells is that fewer control signal lines are required to be routed to each cell, and thus one less control signal need be provided to the IC chip. This further saves on chip real estate and saves one pin-out on the IC chip.
• V/NV RAM ICs generally employ the RAM cell structure shown in Fig. 1 of the Uchida '343 patent (a virtually identi ⁇ cal cell structure also being shown in Fig. 10 of the Mark et al. '530 patent).
• These V/NV RAM cells employ bypass transistors in parallel with the non-volatile memory transistors in the load circuits of the cell with a separate control line provided to these bypass transistors to turn them off when information is being read out of the non-volatile memory transistors and to turn them on when the cell is operating in the normal volatile mode.
• the bypass transistors and the control lines thereto add substantially to the "real estate" consumed by each V/NV RAM cell, and the control line further requires a separate pinout on the IC chip.
• FIG. 1A of the drawings herein shows the Aneshansley-type V/NV RAM cell employing non-volatile capacitor structures instead of non-volatile transistor structures. It should be apparent that fewer active devices are used in this type of cell and thus the chip real estate consumed by each such memory cell is sub ⁇ stantially less.
• Fig. 1A is structurally equivalent to the V/NV RAM cell disclosed in Fig. 4 of the above- referenced Aneshansley application. The only difference is that a preferred split-gate, non-volatile capacitor
• WLPO structure is schematically depicted in Fig. 1A, whereas the more general non-volatile capacitor symbol is used in Fig. 4 of the Aneshansley application.
• This split gate non-volatile capacitor structure is disclosed in Chang et al. U. S. Patent 3,911,464 (e.g. Figs. 9 and 10).
• the structure and operation of the V/NV RAM cell dis ⁇ closed in the Aneshansley application results inver ⁇ sion of the data during a power-up, non-volatile/volatile restore operation (hereinafter simply called a "NV/V restore operation").
• NV/V restore operation power-up, non-volatile/volatile restore operation
• V/NV RAM cell disclosed in U.S. Patent No. 4,091,460 utilizes a pair of non-volatile charge injec- tion devices as non-volatile storage elements, but has the disadvantage of utilizing a high frequency A.C. charge pump signal.
• the invention set forth and claimed herein comprises an improvement over the V/NV RAM cell dis ⁇ closed in Fig. 4 of the above-referenced Aneshansley .
• OMPI °* patent application in two respects: 1) an improved cell design for use with a single five volt, n-channel, SIS device technology which employs enhancement mode field-effect transistors (FETs) in series with a load impedance means (semiconductor resistor or depletion mode transistor) in each load circuit of the multivi ⁇ brator for bootstrapping the voltage on one of the output terminals during a V/NV write operation, and 2) an improved NV/V restore operation which results in data being restored to the cell in a non-inverted manner.
• FETs enhancement mode field-effect transistors
• load impedance means semiconductor resistor or depletion mode transistor
• the invention comprises an improvement in a memory cell having both volatile and non-volatile binary data storage capability comprising essentially a bistable multivibrator having selectable first and second sta ⁇ ble, volatile operating states and including a pair of output terminals having voltages thereon representing the operating state thereof.
• the multivibrator is constructed with a five volt, n-channel, SIS device technology utilizing load impedance means in the form of a semiconductor resistor or a depletion mode trans ⁇ istor.
• the cell further includes a non-volatile, threshold-alterable capacitor coupled to each of the output terminals and having a gate electrode indepen ⁇ dent of its associated output terminal adapted to receive write, refresh, and erase voltage signals.
• the improved memory cell incorporates enhancement mode field-effect transistor load devices in series with the load impedance means. These enhancement mode transis- tors are operative upon receipt by the gate electrodes of said non-volatile capacitors of a write voltage signal at least several times greater in magnitude than the supply voltage to bootstrap the voltage on one of the output terminals to a magnitude substantially greater than the supply voltage. This bootstrapped voltage provides effective channel-shielding in the
• the invention further comprises an improvement in a memory cell having both volatile and non-volatile binary data storage capability comprising a bistable multivibrator having selectable first and second stable, volatile operating states and including a pair of output termin ⁇ als having voltages thereon representing the operating state thereof, a pair of cross-coupled field-effect switching transistors connected between the output terminals and a reference voltage terminal, a load impedance means coupled between each output terminal and a power supply bus, and a threshold-alterable capacitor coupled to each of the output terminals and having a gate electrode independent of its associated output terminal.
• Each of the non-volatile capacitors comprises a first section having a non-alterable thres ⁇ hold characteristic and a second section having an alterable threshold characteristic with the first section proxi ately connected to its associated output terminal.
• the first section has a threshold at a small enhancement or depletion voltage level and the second section has an erased state threshold at a small deple ⁇ tion voltage level and a written state threshold at a relatively large enhancement voltage level with one of the non-volatile capacitors having its second section in an erased state and the other non-volatile capacitor having its second section in a written state.
• the gate electrodes of the non-volatile capacitors and the power supply bus are adapted to receive, respectively, a refresh voltage signal and a power supply step function signal having relative timing and rise time characteristics such that binary information stored in the non-volatile capaci- tors is refreshed to the bistable multivibrator in a non-inverted fashion.
• Fig. 1A is a circuit schematic diagram of a V/NV RAM cell of the type disclosed in the above-refer ⁇ enced Aneshansley patent application.
• Fig. IB is a circuit schematic diagram of a V/NV RAM cell having a structure in accordance with this invention.
• Fig. 2 is an operating signal diagram depicting one operating mode of the V/NV RAM cell illustrated in Fig. IB, incorporated in a system environment exempli ⁇ fied in Fig. 4.
• Fig. 3 is an operating signal diagram showing an alternate mode of operation of the V/NV RAM cell depicted in Fig. IB.
• Fig. 4 is a block schematic diagram of a V/NV RAM system utilizing a V/NV RAM cell in accordance with this invention in an exemplary data processing system environment.
• Fig. 5 is a circuit schematic diagram of an alternate embodiment of a V/NV RAM cell in accordance with this invention.
• Fig. 1A depicts a V/NV RAM cell generally in accordance with the above-referenced Aneshansley patent application.
• the V/NV RAM cell depicted in Fig. 1A is essentially the same as the V/NV RAM cell shown in Fig. 4 of the Aneshansley application.
• This V/NV RAM cell comprises essentially a bistable multi- .
• OMPI vibrator or flip-flop circuit arrangement which has selectable first and second stable, volatile operating states.
• Output terminals A and B have voltages thereon which represent the operating state of the multivibrator.
• a pair of cross-coupled field-effect transistors 201 and 202 are connected between output terminals A and B and a reference voltage terminal 211, shown connected to a ground reference potential.
• a pair of enhancement mode load transistors 209 and 210 are coupled between res- pective output terminals A and B and a power supply bus 123A.
• the multivibrator further employs a pair of non ⁇ volatile, threshold-alterable capacitors 207 and 208 connected, respectively, to output terminals A and B via lines 207D and 208D.
• Non-volatile capacitors 207 and 208 have gate electrodes 207C and 208C, respective ⁇ ly, which are independent of output terminals A and B and are connected to a control terminal 51 over a control line 51A.
• Control terminal 51 is also desig ⁇ nated W/R/E to indicate that control terminal 51 is selectively provided with Write, Restore, and Erase voltage signals during a sequence of V/NV write, NV/V restore, and erase operations on cell 200.
• Field- effect transistor 203 is connected between output terminal A and column data line X.
• Field-effect trans- istor 204 is connected between output terminal B and the column data line X.
• transistors 203 and 204 are connected to a row address line 131A which is also denoted DRA, signifying D_ecoded Row Address signal.
• Transistors 203 and 204 are commonly called access transistors.
• Complementary column data lines X and X ⁇ are typically connected to the power supply voltage through load devices (not shown).
• V/NV RAM cell 200 is a standard static RAM cell and functions in the typical data write, read and storage modes of such a cell. The volatile operation of such a static RAM cell is well-
• RAM cell 200 has two stable, volatile operating states. In the first of these volatile operating states, switching transistor 201 is on and switching transistor 202 is off. For conven ⁇ ience, this will be hereafter termed a "volatile 0 state" corresponding to a stored 0 bit. Accordingly, the voltage on output terminal A is essentially ground reference potential since transistor 201 is designed to have a very low impedance in its on state. Contrast ⁇ ingly, output terminal B has a voltage thereon substan ⁇ tially equal to the power supply voltage on bus 123A less the voltage drop across load transistor 210.
• the second stable volatile operating state exists when transistor 201 is off and transistor 202 is on. For convenience, this will be called the "volatile 1 state" corresponding to a stored 1 bit.
• the volatile 1 state the voltages on output terminals A and B are reversed, i.e. , the voltage on output terminal A is at a positive voltage and the output terminal B is at ground reference potential.
• Access transistors 203 and 204 are employed to write binary data into RAM cell 200 and to read out binary data from the cell.
• access transistors 203 and 204 are turned on to enable voltages provided on complementary column data lines X and X to be coupled to output terminals A and B, res ⁇ pectively. If RAM cell 200 is to be written into a volatile 0 state, column data line X will be provided with a ground reference signal and column data line X will be provided with a voltage of about the same magnitude as the power supply voltage on bus 123A. These voltages on the complementary column data lines are coupled through the access transistors 203 and 204 when a DRA (D_ecoded Row Address) signal is provided to line 131A. Once these voltages are coupled to output .
• DRA D_ecoded Row Address
• the bistable multivibrator will be written into the volatile 0 state regardless of its previous state.
• column data line X is provided with a voltage generally corresponding to the power supply voltage and column data line X is provided with a ground reference potential.
• These voltages coupled through access transistors 203 and 204 will cause the bistable multivibrator to assume the volatile 1 state regardless of its prior state.
• access transistors 203 and 204 are turned off. The cell retains the binary digit value (bit value) associated with that written opera ⁇ ting state as long as electric power is provided to the cell.
• access transistors 203 and 204 are turned on to couple whatever voltages appear on output termin- als A and B to complementary column data lines X and X, respectively.
• the multivibrator circuit ⁇ in V/NV RAM cell 200 will not retain the stored infor ⁇ mation once power to the cell is removed or lost. While there is some capacitance associated with output terminals A and B which retains the voltages thereon for a short period of time, any power outage of sub ⁇ stantial duration will result in a dissipation of those voltages and loss of stored information. Then when power is returned to the cell, it will assume a particu ⁇ lar one of its operating states depending on the rela ⁇ tive capacitive imbalance between the two halves of the cell regardless of the operating state of the cell upon power down.
• non-volatile capacitors 207 and 208 in V/NV RAM cell 200 enable th.e bit stored in the volatile 1 or 0 state of the multi ⁇ vibrator to be written into the non-volatile capacitors 207 and 208 in a V/NV write operation prior to loss of power to the cell. Once the bit has been written into non-volatile capacitors 207 and 208, it is retained therein until power is restored to the cell. There ⁇ after, the non-volatilely stored bit can be restored to the multivibrator in a NV/V restore operation.
• non-volatile capacitors 207 and 208 may be erased with an erase voltage signal on control line 51A to prepare them for the next V/NV write operation.
• the stored information in non-volatile capacitors 207 and 208 may be retained during power-up operation and erased prior to being written after power loss occurs the next time.
• the threshold-alterable portions 207B and 208B of non-volatile capacitors 207 and 208 typically require write and erase voltages of a magnitude on the order of twenty or twenty five volts.
• the write voltage is ' a negative voltage and the erase voltage is a positive voltage.
• non-alterable sections 207A and 208A typically have an enhancement voltage threshold of about negative 2 volts.
• Alterable sections 207B and 208B typically hav.e an erased depletion thres ⁇ hold of about positive 2 volts and a written enhance ⁇ ment threshold voltage of about negative 8 volts.
• a p-channel version of V/NV RAM cell 200 would typically employ negative power supply voltages on power supply bus 123A of sufficient magnitude (e.g. fifteen to twenty volts) to provide an effective chan ⁇ nel-shielding voltage to one of the non-volatile capaci ⁇ tors 207 and 208 which is to be retained essentially in its erased threshold state.
• V/NV RAM cell 200 in a p-channel version of V/NV RAM cell 200, one of the output terminals A and B will have thereon a voltage substan ⁇ tially equal to the negative power supply voltage.
• output terminal B will have a voltage thereon substantially equal to the negative power supply voltage.
• This voltage on output terminal B is coupled via line 208D to the channel of non-volatile capacitor 208 where it provides an effective channel-shielding voltage to preclude substantial alteration of the threshold of alterable capacitor por- tion 208B when a write voltage of, for example, nega ⁇ tive twenty five volts is applied to gate electrode 208C.
• the signal on terminal B (e.g. twenty volts) will be coupled to the channel of alter ⁇ able section 208B so that the negative twenty five volt signal on gate electrode 208C will be insufficient to substantially alter the threshold of the alterable section 208B of non-volatile capacitor 208.
• the output terminal A has substantially ground reference potential thereon and thus the negative twenty five volt write signal on gate electrode 207C of non-volatile capacitor
• non-volatile capacitor 207 will be sufficient to place alterable section 207B of non-volatile capacitor 207 into its written thres ⁇ hold state. Consequently, the write voltage pulse will cause non-volatile capacitor 207 to be written to a high negative threshold while non-volatile capacitor
• alterable section 208B will have its alterable section 208B either remain ⁇ ing in an erased threshold state (i.e. a positive threshold voltage) or, at worst, a partly-written state with a very low negative threshold voltage (i.e. less than negative two volts). In any event, the threshold voltage differential between alterable sections 207B and 208B will be quite substantial after a V/NV write operation.
• an erased threshold state i.e. a positive threshold voltage
• very low negative threshold voltage i.e. less than negative two volts
• the volatile bit stored in cell 200 becomes a stored non ⁇ volatile bit.
• the stored non-volatile bit can be restored reliably to the multivibrator in a NV/V re ⁇ store operation.
• the following NV/V restore operation can be implemented.
• the V/NV RAM cell output terminals A and B are precharged to ground reference potential via comple ⁇ mentary column data lines X and X and access transistors 203 and 204.
• Power supply line 123A is at about twenty volts negative.
• an erase pulse can be supplied to control line 51A (e.g. a positive twenty five volt signal) to return both alter- able threshold sections 207B and 208B of non-volatile capacitors 207 and 208 to an erased threshold state.
• control line 51A e.g. a positive twenty five volt signal
• alter- able threshold sections 207B and 208B of non-volatile capacitors 207 and 208 to an erased threshold state.
• n-channel, device technology utilizing a single positive power supply voltage of substantially five volts or less to achieve high density, fast access, low power consump ⁇ tion ICs.
• Straightforward adaptation of RAM cell 200 to five volt, n-channel SIS device technology would involve substitution of either low current depletion mode transistors or, preferably, high resistance value semiconductor resistors for enhancement mode transis ⁇ tors 209 and 210 to achieve low current cell operation.
• the five volt signal on one of the output terminals A or B (depending on the state of the multivibrator) is not sufficient to provide effective channel shielding in the associated non-volatile capacitor.
• V/NV RAM cell 200 with semiconductor resistors in the load circuits in place of enhancement mode transistors 209 and 210.
• a volatile 0 state such that output terminal A is near ground reference and output terminal B is at about five volts.
• non-alterable sections 207A and 208A of non-volatile capacitors 207 and 208 have a threshold of about one volt positive or negative.
• alterable sections 207B and 208B have an erased state threshold of about one volt negative and a written state threshold of about six volts posi ⁇ tive.
• a positive twenty volt signal is applied to gate electrodes 207C and 208C of non-volatile capacitors 207 and 208.
• the five volt signal on output terminal B is coupled via line 208D to the channel of the non-volatile capacitor 208.
• the voltage difference of approximately 15 volts across the device is sufficient to write alterable section 208B to a fairly substantial written threshold — perhaps as much as four volts positive. The difference between ,
• the non-volatile capacitors have dif ⁇ ferent written thresholds at different temperatures and may have different degredation rates under write/erase cycling, the differences in written thresholds between a fifteen volt write and a twenty volt write may prob ⁇ ably not be sufficient to provide reliable NV/V restore operation of the cell over the required operating life of the IC device in which it is incorporated.
• a cell which functions with sufficient margins when the IC device in which it resides is new might begin to malfunction after the device has been used for a relatively long period of time and a relatively large number of V/NV write, NV/V refresh, and, erase cycles have been performed on the cell.
• V/NV RAM cell 300 differs from that of the prior art V/NV RAM cell 200 shown in Fig. 1A in that both enhancement mode field-effect transistors 309 and 310 and polysilicon resistive load devices 305 and 306 are employed in the load circuits of the multivibrator.
• the 300 series reference numerals in Fig. IB correspond to the 200 series reference numerals in Fig. 1A.
• the normal volatile operation of V/NV RAM cell 300 is virtually identical to the normal volatile operation of V/NV RAM cell 200 and will not be repeated here.
• V/NV RAM cell 300 Incorporating enhancement mode load transistors 309 and 310 with polysilicon resistors 305 and 306 in V/NV RAM cell 300 enables cell 300 to be reliably implemented in five volt, n-channel, SIS device tech- nology due to a dramatic improvement in the reliability of the V/NV write operation of V/NV RAM cell 300.
• V/NV RAM cell 300 To be in its second bistable state with switching transistor 301 off and switching transistor 302 on. In this state, output terminal A has a voltage thereon of approximately +three and one- half volts and output terminal B has substantially ground reference potential thereon.
• a positive write voltage signal is applied to control line 51A and thus to gate electrode 307C and 308C of non-volatile capacitors 307 and 308.
• non-volatile capacitor 307 will capacitively couple this signal to output terminal A.
• Cell 300 is preferably designed such that the capaci- tance to ground at each output terminal A and B is equal to the total capacitance of non-volatile capaci ⁇ tors 307 and 308 in an erased state. Typical capaci ⁇ tance values for each would be about 50-60fF (femto- farads).
• the signal on output terminal A will be bootstrapped to a positive voltage of approximately thirteen volts, due to the back biased diode provided by transistor 309 enabling the voltage on terminal A to rise above the five volt supply on bus 123A.
• Output terminal B will, of course, remain at ground reference potential.
• the bootstrapped voltage on output terminal A provides effective channel-shielding in the channel of non ⁇ volatile capacitor 307 during the V/NV write operation.
• Non-volatile capacitor 307 will have only a six and one- naif volt signal differential between its gate electrode and. the channel of threshold-alterable section 307B. This voltage differential will, at most, slightly raise the threshold voltage of alterable section 307B from its erased threshold of one volt negative.
• the twenty volt differential between gate electrode 308C and the channel of alterable section 308B of non-volatile capacitor 308 will produce a full writing of alterable section 308B, i.e. its threshold voltage changes from one volt negative to about six volts positive.
• the bootstrap voltage on output termin ⁇ al A thus insures a substantial differential threshold window between alterable section 307B of non-volatile capacitor 307 and alterable section 308B of non-vola ⁇ tile capacitor 308.
• This substantial differential threshold window provides for a reliable NV/V restore operation of cell 300.
• V/NV RAM cell . 300 can thus readily be implemented in a five volt, n-channel, SIS device technology to produce a V/NV RAM system having reliable non-volatile backup data storage capability under power-down conditions.
• the NV/V restore, operation of V/NV RAM cell 300 is performed in a manner which re ⁇ stores information stored in non-volatile capacitors 307 and 308 to the multivibrator in a non-inverted fashion.
• This is accomplished by a NV/V restore opera ⁇ tion in which a restore signal of about ..fiv>e volts positive is applied to control line 51A at the same time that, or shortly prior to, application of a step function power supply voltage to bus 123A.
• V/NV RAM cell 300 can also be provided with the NV/V restore signal sequence as set forth above in connection with Fig. 1A, in which case the data stored in non ⁇ volatile capacitors 307 and 308 would be restored to the cell in an inverted fashion.
• V/NV RAM VOLATILE/NON-VOLA ⁇ TILE STATIC RAM SYSTEM
• CENTRAL PROCES ⁇ SOR UNIT CPU
• PLCS POWER LINE CONDITION SENSE CIRCUIT
• DC POWER SUPPLY 40 DC POWER SUPPLY 40
• V/NV RAM 10 includes a MEMORY CELL MATRIX 110, typically incorporating a plurality of rows and columns of volatile/non-volatile RAM cells 300 depicted in Fig. IB.
• V/NV RAM 10 further includes CONTROL LOGIC 120, ROW ADDRESS DECODER 130, and COLUMN ADDRESS DECODER AND DATA I/O DRIVERS 140.
• CONTROL LOGIC 120 provides a number of important control functions during both the volatile write/read operations on memory cell matrix 110 and the V/NV write, NV/V restore, and erase opera ⁇ tions thereon. The various functions of CONTROL LOGIC 120 will be more apparent from the detailed description of these various operating modes given below.
• V/NV RAM 10 includes a resistor 124 connecting W/R/E line 51.
• CONTROL LOGIC 120 functions essentially the same as in prior art V/NV RAM systems employing non ⁇ volatile, threshold-alterable transistors. Consequent ⁇ ly it will not be discussed in detail herein.
• AC POWER is a constant power source.
• OMPI WIPO SUPPLY 60 is typically a central power station of a utility supplying AC line voltage at an outlet to which a data processing system is connected.
• Switch 70 represents one or all of a main power switch on the data processing system, a circuit breaker on the system and a circuit breaker in a central breaker box at the installation.
• PLCS unit 30 is connected via line 71 to the system side of switch * 70 so that it can sense the loss of AC power to DC POWER -SUPPLY 40 regardless of the cause.
• PLCS unit 30 provides an output signal on line 31 to CPU 20 indicating the presence or absence of AC power to DC POWER SUPPLY 40.
• Various approaches can be implemented in PLCS unit 30.
• the PLCS unit examines consecutive cycles of AC signal on the power line and signals the CPU that power is on except when it detects that a preselected number of consecutive cycles are missing, at which time it signals the CPU that power is off. This approach is readily implemented in straight ⁇ forward, analog and digital circuits.
• DC POWER SUPPLY 40 may generally be any typical power supply capable of supplying sufficient current at a five volt level to the ..various operating portions of the data processing system.
• the only special characteristic required for DC POWER SUPPLY 40 is that it be capable of continuing to supply DC volt ⁇ age at about the five volt level to the system after loss of AC power, so that the CPU and other portions of the system can function for the time required to res ⁇ pond to the power down condition.
• the DC supply to V/NV RAM system 10 must continue for sufficient time for the system to execute a V/NV write operation"before power -to V/NV RAM system 10 is lost. Power supplies having such characteristics are avail ⁇ able in the prior art and generally it is sufficient for such power supplies to store the five volt signal, on a large enough capacitor to retain the signal for about fifty milliseconds after interruption of AC power.
• W/R/E SG unit 50 is preferably the unit disclosed in the above-mentioned related international application. This unit functions to provide a write voltage signal to V/NV RAM 10 on line 51 under control of CPU 20 via a signal on bus 26 during a V/NV write operation. It also functions to provide an erase signal under the control of CPU 20 after an NV/V restore oper ⁇ ation has been performed on V/NV RAM 10. If V/NV RAM 10 is to be restored in a non-inverted fashion, it also provides the restore signal required prior to erase.
• V/NV RAM system 10 in exemplary sequence of V/NV write, NV/V restore, and erase opera ⁇ tions will now be described in conjunction with Figs. IB, 2, and 4.
• each cell in MEMORY CELL MATRIX 110 is a cell as shown in Fig. IB.
• the sequence of operations simultaneously effects operations in each cell, but it will be sufficient to consider only one cell because the operation on each is essen ⁇ tially identical.
• Fig. 2 shows the signals appearing on various leads and terminals of the system of Fig. 4 and an exemplary memory cell shown in Fig. IB at various times in an exemplary sequence of V/NV write, NV/V restore and erase operations.
• Fig. 2 shows the signals appearing on various leads and terminals of the system of Fig. 4 and an exemplary memory cell shown in Fig. IB at various times in an exemplary sequence of V/NV write, NV/V restore and erase operations.
• aiid CPU 20 can perform normal volatile read or write opera ⁇ tions on V/NV RAM 10.
• CE chip enable
• DRA decoded row address
• Volatile write (VW) signal from CPU 20 on line 24 (not shown) is low as is reset signal (RS) on line 25 from CPU 20.
• RS reset signal
• the exemplary cell being dis ⁇ cussed is in its volatile 1 state such that terminal A of the cell has a positive voltage thereon while ter- minal B has ground reference voltage thereon. Since the DRA signal is high, access transistors 303 and 304 in cell 300 are on and complementary column data lines X and X have thereon substantially the same voltage as output terminals A and B.
• V/NV RAM 10 presents this information on the volatile 1 state of cell 300 to CPU 20 via one of DATA I/O lines 141.
• CPU 20 will have recognized the power failure due to the PL signal and will, if neces ⁇ sary, -take a short* ime to complete its execution of certain machine operations in preparation for perform ⁇ ing a V/NV write operation. For example, CPU 20 may want to dump certain information into memory cell ⁇
• OMPI ⁇ > IPO matrix 110 so that it can later determine the last operation which it performed prior to executing the V/NV write operation.
• CPU 20 will begin to execute a subroutine, which may be stored in ROM program memory (not shown) , to provide the V/NV write operation.
• a subroutine which may be stored in ROM program memory (not shown)
• ROM program memory not shown
• DRA goes low and access trans- istors 303 and 304 are turned off.
• X stays high and X goes high.
• CPU 20 signals W/R/E SG 50 to produce a non-volatile write signal (e.g. 20 volts positive of about 10 milliseconds duration) on W/R/E line 51 which is coupled to W/R/E line 51A in cell 300.
• this positive write signal causes the voltage on output terminal A to bootstrap up to a level of about thirteen volts positive.
• the bootstrapped voltage on terminal A is coupled via line 307D to the channel of non-volatile capacitor 307 in cell 300 to provide channel-shielding for the threshold alterable section 307B therein.
• the positive write signal on line 51A in cell 300 is furnished to gate electrode 308C of non-volatile capacitor 308 to cause alterable threshold section 308B to be written into its written threshold state of about six volts positive.
• the V/NV write operation has been completed, and the volatile 1 state of cell 300 has been transformed into a non-volatile 1 state in cell 300. It should be understood that this V/NV write operation is simultaneously performed on each cell in memory matrix 110 such that each cell having a volatile 1 state is written to a non-volatile 1 state and each cell in a volatile 0 state is written to a non-volatile 0 state.
• signal P from DC POWER SUPPLY 40 continues to degrade toward zero volts.
• the power signal RP supplied to each cell on RP line 123 also degrades to zero volts during this interval. Between t. and t- the power is off. In a typical power failure situation, the power may be off for anywhere from just a few seconds to several hours or more. Where the system has purposely been shut down, by turning it off at night, for example, the power may be off for a number of hours or even over a weekend. The length of the power off condition is incidental since V/NV RAM 10 is capable of retaining the stored non ⁇ volatile information for at least thirty days.
• the NV/V restore operation begins as CPU 20 turns RS on line 25 high.
• Control logic 120 responds to this reset signal by turning on all DRA lines to memory cell matrix 110 and placing ground reference voltages on all complementary column data lines X and X associated with each column of the memory cell matrix 110.
• This completely resets the output terminals A and B in each cell of memory cell matrix -110 to ground reference potential in preparation for application of a restore signal on W/R/E line at time t culinary.
• the vertical scale of voltages associ ⁇ ated with the three signal lines designated W/R/E, A,. and B is changed in order to enable the restore sig ⁇ nal and the response to that signal to be more clearly shown.
• time scale between t R and t. is changed in order to show the operation of the cell 300 in response to a restore signal.
• control logic 120 provides an RP power signal on line 123 to the memory cell matrix 110.
• the restore signal is furnished to each memory cell on W/R/E line 51.
• the restore signal is a short five volt pulse having a rise time of about 100 nanoseconds.
• the RP signal is a five volt step function signal having a similar rise time.
• the restore signal has reached about one volt which is the threshold level of non-alterable capacitor sections 307A and 308A of non-volatile capacitors 307 and 308 in cell 300.
• alterable section 307B is in an erased state threshold of about one volt negative while alterable section 308B is in a written state threshold of about six volts positive.
• Non-alterable sections 307A and 308A turn on.
• Alter- able section 3.07B had previously been turned on by the restore signal. • Consequently, the restore signal is c * apacitively coupled through the relatively large capacitance value of both sections of capacitor 307 to output terminal A, whereas at that point the capacitive coupling of that signal to terminal B only through non- altera£>le section 308A is considerably less.
• the voltage on output terminal A rises much more quickly than the voltage on output terminal B during the t q - ⁇ Q interval.
• Enhancement mode transistors 309 and 310 are just starting to turn on and do not swamp out the voltage differentials on the output terminals. The more rapidly rising voltage on output terminal A f
• OMPI /,, IPO . causes transistor 302 to turn on at time t, Q , whereupon the voltage on output terminal A rapidly rises to about three and one-half volts and transistor 301 turns off so that the voltage on terminal B rapidly falls to ground reference potential.
• the restore signal goes low, the NV/V restore operation has been completed at that time and RAM cell 300 has been re ⁇ turned to its volatile 1 state with a positive voltage on output terminal A and a ground potential on output terminal B.
• V/NV RAM 10 is typically implemented on a single IC chip. To provide the necessary amount of static RAM storage capability, a typical system will employ a plurality of such IC chips.
• the CE signal is used to address one particular chip at a time for volatile data write and read operations. However, during the V/NV write, NV/V restore, and erase operations, all V/NV RAM chips in the system are provided simultaneously with the write, restore, and erase signals.
• NV/V restore mode of operation for cell 300 would involve maintaining RP signal at ground reference until shortly after time t, n and the stepping it up to five volts.
• the design of cell 300 does not require that the RP signal step up in coincidence with the restore signal on line 51. It must not, however, precede the restore signal or the restore signal may not be effective and data may come up in each cell in an erroneous fashion as when the power was first turned on to the system at time t .
• the NV/V restore operation shown in Fig. 2 and described with respect to the cell 300 shown in Fig. IB could also be employed to provide a non-inverted data restore operation for p-channel memory cell 200 in Fig. 1A.
• this invention encompasses the novel non-inverted NV/V restore opera ⁇ tion for both cell 300 shown in Fig. IB having the novel structure in accordance with this invention and cell 200 shown in Fig. 1A.
• the non-inverted restore operation could possibly be used in an n-channel five volt version of cell 200 in Fig. 1A in spite of the marginal differential writes involved in using poly- silicon resistors in such n-channel version.
• Fig. 3 shows an operating diagram for an alternative NV/V restore operation which could be performed on a slightly modified version of cell 300.
• the NV/V restore operation shown in Fig. 3 results in data inversion upon restore.
• non-volatile capacitors 307 and 308 are made with a depletion threshold in the non- alterable sections 307A and 308A thereof.
• the V/NV write operation shown in Fig. 3 is identical to that shown and described in Fig. 2.
• the NV/V restore opera ⁇ tion shown in Fig. 3 starts with the same reset pulse on RS as the NV/V restore operation in Fig. 2.
• both output terminals A and B will begin to charge toward positive voltages.
• a larger capacitance is coupled to output terminal A due to both non-alterable section 307A and alterable sec ⁇ tion 307B being turned on at the ground voltage signal provided on W/R/E line at this time by W/R/E signal generator in conjunction with resistor 124, output ter- inal A will charge toward a positive voltage much more slowly than output terminal B. Accordingly, the voltage at output terminal B will reach the threshold voltage of switching transistor 301 before the voltage on output terminal A reaches the threshold voltage of switching transistor 302.
• switching trans ⁇ istor 301 turns on to ground output terminal A.
• Switch ⁇ ing transistor 302 remains off and output terminal B rises rapidly towards its final positive voltage level.
• the inverted data can be handled by CPU 20 in a number of ways. One way would be to produce a second sequence of V/NV write and NV/V restore operations to re-invert the data to its original value. Another straightforward approach would be to read out all of the data from each V/NV RAM chip, re-invert it and write it back into the V/NV RAM chips.
• Fig. 5 shows a slightly modified version of the V/NV RAM cell shown in Fig. IB.
• the enhancement mode transistors 309 and 310 have their gates tied to the RP line and power is restored to cell 300 by switching on these transistors in the non-in ⁇ verted NV/V restore operation shown in Fig. 2.
• the silicon load resistors 305 and 306 are connected to the Power supply line P(V ) along with the column data line load resistors 312 and 313. While this embodiment involves some sacrifice of chip real estate due to an additional control line to the cell, it has the advantage of avoiding the requirement of switching a heavy current in a single device in con ⁇ trol logic 120 shown in Fig. 4.
• RAM cell 300 shown in Fig. IB in a power-up initial ⁇ izing mode in which data is maintained continuously in the non-volatile capacitors 307 and 308. This initial ⁇ izing data is refreshed to the cell after each power- down operation to initialize the V/NV RAM- to a predeter- mined arrangement of data bits regardless of the ar ⁇ rangement of data bits therein at the time power is lost.
• each cell could be provided with an additional set of non-volatile capacitors with the first set used to store initializing data bit pat- terns and the second set used to store actual data bit patterns existing in memory cell matrix 110 at the time a power-down condition occurs.
• a power-down/power- p se ⁇ quence is shown in which a V/NV write operation only is performed on power-down and an erase operation is per ⁇ formed on power up after a NV/V restore operation.
• the power-down sequence involve an erase operation quickly followed by a V/NV write operation.

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• 1980
  • 1980-03-10 JP JP50169480A patent/JPS56500109A/ja active Pending
  • 1980-03-10 WO PCT/US1980/000251 patent/WO1980001965A1/en not_active Application Discontinuation
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