WO1980000101A1 - Dispositif de sondage et interface pour tranches de circuits integres - Google Patents

Dispositif de sondage et interface pour tranches de circuits integres Download PDF

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Publication number
WO1980000101A1
WO1980000101A1 PCT/US1979/000444 US7900444W WO8000101A1 WO 1980000101 A1 WO1980000101 A1 WO 1980000101A1 US 7900444 W US7900444 W US 7900444W WO 8000101 A1 WO8000101 A1 WO 8000101A1
Authority
WO
WIPO (PCT)
Prior art keywords
printed circuit
probe
circuit card
accordance
probe device
Prior art date
Application number
PCT/US1979/000444
Other languages
English (en)
Inventor
R Schwartz
G Orman
J Tarzwell
Original Assignee
Cerprobe Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cerprobe Corp filed Critical Cerprobe Corp
Publication of WO1980000101A1 publication Critical patent/WO1980000101A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card

Definitions

  • the present invention relates to the field of integrated circuit testing device, and more specifically to probe type devices for testing integrated circuit wafers.
  • probe cards are being utilized during the manufacture of integrated circuits to determine the usability of the individual circuits.
  • these probe cards consist of multi-probe members which are mechanically held in contact with th ⁇ . circuit wafers. Such mechanical contact allows electrical testing of the individual integrated circuits prior to their severance from the wafer.
  • the required input voltages and input signals may be provided to the individual integrated circuit and the resulting output signals may be monitored.
  • it is desired to use these probe cards to couple . high frequency signals to the integrated circuit wafers and to allow monitoring of high frequency output signals.
  • the blade probe card consists of an epoxy-glass printed circuit card to which is affixed a plurality of beryllium-copper blades. A metal needle ⁇ like probe is then soldered to each blade and all the probes are configured so that they may contact the pads of an integrated circuit chip on a wafer.
  • the blade probe card has several distinc disadvantages.
  • the greatest disadvantage is its high electrical capacitance between circuit paths resulting from the parallel configuration of the metal blades. Th is, the necessary closeness and parallelism of the metal blades results in a capacitive effect between the indi ⁇ vidual blades. Due to this high capacitance, the blade probe card cannot be used for testing a variety of integrated circuits, including metal-oxide silicon (MOS) circuits, and for general high frequency testing;
  • MOS metal-oxide silicon
  • a further disadvantage of the blade probe card results from the low surface resistance and low dielectr constant of the epoxy-glass material.
  • Such probe cards optimally should have infinite surface resistance to allow total isolation of the circuit paths.
  • the epoxy-glass material has a low surface resist- ance, the individual circuit paths are allowed to intera to the detriment of integrated circuit testing.
  • the low dielectric constant of the epoxy-glass material limits the upper frequency at which the card can be used because of the resulting higher capacitance between indi- vidual circuit paths.
  • a second prior art attempt to provide the testing capabilities noted above is the epoxy-ring card.
  • This card consists of an epoxy-glass card which has probes soldered to copper strips which are affixed to the epoxy glass.
  • the epoxy-ring card also has a variety of disadvantages.
  • One disadvantage, difficulty of repair, stems from the method of affixing the copper strips to the epoxy-glass. The copper strip is laminate or glued to the epoxy-glass and the probe is then solder to the strip. If a probe becomes damaged and must be
  • Another problem associated with the epoxy-ring card is the flexibility of the card. Since such cards are not rigid, the individual probes soon lose their planarity and alignment with other probes. Such lack of planarity, as in the case of the blade probe card, results in damage to the circuit wafers and variation in contact resistance. Further disadvantages of the epoxy-ring card, just as in the blade probe card, are a consequence of the utilization of epoxy-glass material. The epoxy-ring card also cannot be used at elevated temperatures since the plastic components of the glass material will deteriorate. In addition, the low surface resistance of the glass material and its low dielectric constant allows inter ⁇ action of the input and monitoring lines as well as limiting its high frequency use.
  • Both of the probe card types described above have the common problem of probe to probe capacitance and line to line capacitance on the PC board which limits the use of the card for high frequency and/or high impedance and high gain test applications.
  • a third type of card utilizing ceramic holders, to which individual needle- like probe members are attached solves part of the problems inherent in the blade and epoxy-ring cards.
  • the ceramic probe holders are inherently low capacitance and insensitive to high temperatures. They may be attached to a ceramic holder card which further decreases capaci- tance, temperature sensitivity and line to line leakages.
  • the major problem with all the presently available probe card techniques is the necessity to traverse a significant distance through wire or printed circuit lines before test and measurement circuitry can be attached.
  • This line length may present significant capacitance or inductive loading to high speed or high impedance circuitry.
  • Present procedures involve building active buffer circuits and terminations on the probe cards, as close to the actual probe blades as possible, to provide line driving capability for connection to remotely located test equipment. With high speed, MOS or very high gain linear circuits, these techniques still leave much to be desired.
  • the high speed circuitry cannot be tested at its full operating repetition rate and MOS circuitry is loaded excessively creating the necessity to test at a slower rate.
  • Linear amplifiers may have to be tested at much less than full gain or with higher signal amplitudes than desired in order to compendate for probe capacitance and lead inductance. Noise pickup and gener ⁇ ation is also increased by having measurement circuitry remote from the actual circuit connections.
  • the present invention is a probe device for testing integrated circuit wafers.
  • the probe device comprises a support means, a plurality of holding means, hybrid circuitry constructed upon said holding means, and a plurality of corresponding needle-like probe members.
  • the support means is a rectangular or round structure having a generally circular aperture, and electrically con ⁇ ductive portions. Coupled to the support means in a plurality of "L" shaped holding means. These holding means have an extremely thin metalized area along their bottom edge surface which is used to connect them to the support means. A portion of the holding means extends into the circular aperture of the support means. Coupled to the holding means is a plurality of corresponding needle-like probe members, each having a curved portion. The narrow edge surface on the lower portion of the holding means also has an extremely thin metalized area. This metalized area is not connected to the other metalized area used for connection to the support means.
  • Each probe member is coupled to this second metalized area so that the probe member is parallel to the support means while the curved portion of the probe member extends into the circular aperture.
  • the furthest extreme of each probe member is configured so as to be capable of electrically contacting a circuit wafer which is placed within the aperture.
  • Hybrid circuitry is constructed on the flat areas of the sides of the holding means. This hybrid circuitry is used to interface between the probe member and the connection to the support means and subsequently to the test and measurement circuitry.
  • the support means are electrically coupled to their corresponding holding means which are in turn electrical coupled to the hybrid circuitry on the holding means whi is subsequently coupled to the corresponding probe membe which is in turn electrically coupled to contact pads on the integrated circuit chip under test.
  • the present invention allows test ing of integrated circuit wafers at high frequency and under conditions which would not otherwise be possible.
  • the ability to couple inputs and outputs from the inte ⁇ grated circuit wafer to hybrid circuit buffers, loads, drivers and termination devices in close proximity to the integrated circuit wafer allows testing of the device which more closely approximates its final package form.
  • Figure 1 is a top view of the probe device of the present invention and its corresponding testing apparatus
  • Figure 2 is an enlarged top view similar to Figure 1 showing the probes, probe holders and support therefor for the portion of the probe device in proximity to the chip to be tested;
  • Figure 3 is a perspective view of the holding member used to hold the probe tip showing hybrid circuit con- r nection paths and resistors;
  • Figure 4 is a view similar to Figure 3 with the attachment of a corresponding probe member;
  • Figure 5 is an electrical schematic diagram of the hybrid circuit buffer used in the probe device of Figure 1;
  • Figure 6 is a top view of the bonding pad configur ⁇ ation of the integrated circuit chip used in the hybrid circuit of Figure 5;
  • Figure 7 is an enlarged top view of the layout on a holding member substrate of the hybrid circuit of Figure 5 with the integrated chip of Figure 6;
  • Figure 8 is a view similar to Figure 3 showing an alternate embodiment of the holding member.
  • probe device 2 is illustrate with its corresponding testing instrumentation 8.
  • Testin instrumentation 8 is coupled to probe device 2 by means o cable 6 and coupling connector 4. Also illustrated in
  • Figure 1 is support means 3 and its metalized portions 10
  • the metalized portions 10 may be implemented by silk screening onto ceramic, plastic or other suitable materia or by etching and/or plating methods applied to standard printed circuit boards. If a silk screening process is used, the resulting assembly may be fired at high temper ⁇ ature causing the metalized portions to fuse directly to the support means 3, essentially becoming a part of it. By this method of application, the metalized portions 10 have little tendency to lift from support means 3 when heat is applied. This allows the metalized portions 10 to be repeatedly soldered during construction or repaid of probe device 2 without degradation.
  • the use of silk screening techniques for implementing metalized portions 10 on the support means 3 is also compatible with the implementation of hybrid circuitry. Screening techniques may also be used to implement resistors on the support means 3.
  • Figure 1 also illustrates circular aperture 12 of support means 3. The particular integrated circuit to be tested on the integrated circuit wafer is located immediately beneath the circular aperture 12 and holding means 16.
  • Probe members 20 "are needle-like '-members which are made of tungsten or similar metal. Probe members 20 are coupled to holding means 16 in a manner which will be more fully described below. Probe tips 21 are aligned and configured such that they may make electrical contact with metalized pads on the integrated circuit chip to be tested. In operation, the probe device 2 is placed in a rigid holder over an integrated circuit wafer located below .the circular aperture 12. The wafer is aligned such that the metalized pads on the surface of a chip align with the array of probe tips 21.
  • the wafer is normally held in place on a flat movable chuck by vacuum applied to the back of the wafer through holes in the chuck.
  • the chuck may be raised until the probe tips 21 contact the chip.
  • electrical connection is made from the integrated circuit pads through the probe member 20 to the metalized portion of the holding means 16 to which the probe member 20 is attached.
  • This metalized portion is then directly connected to hybrid circuitry on the holding means 16. This configuration results in a very short physical connection between the integrated circuit pad and buffering or measurement circuitry which may be implemented on the holding means 16.
  • Figure 3 shows in greater detail the "L" shaped holding means 16 with its elongated portion 26 and its shortened portion 24.
  • a thin metalized portion 18 is applied to the bottom periphery of the shortened portion 24 of holding means 16. These metalized portions are applied to the narrow surface of the holding means 16 by silk screening and subsequent firing at high temperature.
  • the first metalized portion 18 is used to make mechanical and electrical connection to support means 3.
  • the second metalized portion 30 is used to attach the probe member 20 to the holding means 16. Additional metalized areas and resistor patterns are silk screened on the flat surface 28 of the holding means 16.
  • connection is also made between metalized conductors on the flat surface 28 and the ⁇ J c A(7' OMPI metalized areas 18 and 30 on the edge of holding means 16.
  • This construction permits hybrid circuitry to be imple ⁇ mented on the holding means flat surface 28 and serves as an interface between electrical signals associated with the testing apparatus 8 (see Figure 1) and the integrated circuit chip under test.
  • Figure 4 shows in greater detail the preferred embodiment of the coupling of probe member 20 to the support means 16.
  • probe member 20 is soldered to metalized portion 30 along the narrow surface of shortened portion 28.
  • probe members may also be coupled to holding means 16 by brazing or welding to the metalized portion 30.
  • Probe member 20 is coupled to holding means 16 so that the curved portion 23 of probe member 20 extends beyond holding means 16.
  • Figure 5 shows in schematic form a buffer circuit typical of the type which might be used to improve the capability of an integrated circuit chip output to drive long interconnect lines.
  • the circuit will serve for illustra tion of the concept as an example of a buffer implemented with hybrid circuit techniques on the holding means 16 (see Figure 3) .
  • Its input is connected to the probe member 20 via metalization portion 30 and its output is connected to metalization portion 18 and subsequently to a wire or cable 6 (see Figure 1) leading to the electrical test equipment 8.
  • the buffer circuit in Figure 5 may be implemented using a standard integrated circuit operationa amplifier 74 with appropriate resistors and metal in er- connects.
  • the inverting input IN-78 and the output 86 of the operational amplifier are connected together to implement the unity gain configuration.
  • the output OUT 54 from the circuit is taken from this point and will subse ⁇ quently be connected to metalized portion 18 (see Figure 3 of holding means 16.
  • the non-inverting input IN+80 is driven from a voltage divider circuit formed by resistors 106, 108, 110 and 116.
  • the input signal IN 92 to this resistive divider comes from the probe member 20.
  • Resis ⁇ tor 110 is selected in the proper ratio to resistor 116 to provide the desired attenuation of the input signal. This allows input signal voltages at IN 92 of larger voltage magnitude than could be tolerated at the IN+80 input to the operational amplifier. Alternate scaling ratios may be implemented by selecting resistor 108 or 106 in parallel with resistor 110.
  • Resistors 40 and 42 are con ⁇ nected respectively to the input offset trimming pads N2 76 and Nl 84. The other ends of resistors 40 and 42 are connected together and returned to the positive supply V+ 44. Adjustment of resistors 40 and 42 by standard hybrid manufacturing techniques such as scribing, sand blasting or laser trimming allows the input offset error of the integrated circuit operational amplifier 74 to be adjusted to a value low enough so as not to introduce significant error to the voltage transfer function of the circuit. Power requirements of the operational amplifier are supplied by the positive supply V+44 which is connected to pad 88 and the negative supply V-34 which is connected to pad 82.
  • Figure 6 shows the topological layout of connection or bonding pads on the surface of the integrated circuit operational amplifier 74 to be used for illustration. This physical layout of pads will affect the form or layout of the illustrated hybrid circuit. It should be realized, however, that the concept of the instant invention is applicable to virtually any circuit type and the specific operational amplifer 74 and circuit chosen are for illus ⁇ tration of the principles only.
  • Figure 7 is an enlarged view of- he.,holding..means.,_.- ⁇
  • probe member 20 with its associated hybrid circuitry and probe member 20.
  • the probe member 20 is attached to the metalized portion 30 as previously described which is subsequently connected to the input line IN 92.
  • a drop of epoxy 32 is
  • the integrated circuit operational amplifier is mounted on a large metalized pad area 55 which is connecte to the negative supply lead 34.
  • the V- pad 82 from the chip is connected to this supply lead 34 via wire bond 56.
  • the positive supply is routed to the vicinity of the integrated cricuit chip via metalized trace 44.
  • Wire bond 46 connects the V+ pad 88 to the positive supply lead 44.
  • the monolithic ceramic capacitor 64 is used to bypass electrical noise between the positive supply lead 44 and the negative supply lead 34.
  • the chip capacitor is attach ed by solder connections 66 and 68.
  • the output pad OUT 86 from the operational amplifier is connected by wire bond 4 to the output metalized trace 54 and subsequently to metalized portion 18.
  • Metalized trace 54 also connects to input lead IN 78 via wire bond 60.
  • the input attenuator resistors 106, 108, 110 and 116 are formed by silk screen ⁇ ing a resistive material directly onto the holding means and subsequently firing at a high temperature.-
  • the input lead IN 92 is connected to resistor 110.
  • the other end of resistor 110 is connected to metalized trace 94 which is subsequently connected by wire bond 58 to the non-invertin input IN+ 80 of the operational amplifier. If wire bonds ' 98, 102, 104 and 112 are deleted, the circuit functions as a simple voltage follower with a resistor 110 in series with its input.
  • the input resistance may be eliminated by making the connection from IN 92 to the trace 94 with wire bond 104.
  • Metalized trace 50 is connected by wire bond 52 to pad Nl 84 on the operational amplifier chip.
  • the circuit shown in the present example uses only a portion of the area available in the shortened portion 24 and the elongated portion 26 of the holding means. Essen ⁇ tially the entire area of the holding means 16 is available for construction of hybrid circuitry. The only restriction is that a small area must be maintained clear along the top of the holding means 16 in order to hold the device while attaching it to the support means.
  • Figure 8 shows an alternative to the preferred embodiment of the holding means.
  • metalized portion 18 is made smaller and metalized portions 19, 21 and 23 are added to the bottom periphery of the elongated portions 26 of the. holding means 16.
  • the positive supply lead 44, negative supply lead 34 and the ground lead 69 are routed to the metalized portions 21, 34 and 69, respectively.
  • the remainder of the hybrid circuitry on the holding means 16 would remain essentially unchanged.
  • Metalized portion 30 still connects to metal trace 92 on the shortened portion 24 and metalized portion 18 still connects to metal trace 54 on the elongated portion 26 of holding means 16.
  • the buffering circuitry were built on the support means rather than the holding means, the situation would be improved over having the integrated circuit output drive the cable, however, the capacitance loading presented by this arrangement would still be many times greater than is possible when the buffering circuitry is built directly on the holding means 16.
  • the inductive effect of the signal path from the probe member 20 to the support means and subsequently to the testing equipment are greatly reduced.
  • Many high gain linear circuits and high speed digital circuits are intolerant of inductance in their input, output or supply leads. This can lead to oscillations in the high gain circuitry and oscillations o incorrect measurements in the high speed circuitry. Re ⁇ ducing the capacitive and inductive loading on the circuit outputs by use of the instant invention allows faster and more reliable testing to be accomplished.
  • the concept may be extended to include hybrid circuitry constructed on the support means as well as on the holding means.
  • Circuitry on the support means or on the holding means might be single or double sided in construction and could easily include lines of controlled impedance such as 50 or 75 ohm lines required for testing some high speed logic families.
  • the use of metal covered with an insulating medium for the support means allows controlled impedance lines to be constructed on both sides of the support means.
  • the use of metal also lends support and rigidity to the support means for better performance.
  • Metal substrates also pro ⁇ vide superior thermal conduction properties.
  • a support means or a holding means constructed on insulated metal has the ability to dissipate heat very effectively from hybrid circuitry constructed upon it.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

Dispositif de sondage pour tester des tranches de circuits integres. Le dispositif de sondage comprend un support (3) qui possede une pluralite de parties metallisees (10) et une ouverture (12). Une pluralite de moyens de maintien en forme de "L" (16), ayant chacun une surface en bordure metallique et fine (18), sont couples aux parties metallisees du support de sorte qu'une partie des moyens de maintien s'etend dans l'ouverture. La surface plate (28) desdits moyens de maintien possede des configurations de conducteurs et de resistances (FIG. 7) pour la construction d'ensembles de circuits hybrides actifs et passifs utilises comme tampons, terminaisons, charges, et une interface generale entre le circuit a tester et l'appareil de test du circuit. Un element sonde en forme d'aiguille (20) est couple a une seconde surface de bords metallises (30) de chacun des moyens de maintien de telle maniere que leurs parties courbees s'etendent dans l'ouverture du support pour etablir le contact electrique avec la tranche de circuit placee a l'interieur, et couplee electriquement la tranche de circuit au support et ensuite a l'ensemble des circuits hybrides presents sur le support. Les circuits hybrides peuvent ensuite etre couples au support puis a l'appareil de test du circuit via la premiere surface de bordure metallisee decrite ci-dessus.
PCT/US1979/000444 1978-06-21 1979-06-21 Dispositif de sondage et interface pour tranches de circuits integres WO1980000101A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US91755378A 1978-06-21 1978-06-21
US917553 1978-06-21

Publications (1)

Publication Number Publication Date
WO1980000101A1 true WO1980000101A1 (fr) 1980-01-24

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WO (1) WO1980000101A1 (fr)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514022A (en) * 1983-06-29 1985-04-30 Tektronix, Inc. Probe cable assemblies
EP0257833A2 (fr) * 1986-08-21 1988-03-02 Tektronix, Inc. Sonde à haute impédance et large bande montable sur une carte
US4780670A (en) * 1985-03-04 1988-10-25 Xerox Corporation Active probe card for high resolution/low noise wafer level testing
EP0288801A2 (fr) * 1987-04-29 1988-11-02 International Business Machines Corporation Carte à sondes et procédé pour la prévoir avec des circuits reconfigurables
US4983907A (en) * 1987-05-14 1991-01-08 Intel Corporation Driven guard probe card
GB2297624A (en) * 1995-02-03 1996-08-07 Hewlett Packard Co Multiple point test probe
GB2298049A (en) * 1995-02-03 1996-08-21 Hewlett Packard Co Multiple channel voltage probe with impedance matching
DE29809568U1 (de) 1997-05-28 1998-10-08 Cascade Microtech, Inc., Beaverton, Oreg. Sondenhalter für Niederstrom-Messungen
US7138813B2 (en) 1999-06-30 2006-11-21 Cascade Microtech, Inc. Probe station thermal chuck with shielding for capacitive current
US7420381B2 (en) 2004-09-13 2008-09-02 Cascade Microtech, Inc. Double sided probing structures
US7492172B2 (en) 2003-05-23 2009-02-17 Cascade Microtech, Inc. Chuck for holding a device under test

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4116523A (en) * 1976-01-23 1978-09-26 James M. Foster High frequency probe
US4161692A (en) * 1977-07-18 1979-07-17 Cerprobe Corporation Probe device for integrated circuit wafers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4116523A (en) * 1976-01-23 1978-09-26 James M. Foster High frequency probe
US4161692A (en) * 1977-07-18 1979-07-17 Cerprobe Corporation Probe device for integrated circuit wafers

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514022A (en) * 1983-06-29 1985-04-30 Tektronix, Inc. Probe cable assemblies
US4780670A (en) * 1985-03-04 1988-10-25 Xerox Corporation Active probe card for high resolution/low noise wafer level testing
EP0257833A2 (fr) * 1986-08-21 1988-03-02 Tektronix, Inc. Sonde à haute impédance et large bande montable sur une carte
EP0257833A3 (fr) * 1986-08-21 1990-01-24 Tektronix, Inc. Sonde à haute impédance et large bande montable sur une carte
EP0288801A2 (fr) * 1987-04-29 1988-11-02 International Business Machines Corporation Carte à sondes et procédé pour la prévoir avec des circuits reconfigurables
EP0288801A3 (en) * 1987-04-29 1988-12-07 International Business Machines Corporation Probe card apparatus and method of providing same with reconfigurable probe card circuitry
US4983907A (en) * 1987-05-14 1991-01-08 Intel Corporation Driven guard probe card
FR2733599A1 (fr) * 1995-02-03 1996-10-31 Hewlett Packard Co Sonde de tension a concordance d'impedance
GB2297624B (en) * 1995-02-03 2000-06-14 Hewlett Packard Co Multiple lead voltage probe
GB2298049A (en) * 1995-02-03 1996-08-21 Hewlett Packard Co Multiple channel voltage probe with impedance matching
GB2297624A (en) * 1995-02-03 1996-08-07 Hewlett Packard Co Multiple point test probe
FR2733598A1 (fr) * 1995-02-03 1996-10-31 Hewlett Packard Co Sonde de tension a plusieurs conducteurs
DE19603802A1 (de) * 1995-02-03 1996-08-14 Hewlett Packard Co Spannungssonde mit Vielfachanschlußleitungen
US6232789B1 (en) 1997-05-28 2001-05-15 Cascade Microtech, Inc. Probe holder for low current measurements
DE29809568U1 (de) 1997-05-28 1998-10-08 Cascade Microtech, Inc., Beaverton, Oreg. Sondenhalter für Niederstrom-Messungen
US6384615B2 (en) 1997-05-28 2002-05-07 Cascade Microtech, Inc. Probe holder for low current measurements
US6850082B2 (en) 1997-05-28 2005-02-01 Casecade Microtech, Inc. Probe holder for testing of a test device
US7138813B2 (en) 1999-06-30 2006-11-21 Cascade Microtech, Inc. Probe station thermal chuck with shielding for capacitive current
US7492172B2 (en) 2003-05-23 2009-02-17 Cascade Microtech, Inc. Chuck for holding a device under test
US7876115B2 (en) 2003-05-23 2011-01-25 Cascade Microtech, Inc. Chuck for holding a device under test
US7420381B2 (en) 2004-09-13 2008-09-02 Cascade Microtech, Inc. Double sided probing structures
US8013623B2 (en) 2004-09-13 2011-09-06 Cascade Microtech, Inc. Double sided probing structures

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