UST106201I4 - Master image chip organization technique or method - Google Patents

Master image chip organization technique or method Download PDF

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Publication number
UST106201I4
UST106201I4 US06/457,786 US45778683A UST106201I4 US T106201 I4 UST106201 I4 US T106201I4 US 45778683 A US45778683 A US 45778683A US T106201 I4 UST106201 I4 US T106201I4
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United States
Prior art keywords
pattern
conductors
spacing
coordinate system
macro
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US06/457,786
Inventor
John Balyoz
Chi S. Chang
Barry C. Fox
John A. Palmieri
Majid Ghafghaichi
Teh-Sen Jen
Donald B. Mooney
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Publication date
Priority claimed from US05/974,576 external-priority patent/US4295149A/en
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Priority to US06/457,786 priority Critical patent/UST106201I4/en
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Publication of UST106201I4 publication Critical patent/UST106201I4/en
Pending legal-status Critical Current

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    • H10W20/43—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/901—Masterslice integrated circuits comprising bipolar technology

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming an improved integrated circuit chip structure having a surface from which regions of different conductivity type are arranged in a plurality of electrically isolated macro circuits, each macro circuit including interconnected components, a first X pattern of equally spaced parallel conductors overlying and electrically insulated from said chip structure surface, said first X pattern of conductors being selectively connected to at least certain ones of said plurality of macro circuits, a second Y pattern of equally spaced parallel conductors overlying and electrically insulated from said first pattern of parallel conductors, said second Y pattern of conductors being selectively connected to at least selected certain ones of said first pattern of electrical conductors, said spacing one from another of said first X pattern of conductors being equal to said spacing one from another of said second Y pattern of conductors, said first pattern of conductors being orthogonal of said second pattern of conductors, and each of said connections occurring exclusively at points in space corresponding to X-Y intersections of an X-Y coordinate system, where said X-Y coordinate system geometrically corresponds identically to said X-Y pattern of conductors.
US06/457,786 1978-12-29 1983-01-13 Master image chip organization technique or method Pending UST106201I4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US06/457,786 UST106201I4 (en) 1978-12-29 1983-01-13 Master image chip organization technique or method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/974,576 US4295149A (en) 1978-12-29 1978-12-29 Master image chip organization technique or method
US06/457,786 UST106201I4 (en) 1978-12-29 1983-01-13 Master image chip organization technique or method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US06224240 Continuation 1981-01-12

Publications (1)

Publication Number Publication Date
UST106201I4 true UST106201I4 (en) 1986-03-04

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ID=27038728

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/457,786 Pending UST106201I4 (en) 1978-12-29 1983-01-13 Master image chip organization technique or method

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US (1) UST106201I4 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020134104A1 (en) * 2000-11-10 2002-09-26 James Stenhouse High efficiency discontinuous cryogenic mixed gas refrigeration system using coalescent (depth) membrane filters and plate heat exchangers and refrigerant therefore

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020134104A1 (en) * 2000-11-10 2002-09-26 James Stenhouse High efficiency discontinuous cryogenic mixed gas refrigeration system using coalescent (depth) membrane filters and plate heat exchangers and refrigerant therefore

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