USRE42648E1 - Semiconductor memory apparatus and method for writing data into the flash memory device - Google Patents

Semiconductor memory apparatus and method for writing data into the flash memory device Download PDF

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USRE42648E1
USRE42648E1 US12/016,751 US1675103A USRE42648E US RE42648 E1 USRE42648 E1 US RE42648E1 US 1675103 A US1675103 A US 1675103A US RE42648 E USRE42648 E US RE42648E
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page
block
write target
logical
data
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Yoshihisa Inagaki
Toshiyuki Honda
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Godo Kaisha IP Bridge 1
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Panasonic Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Definitions

  • the present invention relates to a semiconductor memory apparatus that includes a flash memory device.
  • the invention relates to a method of writing data into the flash memory device.
  • Information processing appliances and, further in recent years, household electric appliances, such as television sets and refrigerators, include CPUs and realize advanced operating control by software.
  • the appliances store (firmware) programs for the operating control and parameters in ROMs.
  • Semiconductor memory apparatuses that include flash memory devices are extensively used as the ROMs.
  • the semiconductor memory apparatuses are extensively used in portable information processing appliances (mobile appliances), such as notebook computers, personal digital assistants (PDA), digital cameras, portable audio players, and cellular phones, as external, miniature recording media like memory cards.
  • mobile appliances such as notebook computers, personal digital assistants (PDA), digital cameras, portable audio players, and cellular phones, as external, miniature recording media like memory cards.
  • PDA personal digital assistants
  • portable audio players portable audio players
  • cellular phones portable audio players
  • it is desirable that the semiconductor memory apparatuses have large capacities and small sizes.
  • the storage area of a flash memory device is generally divided into a plurality of pages each having a fixed number of memory cells. Writing and reading of data are performed page by page.
  • the storage area is further divided into a plurality of blocks each having a fixed number of the pages. A data erasing is performed collectively in each of the blocks. Accordingly, page-by-page overwriting of data cannot be performed in the strict sense in the flash memory device, in contrast to RAMs.
  • a conventional semiconductor memory apparatus realizes a renewal of data stored in some pages of flash memory devices (which is hereafter referred to as a renewal of pages) and a writing of new data onto blank pages (which is hereafter referred to as an addition of pages), for example, as follows.
  • FIG. 9 is an illustration of the renewal or addition of pages in one block of a flash memory 1 by the conventional semiconductor memory apparatus.
  • the conventional semiconductor memory apparatus comprises the flash memory 1 and two RAMs; a saving buffer 20 and a page buffer 2 .
  • the flash memory 1 is divided into more than one block B 0 , B 1 , . . .
  • a physical address is allocated to each of the blocks B 0 , B 1 , . . .
  • Each of the blocks includes 32 pages.
  • the head block (or the first block) B 0 includes pages P 0 , P 1 , . . . , and P 31
  • the (n+1)th block Bn (n ⁇ 1) includes pages Q 0 , Q 1 , . . . , and Q 31 .
  • a page in the block is identified by the pair of the physical address of the block and a page number in the block.
  • the page numbers are, for example, serial numbers 0 - 31 put on the respective pages of the block from its top page in sequence.
  • the saving buffer 20 and the page buffer 2 each have a storage capacity substantially equal to that of one page of the
  • a host sends out a logical address designating a write target page and data objects to be written, to the semiconductor memory apparatus.
  • the semiconductor memory apparatus stores the data objects DN in the page buffer 2 .
  • the semiconductor memory apparatus identifies the corresponding page in the flash memory 1 from the logical address. For example, when the logical address designates the (p+1)th page Pp (0 ⁇ p ⁇ 31) of the head block B 0 , the semiconductor memory apparatus converts the logical address into the pair of the physical address of the head block B 0 and the page number p of the (p+1)th page Pp.
  • the physical address is identified as the physical address of a block being a source of data transfer (which is hereafter referred to as a source block).
  • the semiconductor memory apparatus selects, in the flash memory 1 , one block in which data has not yet been written (which is hereafter referred to as a blank block).
  • the semiconductor memory apparatus selects, for example, the (n+1)th block Bn being the blank block.
  • the physical address of the (n+1)th block Bn is identified as a physical address of the block to which the data stored in the source block B 0 is transferred (which is hereafter referred to as a destination block).
  • the conventional semiconductor memory apparatus transfers data items stored in the source block B 0 to the destination block Bn as follows. First, the data item D 0 of the top page P 0 of the source block B 0 is read into the saving buffer 20 (see the arrow R 0 shown in FIG. 9 .) Next, the data item D 0 of the saving buffer 20 is written onto the top page Q 0 of the destination block Bn (see the arrow WO shown in FIG. 9 .) Then, the data item D 1 of the second page P 1 of the source block B 0 is read into the saving buffer 20 (see the arrow R 1 shown in FIG.
  • the data item D 1 of the saving buffer 20 is written onto the second page Q 1 of the destination block Bn (see the arrow W 1 shown in FIG. 9 .)
  • the semiconductor memory apparatus skips the data transfer to the saving buffer 20 for the page. Instead, the data object DN to be written, which is stored in the page buffer 2 .
  • the semiconductor memory apparatus brings the logical address corresponding to the physical address of the source block B 0 into correspondence with the physical address of the destination block Bn.
  • the data item on the (p+1)th page Pp having the page number p is rewritten in the destination block Bn, in contrast to the source block B 0 .
  • the conventional semiconductor memory apparatus realizes the renewal and addition of pages for one block of the flash memory 1 .
  • Semiconductor memory apparatuses are required to have large capacities and small Sizes as far as possible. However, improvements in packing density of the flash memory devices are not easy. Accordingly, size reductions of circuit parts except the flash memory devices are desirable. For example, when many functional sections each include common circuit parts, the common parts are to be integrated into a single part. Thereby, reductions in number of the common parts are desirable. Size reductions of the semiconductor memory apparatuses are more desirable since they reduce the costs of manufacturing through the reductions in area of chips.
  • the conventional semiconductor memory apparatus has the two RAMs, the saving buffer and the page buffer, as described above. The RAMs share the commonalities, being used as a buffer memory and having the substantially same storage capacity as that of one page of the flash memory device.
  • the integration of the saving buffer and the page buffer into one RAM is strongly desirable.
  • the page buffer has to hold data objects to be written until the write target page is set as a target of saving, as described above. Therefore, it is difficult that the page buffer doubles as the saving buffer.
  • An object of the present invention is to provide a semiconductor memory apparatus wherein the size of RAM is reduced through the integration of the saving buffer and the page buffer into a single RAM, and thereby miniaturization is achieved.
  • a semiconductor memory apparatus comprises:
  • (A) a flash memory device comprising more than one block, each of which includes more than one page, and a page-offset storage area in which a page offset of each of the blocks is stored, and writing data into a blank block from its top page in sequence;
  • the logical page numbers are serial numbers allocated to the respective pages in the flash memory device by the host.
  • the physical page numbers are serial numbers put on the respective pages of each block in the flash memory device, from the top page in sequence.
  • the page offset of a block means a cyclic deviation of the logical page order from the physical page order in the block.
  • the page offset of the block is preferably the same as the logical page number of the top page of the block.
  • the above-described semiconductor memory apparatus according to the present invention stores the page offsets of the respective blocks in the flash memory device.
  • the actually stored data items may be the logical page numbers of particular pages, in addition to the page offsets themselves.
  • the page offset storage areas are preferably the redundant areas of the top pages of the respective blocks.
  • the redundant area of the page is the storage area accessible independently of the data area of the page.
  • the logical address corresponding to the page, the flag showing whether or not the page is a blank page, the flag showing that the data written onto the page is enabled/disabled (in other words, the access of the host to the page is allowed/inhibited), and the error-detecting code (e.g. CRC) of the data are stored in the redundant area of the page.
  • the storage space for the page offsets may be allocated to a non-volatile memory separated from the above-described flash memory device (which is hereafter referred to as a page-offset storage section), in addition to the page-offset storage area in the flash memory device.
  • the page-offset storage section is included, for example, in the memory control section.
  • the page buffer is a RAM, and preferably, an SRAM.
  • the number of pages of the data objects to be written means the amount of the data objects expressed in the unit that is the data storage capacity per page in the flash memory device.
  • the number of pages of the data objects is equal to the number of pages of the page area of the destination block into which the data objects are written.
  • the logical page numbers of the pages in the flash memory device may shift from the physical page numbers of the pages in a cyclic manner in the respective blocks.
  • the physical page number of each page is calculated based on the logical page number of the page and the page offset of the block to which the page belongs.
  • the above-described semiconductor memory apparatus can use the page buffer as a saving buffer at the saving of the source block.
  • the above-described semiconductor memory apparatus according to the present invention has RAMs smaller in size than those of conventional apparatuses. Therefore, the above-described semiconductor memory apparatus according to the present invention has the whole size smaller than that of the conventional apparatus when the sizes of the flash memory devices are fixed.
  • the above-described semiconductor memory apparatus may further comprise: (a) a host interface for receiving the logical address of the write target page and the data object, which are sent out from the host; and (b) an address-conversion-table storage section storing a logical/physical address conversion table showing a correspondence between a logical address and a physical address for each of the blocks in the flash memory device, and a flag for showing whether or not each of the blocks is the blank block; and the above-described memory control section may count the number of pages of the data objects and may start data transmission from the source block to the destination block, when the number of the pages reaches a predetermined number, or when the host provides notification of the end of sending of the data object.
  • the address-conversion-table storage section is preferably a RAM.
  • the logical/physical address conversion table is the table showing the correspondences between the logical address allocated to each block in the flash memory device and the physical address of the block.
  • the host interface is independent of the memory control section, data communications between the host and the semiconductor memory apparatus are performed independently of data writing/reading in the flash memory device. Thereby, for example, the latency time of the host for writing data into the flash memory device is shortened.
  • the address conversion section scans, for example, the redundant areas of the pages in the flash memory device. Thereby, the logical addresses of the respective blocks in the flash memory device are listed. Thus, the address conversion section creates the logical/physical address conversion table, and stores the table into the address-conversion-table storage section. The address conversion section consults the logical/physical address conversion table, when converting the logical address of the write target page into the pair of the physical address of the source block and the logical page number of the write target page. Thereby, the section can promptly retrieve the physical address corresponding to the logical address.
  • the address conversion section further checks whether or not each block is a blank block, based on the data items stored in the scanned redundant areas. Thereby, the section determines the above-described flags for the respective blocks, and stores the flags into the address-conversion-table storage section.
  • the memory control section consults the above-described flags, when selecting one of the blank blocks as a destination block. Thereby, the section can promptly determine the destination block.
  • the memory control section when transferring the data objects to be written, which the host stores in the page buffer, from the page buffer to the destination block, the memory control section counts the number of times of the transfer.
  • the host may notify the semiconductor memory apparatus of the end of sending of the data objects, for example, using a predetermined command. In that case, the memory control section can detect the number of pages of the data objects from the above-described number of times of the transfer at the receipt of the notification.
  • the memory control section starts the data transfer from the source block to the destination block.
  • the host may notify the semiconductor memory apparatus of the number of pages of the data objects before sending the data objects. In that case, the memory control section starts the data transfer from the source block to the destination block when the above-described number of times of the transfer reaches the notified number of pages.
  • a method of writing data into a flash memory device which is the method of writing data into a flash memory device comprising more than one block, each of which includes more than one page, and writing data into a blank block from its top page in sequence;
  • (H) obtaining a physical page number of a transfer start page of the source block based on the number of pages of the data objects and the physical page number of the write target page, and transferring data stored in the source block, from the transfer start page in a sequential and cyclic manner, via the page buffer, to a page next to or after a page area of the destination block into which the data object is written.
  • the logical page number, the physical page number, the page offset of the block, the page-offset storage area (or the page-off set storage section), the page buffer, and the number of pages of the data objects to be written are defined in a manner similar to the above-described ones.
  • the logical page numbers of the pages in the flash memory device may shift from the physical page numbers of the pages in a cyclic manner in the respective blocks.
  • the physical page number of each page is calculated based on the local page number of the page and the page offset of the block to which the page belongs.
  • the method of writing data according to the present invention may further comprise the step of counting the number of pages of the page area of the destination block, into which the data objects are written, and starting data transmission from the source block to the destination block, when the number of the pages reaches a predetermined number, or when the host provides notification of the end of sending of the data object. For example, every time when the data object is transferred from the page buffer to the destination block, the number of times of the transfer is counted.
  • the host may notify the semiconductor memory apparatus of the end of sending of the data object, for example, using a predetermined command. In that case, the number of pages of the above-described page area is detected from the above-described number of times of the transfer at the receipt of the notification.
  • the data transfer from the source block to the destination block gets started at the notification.
  • the host may notify the semiconductor memory apparatus of the number of pages of the data objects before sending the data objects. In that case, the data transfer from the source block to the destination block starts when the above-described number of times of the transfer reaches the notified number of pages.
  • the page buffer is freed before the start of the saving process for the source block in the above-described semiconductor memory apparatus and its method of writing data according to the present invention. Accordingly, the page buffer can double as a saving buffer at the saving process.
  • the above-described semiconductor memory apparatus has RAMs smaller in size than those of conventional apparatuses. Therefore, the above-described semiconductor memory apparatus according to the present invention has the whole size smaller than that of the conventional apparatus when the sizes of the flash memory devices are fixed. Manufacturing costs of the above-described semiconductor memory apparatus according to the present invention reduce lower than those of the conventional apparatuses, since the chip area is particularly small.
  • FIG. 1 is a block diagram showing a semiconductor memory apparatus 10 according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing the outline of the structure of a cell array in a flash memory 1 according to the embodiment of the present invention
  • FIG. 3 is an illustration about the semiconductor memory apparatus 10 according to the embodiment of the present invention, showing-the transfer process from a page buffer 2 to the flash memory 1 that a memory controller 6 performs for the data objects DN 8 -DN 12 to be written, which are transferred from a host H to the page buffer 2 ;
  • FIG. 4 is an illustration about the semiconductor memory apparatus 10 according to the embodiment of the present invention, showing the first half of the data transfer process from a source block B 0 to a destination block Bn that the memory controller 6 performs following the data transfer process shown in FIG. 3 ;
  • FIG. 5 is an illustration about the semiconductor memory apparatus 10 according to the embodiment of the present invention, showing the second half of the data transfer process from the source block B 0 to the destination block Bn that the memory controller 6 performs following the data transfer process shown in FIG. 3 ;
  • FIG. 6 is a flow chart of the method of writing data by the semiconductor memory apparatus 10 according to the embodiment of the present invention.
  • FIG. 7 is a flow chart of transfers of the data objects DN(q) ⁇ DN(q+m ⁇ 1) to be written from the page buffer 2 to the destination block Bn (Step 7 ), about the method of writing data by the semiconductor memory apparatus 10 according to the embodiment of the present invention;
  • FIG. 8 is a flow chart of data transfers from the source block B 0 to the destination block Bn (Step S 8 ), about the method of writing data by the semiconductor memory apparatus 10 according to the embodiment of the present invention;
  • FIG. 9 is an illustration for demonstrating a renewal or an addition of pages in one block of the flash memory 1 by a conventional semiconductor-memory apparatus.
  • FIG. 1 is the block diagram showing the semiconductor memory apparatus 10 according to the embodiment of the present invention.
  • the semiconductor memory apparatus 10 is connected with the host H through an external bus 7 .
  • the host H is, for example, an information processing device such as a personal computer, or a mobile appliance such as a PDA and a cellular phone.
  • the semiconductor memory apparatus 10 may be provided for the host H either internally or externally.
  • the flash memory 1 is preferably a NAND-type EEPROM (electrically erasable programmable ROM).
  • FIG. 2 is the schematic diagram showing the outline of the structure of the cell array in the flash memory 1 .
  • the cell array is a cluster of many blocks B 0 , B 1 , B 2 , . . . Each block includes 32 pages, for example.
  • the head block B 0 includes 32 pages P 0 -P 31 , for example.
  • Other blocks B 1 , B 2 , . . . are alike.
  • data items are only collectively erased on a block-by-block basis.
  • Each page includes the two-dimensional arrangement of (512+16)-column ⁇ 8 memory cells.
  • the redundant area RA stores the attributes of the data items stored in the data area DA of the page to which the redundant area belongs.
  • the redundant area includes, for example, the logical address corresponding to the page to which the redundant area belongs, a flag showing whether or not the page is blank, a flag showing whether the data items written on the page are enabled or disabled (in other words, the access by the host is allowed or inhibited), and/or the error-detecting codes (e.g., CRC) of the data items.
  • CRC error-detecting codes
  • the data streams are divided into pages and written into the data areas DA of the respective pages, from the top page of the blank block in sequence.
  • the logical page order in each block may shift from the physical page order in the block in a cyclic manner as follows: In FIG. 2 , for example, the top page (the first page) P 0 , the second page P 1 , . . . , the 30th page P 29 , the 31st page P 30 , and the final page (the 32nd page) P 31 of the head block B 0 store data items D 2 , D 3 , . . . , D 31 , D 0 , and D 1 , respectively.
  • numerical values beside the reference symbol P showing the pages of the head block B 0 indicate the physical page numbers of the respective pages. Furthermore, numerical values beside the reference symbol D showing data items stored in the pages P 0 -P 31 indicate the logical page numbers of the respective pages. Then, each logical page number of the pages P 0 -P 31 of the head block B 0 shifts from the physical page number by a constant number, “2”.
  • the cyclic deviations between the logical page orders and the physical page orders generally vary among the blocks.
  • This cyclic deviation of a block is referred to as a page offset of the block.
  • the page offset of a block is the same as the logical page number of the top page of the block.
  • the page offsets are represented by integers between 0 and 31 inclusive and stored in page-offset storage areas of the respective blocks.
  • the page-offset storage area is, for example, the redundant area RA of the first page of each block.
  • the page offset “2” of the head block B 0 is stored in the redundant area RA of the top page P 0 .
  • the page offset may be stored in the redundant area RA of one of the pages except the top page.
  • the stored data item may be the logical page number of the page instead of the page offset itself.
  • the semiconductor memory apparatus 10 can calculate the page offset from the deviation between the logical page number and the physical page number of the page.
  • a host interface 3 relays data between the external bus 7 and the internal bus 8 , and realizes data exchanges between functional sections in the semiconductor memory apparatus 10 and the host H.
  • the host interface 3 decodes the read command and sends the logical address to specify a read target page to the address conversion section 4 .
  • the host interface 3 further sends the data objects to be read, which are transferred from the flash memory 1 to the page buffer 2 by the memory controller 6 , through the external bus 7 to the host H.
  • the host interface 3 decodes the write command and sends the logical address to specify the write target page to the address conversion section 4 .
  • the host interface 3 further transfers the data objects to be written, which are received from the host H, through the internal bus 8 to the page buffer 2 .
  • the page buffer 2 is an SRAM preferably, and temporarily stores the data items exchanged between the host interface 3 and the memory controller 6 .
  • the storage capacity of the page buffer 2 is 512 bytes, for example, and substantially the same as the storage capacity of (the data area DA of) one page in the flash memory 1 .
  • the address conversion section 4 receives the logical address from the host interface 3 .
  • the logical address for example, the upper bits show the logical address of one block in the flash memory 1 (a logical block address), and the lower bits show the logical page number of one page in the block.
  • the address conversion section 4 first divides the logical address input into the logical block address and the logical page number.
  • the address conversion section 4 next accesses an address-conversion-table storage section 5 .
  • the address-conversion-table storage section 5 is a RAM preferably, and stores a logical/physical address conversion table L.
  • the address conversion section 4 converts the logical block address into the physical address of the corresponding block, based on the logical/physical address conversion table L.
  • the logical/physical address conversion table L is a table bringing a-logical block address allocated to each enabled block in the flash memory 1 into correspondence with the physical address of the block.
  • the address conversion section 4 scans the redundant areas RA of the top pages of blocks of the flash memory 1 at the start up of the semiconductor memory apparatus 10 , for example, thereby listing the logical block addresses of the enabled blocks in the flash memory 1 .
  • the logical/physical address conversion table L is created and stored in the address-conversion-table storage section 5 .
  • the address-conversion-table storage section 5 stores, for example, a flag F for each block of the flash memory 1 to show whether or not to be a blank block, in addition to the logical/physical address conversion table L.
  • the address conversion section 4 checks each block in the flash memory 1 for a blank block, based do the data stored in the redundant area RA of the block, and determines the above-described flag F.
  • the address conversion section 4 further stores the flags F into the address-conversion-table storage section 5 .
  • the memory controller 6 identifies one page in the flash memory 1 based on the pair of the physical address and the logical page number, which is received from the address conversion section 4 .
  • the memory controller 6 performs data reading/writing for the identified page. For example, at the receipt of a read command from the host H, the memory controller 6 first receives from the address conversion section 4 the physical address that is converted from the destination address of the read command, and identifies a block corresponding to the physical address in the flash memory 1 . The memory controller 6 next reads the page offset of the block from the redundant area of the top page of the block. The memory controller 6 identifies the physical page number corresponding to the logical page number, based on the page offset and the logical page number received from the address conversion section 4 . The memory controller 6 reads from the flash memory 1 the data item stored on the page having the physical page number, and transfers the data item to the page buffer 2 .
  • FIGS. 3-5 are illustrations for demonstrating a method of writing data by the memory controller 6 .
  • FIG. 3 shows a transfer process from the page buffer 2 to the flash memory 1 , which the memory controller 6 performs for the data objects DN 8 -DN 12 to be written (numerical values beside the reference symbol DN show logical page numbers) that are transferred from the host H to the page buffer 2 .
  • DN 8 -DN 12 number of data objects
  • DN show logical page numbers
  • FIG. 4 and FIG. 5 respectively show the first and second halves of the data transfer process from a source block B 0 to a destination block Bn that the memory controller 6 performs following the data transfer process shown in FIG. 3 .
  • the memory controller 6 first receives a physical address from the address conversion section 4 . Then, the memory controller 6 identifies a block corresponding to the physical address as a source block in the flash memory 1 . In FIGS. 3-5 , for example, the head block (the first block) B 0 is identified as the source block. The memory controller 6 next reads the page offset “2” of the source block B 0 from the redundant area RA of the top page (the first page) P 0 of the source block B 0 . Data items D 0 , D 1 , . . . , and D 31 (numerical values beside the reference symbol D show the logical page numbers of the pages storing the data items) are stored in the data areas DA of the source block B 0 .
  • the logical page numbers of the pages P 0 -P 31 shift from the physical page numbers by the page offset “2” in a cyclic manner, as shown in FIG. 3 .
  • the pages P 0 , P 1 , . . . , and P 31 may include a page in a state of being erased (or a blank page).
  • the difference generally ranges from ⁇ 31 to 31 inclusive.
  • the memory controller 6 identifies the difference as the physical page number of the write target page.
  • the physical page number of the write target page is determined as an integer between or equal to 0 and 31.
  • the seventh page P 6 of the source block B 0 is identified as the write target page.
  • the memory controller 6 accesses the address-conversion-table storage section 5 and, based on the flags F stored there, selects one of blank blocks in the flash memory 1 as a destination block.
  • the (n+1)th block Bn (n ⁇ 1) is selected as the destination block.
  • Any of the 32 pages Q 0 , Q 1 , . . . , and Q 31 (numerical values beside the reference symbol Q show physical page numbers) in the destination block Bn is blank.
  • the host interface 3 receives data objects DN 8 -DN 12 to be written that is sent from the host H, and writes the data objects into the page buffer 2 page by page.
  • the memory controller 6 transfers the data objects DN 8 -DN 12 from the page buffer 2 to the destination block Bn page by page (see the arrow shown in FIG. 3 .)
  • the data objects DN 8 -DN 12 are written page by page, starting from the top page Q 0 of the destination block Bn in sequence. Thereby, the data objects DN 8 -DN 12 are stored in the data areas DA of the top page Q 0 through the fifth page Q 4 of the destination block Bn (see FIG. 3 .)
  • the memory controller 6 further determines the logical page number “8” of the write target page as the page offset of the destination block Bn, and writes the page offset into the redundant area RA of the top page Q 0 of the destination block Bn.
  • the memory controller 6 Every time when transferring the data objects DN 8 -DN 12 from the page buffer 2 to the destination block Bn, the memory controller 6 counts the number of times of the transfer.
  • the host H notifies the semiconductor memory apparatus 10 of the end of sending of data objects to be written, using a predetermined command.
  • the memory controller 6 detects the command through the host interface 3 .
  • the memory controller 6 determines the number of pages, “5”, of the storage region Q 0 -Q 4 of the data objects DN 8 -DN 12 , based on the above-described number of times of the transfer. Then, the memory controller 6 further starts the data transfer from the source block B 0 to the destination block Bn.
  • the host H may provide the semiconductor memory apparatus 10 with prior notification of the page number “5” required for the storage of the data objects DN 8 -DN 12 . In that case, when the above-described number of times of the transfer reaches the notified page number “5”, the memory controller 6 starts the data transfer from the source block B 0 to the destination block Bn.
  • the page buffer 2 Before the start of a data transfer from the source block B 0 to the destination block Bn (which is hereafter referred to as a block transfer), the page buffer 2 is freed.
  • the memory controller 6 using the page buffer 2 , performs the block transfer as follows (see FIG. 4 and FIG. 5 ): First, the fifth page (the 12th page) P 11 counted from the write target page (the seventh page) P 6 of the source block B 0 is identified as the start page of the block transfer (which is hereafter referred to as a transfer start page) (see FIG. 4 .) Next, data items D 13 , . . .
  • the data item D 14 in the page buffer 2 is written onto the seventh page Q 6 of the destination block Bn (see the arrow W 2 shown in FIG. 4 .)
  • the data items D 13 , D 14 , . . . , D 31 , D 0 , and D 1 on the 12th page P 11 through the final page P 31 of the source block B 0 are transferred to the data areas DA of the sixth page Q 5 through the 26th page Q 25 of the destination block Bn.
  • the memory controller 6 next transfers data items D 2 , D 3 , . . . , and D 7 of the to page P 0 through the page (the sixth page) P 5 just before the write target page P 6 of the source block B 0 to the destination block Bn as follows (see FIG. 5 ): First, the data item D 2 on the top page P 0 of the source block B 0 is read into the page buffer 2 (see the arrow R 26 shown in FIG. 5 .) Furthermore, the data item D 2 is written from the page buffer 2 onto the 27th page Q 26 of the destination block Bn. Next, the data item D 3 ) on the second page P 1 of the source block B 0 is similarly transferred via the page buffer 2 to the 28th page Q 27 of the destination block Bn.
  • the physical page number of the transfer start page is equal to the sum of the physical page number of the write target page and the number of pages of the storage region of the data objects to be written.
  • the value of the sum minus the total page number is identified as the physical page number of the transfer start page.
  • the memory controller 6 transfers the data items on the transfer start page through the page just before the write target page to the destination block Bn in a manner similar to the data transfers shown in FIG. 5 .
  • the data items D 8 -D 12 on the pages having the logical page numbers “8” through “12” are replaced with the new data items DN 8 -DN 12 in the destination block Bn, in contrast to the source block B 0 (see FIG. 5 .) Furthermore, the logical page order changes in a cyclic manner, and the page offset changes from “2” to “8”.
  • the memory controller 6 disables or collectively erases data items in the source block B 0 .
  • the address conversion section 4 updates the logical/physical address conversion table L, and brings the logical address corresponding to the physical address of the source block B 0 into correspondence with the physical-address of the destination block Bn.
  • the address conversion section 4 further resets the flag F stored in the address-conversion-table storage section 5 to show that the source block B 0 is a blank block.
  • the memory controller 6 performs the data writing from the page buffer 2 into the destination block Bn, starting from the top page Q 0 of the destination block Bn and finishing at the final page Q 31 as described above.
  • This writing order is the same as that of conventional apparatuses. Accordingly, the same configuration as that of the conventional apparatuses may be used for the data writing from the page buffer into the destination block.
  • FIG. 6 is the flow chart of the method of writing data by the semiconductor memory apparatus 10 .
  • a data write command is sent out from the host H.
  • the host interface 3 receives the data write command and decodes it into the logical address of a write target page.
  • the host interface 3 further sends the logical address to the address conversion section 4 .
  • the address conversion section 4 receives the logical address from the host interface 3 .
  • the address conversion section 4 then consults the logical/physical address conversion table L and converts the logical address into the pair of the physical address of the source block B 0 and the logical page number q (0 ⁇ q ⁇ 31) of the write target page.
  • the address conversion section 4 further sends the pair to the memory controller 6 .
  • the memory controller 6 accesses the address-conversion-table storage section 5 and selects one of blank blocks, Bn in the flash memory 1 as a destination block, based on the flags F.
  • the source block B 0 is a blank block
  • the source block B 0 itself may be selected as the destination block Bn. In that case, the following steps S 8 and S 9 are skipped.
  • the memory controller 6 writes the logical page number q received from the address conversion section 4 into the redundant area RA of the top page Q 0 of the destination block Bn (see FIG. 3 .)
  • the memory controller 6 reads the page offset p (0 ⁇ p ⁇ 31) of the source block B 0 from the redundant area RA of the top page P 0 of the source block B 0 .
  • the memory controller 6 determines the difference between the logical page number q of the write target page and the page offset p of the source block B 0 .
  • the host interface 3 receives data objects DN(q), DN(q+1), . . . to be written from the host H (reference symbols in parentheses beside the reference symbol DN show logical page numbers.)
  • the host interface 3 transfers the data objects DN(q), DN(q+1), . . . to the page buffer 2 page by page.
  • the host interface 3 further notifies the memory controller 6 of the transfer.
  • the memory controller 6 transfers the data objects DN(q), DN(q+1), . . . in the page buffer 2 every notification from the host interface 3 , starting from the top page Q 0 of the destination block Bn in sequence.
  • FIG. 7 is the flow chart of the transfers.
  • the memory controller 6 starts a data transfer from the source block B 0 to the destination block Bn (a block transfer).
  • FIG. 8 is the flow chart of the block transfer.
  • the memory controller 6 collectively erases or disables data items in the source block B 0 .
  • the address conversion section 4 then updates the logical/physical address conversion table L, and brings the logical address corresponding to the physical address of the source block B 0 into correspondence with the physical address of the destination block Bn.
  • the address conversion section 4 further resets the flag F stored in the address-conversion-table storage section 5 to show that the source block B 0 is a blank block.
  • the semiconductor memory apparatus 10 uses the page buffer 2 as a saving space of the data items in the original block, thereby including no saving buffer apart from the page buffer 2 , in contrast to conventional apparatuses.
  • the semiconductor memory apparatus has RAMs smaller in size than those of the conventional apparatuses. Therefore, a small size of the whole apparatus can be maintained.
  • the semiconductor memory apparatus realizes miniaturization through the integration of page buffer and saving buffer. Therefore, the present invention has extremely high industrial applicability.

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