USRE41031E1 - Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states - Google Patents
Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states Download PDFInfo
- Publication number
- USRE41031E1 USRE41031E1 US11/367,051 US36705106A USRE41031E US RE41031 E1 USRE41031 E1 US RE41031E1 US 36705106 A US36705106 A US 36705106A US RE41031 E USRE41031 E US RE41031E
- Authority
- US
- United States
- Prior art keywords
- signal
- clock signal
- transitions
- frequency
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 81
- 230000007704 transition Effects 0.000 claims abstract description 176
- 230000004044 response Effects 0.000 claims description 69
- 238000000034 method Methods 0.000 claims description 17
- 230000007423 decrease Effects 0.000 claims description 15
- 230000003111 delayed effect Effects 0.000 claims description 11
- 230000008859 change Effects 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 9
- 230000003534 oscillatory effect Effects 0.000 claims description 3
- 230000001419 dependent effect Effects 0.000 claims 8
- 230000003247 decreasing effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000003786 synthesis reaction Methods 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000002194 synthesizing effect Effects 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Definitions
- the present invention relates to a frequency control system for extracting a clock signal from a high bit rate digital signal or for synthesizing a frequency.
- the system comprises a circuit loop including a voltage-controlled oscillator (VCO) slaved to an incoming signal of unstable frequency.
- VCO voltage-controlled oscillator
- the frequency control of a VCO is used in a receiver in order to extract from a digital data signal an original clock signal produced by a transmitter which transmitted the data signal.
- Frequency synthesis using a VCO is used in radio transmitters and receivers when it is necessary to generate precise frequencies for selecting a channel.
- the main technical problem is to extract the clock signal contained in the received digital data signal, which is affected by noise, i.e. which contains jitter, and to synthesize a precise frequency based on an unstable reference frequency.
- the invention has applications in the field of digital transmissions at high bit rates, up to several hundred Mbit/s, for recovering the clock signal needed to process the received data, and in the field of radio equipments, for synthesizing high frequencies, typically up to a few GHz.
- phase-locked loop which comprises a VCO, a frequency divider which can be programmable and which is connected to the output of the oscillator to provide a divided frequency signal, and a phase comparator which delivers an error signal based on comparing the phases of the divided frequency signal and a reference signal.
- PLL phase-locked loop
- a first difficulty encountered in the prior art, when the required frequency is high, is that of providing a divide-by-N frequency divider which is needed to synthesize any frequency equal to k.N.Fr where k is a constant, N is a variable coefficient and Fr is the frequency of the reference signal. If N is an integer, frequencies multiple of the frequency Fr of the reference signal are generated by the oscillator VCO. However, it is routine practice not to limit N to integer values, which increases the complexity of the frequency divider included in the loop and leads to insurmountable technical implementation constraints at high frequencies.
- a second difficulty results from the necessity to apply a very stable reference signal to the phase comparator; if this is not achieved, noise in the reference signal is multiplied by a factor k.N in the synthesized signal output by the oscillator.
- the main object of this invention is to overcome the aforementioned difficulties by providing a frequency control system which is based on comparing the frequencies of an incoming digital signal which has an unstable clock frequency and a clock signal generated directly or indirectly by an oscillator VCO and which is used both to extract the clock signal and for frequency synthesis, with the aim of tolerating variation in the frequency of the incoming signal about a mean value without any effect on the clock signal to be extracted or on the clock signal to be synthesized, whose frequency remains stable even in the presence of high jitter in the incoming signal.
- a frequency control system comprising voltage-controlled oscillator means generating a clock signal, means receiving a digital incoming signal with unstable frequency for sampling the clock signal at two pairs of times corresponding to two consecutive transitions of the incoming signal in response to each of predetermined transitions of the incoming signal, the times of one pair being separated by a predetermined time-delay at most equal to half the period of the clock signal, to produce four state signals of the clock signal, a frequency comparator combining the four state signals to form an upcounting signal only when the frequency of the clock signal is substantially less than the frequency of the incoming signal and to form a downcounting signal only when the frequency of the clock signal is greater than the frequency of the incoming signal, and upcounting and downcounting means for respectively upcounting and downcounting predetermined transitions of the incoming signal in response to the upcounting signal and the downcounting signal in order to apply a control voltage depending on a content of the upcounting and downcounting means to the oscillatory means.
- the frequency comparison in accordance with the invention is effected on the basis of two transitions of the incoming signal and not on one transition, as is generally the case in the prior art.
- the four state signals resulting from sampling the incoming signals at the two pairs of times for each transition can be combined by means for producing the upcounting signal for as long as three of the state signals corresponding to consecutive sampling times of the clock signal are identical, and means for producing the downcounting signal for as long as one of two state signals corresponding to sampling times of the clock signal lying between sampling times of the clock signal corresponding to the other two state signals is different from the other three state signals.
- the functions of the aforementioned two producing means are implemented in the frequency comparator by means of a first EXCLUSIVE-OR gate receiving two state signals corresponding to sampling times of the clock signal between which are sampling times of the clock signal corresponding to the other two state signals, a second EXCLUSIVE-OR gate receiving the other two state signals, a first AND gate connected directly to the first EXCLUSIVE-OR gate and via an inverter to the second EXCLUSIVE-OR gate to produce said upcounting signal and a second AND gate connected directly to the second EXCLUSIVE-OR gate and via an inverter to the first EXCLUSIVE-OR gate to produce the downcounting signal.
- the sampling means comprises preferably means for detecting predetermined transitions in the incoming signal in order to produce a transition signal and another transition signal delayed by the predetermined time-delay, and two pairs of flip-flops respectively producing the state signals.
- Each pair of flip-flops has a first flip-flop receiving the clock signal and a second flip-flop having an input connected to the direct output of the first flip-flop. The transition signal and the delayed transition signal are respectively applied to clock inputs of the pairs of flip-flops.
- the sampling means is entirely digital.
- the transition detecting means comprises a divide-by-four frequency divider to produce a clock signal at half the frequency of the incoming signal, and means for selecting a transition of said incoming signal and a transition in the complementary signal of the incoming signal when it has been complemented, during one half-period in two of the half-frequency clock signal in order to produce the transition signal and the delayed transition signal, respectively.
- the system comprises means connected to the sampling means for comparing the phases of the incoming signal and the clock signal as a function of two of the four state signals in order to select from the clock signal and the complementary signal thereof an outgoing clock signal which is more in phase with the incoming signal and which is used to read the incoming signal.
- the outgoing clock signal is the recovered clock signal originally produced by the transmitter.
- the phase comparing means comprises latch logic means connected to the sampling means for selecting from the clock signal and the complementary signal thereof an outgoing clock signal which is more in phase with the incoming signal when the state signals produced by the first or second flip-flops of said pairs of flip-flops are respectively at first and second states and at second and first states, and a flip-flop for reading the incoming signal as a function of the outgoing clock signal.
- the frequency control system When the frequency control system is used to synthesize frequencies, it comprises divider means for generating the input signal to be applied to the sampling means in the form of an unstable reference clock signal having a mean frequency over a respective number of periods equal to a programmed frequency from a unit clock signal having a stable frequency not less than four times the programmed frequency, the ratio between the programmed frequency and the respective number of periods being constant.
- the frequency of the unit clock signal is therefore more than four times the highest frequency that can be programmed in the programmable frequency divider.
- the reference clock signal has a variable frequency resulting from programmed integer or non-integer division of the stable frequency of the unit clock signal, which is delivered by a quartz-crystal-controlled clock, for example. Variation of the reference signal frequency is inhibited in the control loop consisting essentially of the sampling means, the frequency comparator, the upcounting and downcounting means and the oscillator, with the result that the synthesized frequency produced by the oscillator is the required stable frequency, which is equal to a multiple of the mean reference clock frequency.
- the invention replaces the programmable frequency divider of prior art synthesis loops with a fixed frequency divider.
- Frequency divider means comprises in a preferred embodiment of the invention an adder and a buffer register clocked at the frequency of the unit clock signal and storing a sum at outputs of the adder, wherein the adder adding the sum to the respective number associated with the programmed frequency.
- frequency divider means comprises a divide-by-two frequency divider receiving the most significant bit of the sum from the buffer register to generate the reference clock signal.
- oscillatory means comprises at least one voltage-controlled oscillator controlled by the upcounting and downcounting means via a loop filter, and a frequency divider for dividing the frequency of the signal generated by the oscillator by a fixed ratio in order to generate the clock signal.
- the fixed ratio is preferably a power of two.
- the loop filter filters in particular harmonics of the unit clock signal resulting from frequency division in the programmable frequency divider.
- FIG. 1 is a schematic block diagram of a clock extractor circuit according to the invention
- FIG. 2 shows in detail a sampling circuit included in the clock extractor circuit shown in FIG. 1;
- FIG. 3 shows in detail a phase comparator included in the clock extractor circuit shown in FIG. 1;
- FIG. 4 shows in detail a frequency comparator included in the clock extractor circuit shown in FIG. 1;
- FIG. 5 is a block diagram of a frequency synthesizer according to the invention.
- FIG. 5 shows in detail a programmable frequency divider included in the frequency synthesizer shown in FIG. 6;
- FIG. 7 shows in detail a sampling circuit included in the frequency synthesizer shown in FIG. 5.
- a frequency control system serving as a clock extractor circuit EH in telecommunication terminal or receiver includes a phase and frequency comparator CPF and a voltage-controlled oscillator VCO.
- the comparator CPF has two inputs to which are applied a digital incoming data signal Din, which is reshaped after transmission by a telecommunication transmitter, and a clock signal H supplied by the oscillator VCO.
- comparing the phases of the signals Din and H produces an outgoing data signal Dout and an outgoing recovered clock signal Hout which are synchronized and in phase.
- Comparing the frequencies of the signals Din and H in the comparator CPF produces a variable voltage analog control signal VC for direct control of the oscillator VCO, in order to generate the clock signal H having a frequency set to the mean clock frequency of the data signal Din.
- phase and frequency comparator CPF The phase is compared in the phase and frequency comparator CPF by means of a four-state sampling circuit 1 and a phase comparator 2 and the frequency is compared by means of sampling circuit 1 , a frequency comparator 3 , an upcounter-downcounter 4 and a digital-to-analog converter (DAC) 5 .
- DAC digital-to-analog converter
- the sampling circuit 1 comprises an EXCLUSIVE-OR gate 10 having inputs connected to the input terminal 1 E of the circuit EH for the data signal Din, both directly and via a delay line 11 , and an output connected to two cascaded delay lines 12 and 13 .
- the third delay line 13 supplies a sampling signal HE at a clock input C of the upcounter-downcounter 4 .
- the clock signal H supplied by the oscillator VCO is applied to data inputs of first flip-flops 14 and 16 of two cascaded pairs of D-type flip-flops 14 - 15 and 16 - 17 .
- the clock inputs of the flip-flops 14 and 15 of the first pair are connected to the output of the EXCLUSIVE-OR gate 10 and the clock inputs of the flip-flops 16 and 17 of the second pair are connected to the output of the second delay line 12 .
- the Q output of the first flip-flop 14 , 16 is connected to the D input of the second flip-flop 15 , 17 .
- the Q outputs of the flip-flops 14 to 17 constitute respective outputs Q 1 to Q 4 of the four-state sampling circuit 1 respectively connected to four inputs of the frequency comparator 3 . Only the outputs Q 1 and Q 3 of the first flip-flops 14 and 16 of the pairs in the sampling circuit are connected to two clock selection inputs of the phase comparator 2 .
- the sampling circuit 1 supplies to the phase comparator 2 and the frequency comparator 3 the state of the clock signal H produced by the oscillator VCO for each transition of the incoming data signal Din.
- the rising and falling edges of the data signal Din are detected by the EXCLUSIVE-OR gate 10 and the first delay line 11 , which imposes at one input of the gate 10 a short time-delay R 1 relative to the nominal half-period of the incoming data signal Din which is applied directly to the other input of the gate 10 .
- the time-delay R 1 defines the width of the sampling pulses in the transition signal at the output of the EXCLUSIVE-OR gate 10 .
- the sampling pulse supplied by the output of the gate 10 on each change of state of the data signal Din commands storing of the state of the clock signal H in the four D-type flip-flops 14 to 17 .
- the flip-flops 14 and 15 store the state of the signal H in response to a transition of the data signal Din at a time T n and at a time T n-k in response to the preceding transition of the signal Din, respectively.
- the integer k designates a variable number of unit bit periods or unit bit half-periods in the signal Din between two successive transitions.
- the flip-flops 16 and 17 also store two other states of the signal H, but subject to a predetermined time-delay Dt imposed by a transition signal delayed by the second delay line 12 ; thus the flip-flop 16 stores the state of the signal H at time T n +dt and the flip-flop 17 stores the state of the signal H at time T n-k +dt.
- the time-delay dt applied by the delay line 12 is at most equal to TH/2, where TH is the period of the clock signal H to be sampled.
- the third delay line 13 imposes a time-delay R 2 so that the sampling signal HE applied to a clock input of the upcounter-downcounter 4 is in phase with two logic signals H+ and H ⁇ supplied by the frequency comparator 3 , these three signals HE, H+ and H ⁇ being applied to the upcounter-downcounter 4 .
- Each delay line can be implemented using a string of inverters.
- the phase comparator 2 essentially comprises a latch comprising two inverters 20 and 21 , two two-input NAND gates 22 and 23 , a three-input NAND gate 24 , a two-input NAND gate 25 , an inverter 26 , an EXCLUSIVE-OR gate 27 and a D-type flip-flop 28 .
- the output Q 1 of the first flip-flop 14 of the sampling circuit 1 is connected directly to a first input of the NAND gate 22 and via the inverter 21 to a second input of the NAND gate 23 .
- the output Q 3 of the first flip-flop 16 of the second pair in the sampling circuit 1 is connected directly to a first input of the gate 23 and via the inverter 20 to a second input of the gate 22 .
- first inputs of the NAND gates 24 and 25 are respectively connected to the outputs of the gates 22 and 23 and second inputs of the gates 24 and 25 are connected to respective outputs of the gates 25 and 24 .
- a reset input RES of the phase comparator 2 is connected to a third input of the NAND gate 24 and resets the phase comparator when the system EH is switched on by forcing the output of the gate 24 to “1”.
- the output of the gate 24 is also connected via the inverter 26 to a first input of the EXCLUSIVE-OR gate 27 , a second input of which receives the clock signal H from the oscillator VCO.
- the output of the gate 27 supplies the recovered clock signal Hout at the clock input of the flip-flop 28
- the D input of the flip-flop 28 is the same as the input 1 E of the sampling circuit 1 and receives the incoming data signal Din.
- the Q output of the flip-flop 28 supplies the data signal Dout in phase with the clock signal Hout.
- the phase comparator 2 chooses as the clock signal which is more in phase with the data signal Din, either the signal H or its complement H, given that the clock signal H is assumed to be at the “correct” frequency, i.e. synchronized with the mean frequency of the data signal Din by virtue of the processing carried out in the frequency comparator 3 , which is described later.
- the latch 20 - 25 looks for an edge of the clock signal H during each time interval dt.
- the first input of the NAND gate 24 i.e. The R input of the RS flip-flop 24 - 25 , is at “1” and the signals H and Din are substantially in phase; the output of the gate 24 is set to “0” and the gate 27 selects the complemented signal H for reading the data signal Din in the flip-flop 28 .
- the first input of the NAND gate 25 i.e.
- the S input of the RS flip-flop 24 - 25 is at “1” and the signals H and Din are substantially in antiphase; the output of the gate 24 is set to “1” and the gate 27 selects the clock signal H for reading the data signal Din in the flip-flop 28 .
- the inputs of the converters 20 and 21 respectively connected to the first inputs of the NAND gates 23 and 22 are connected to the outputs Q 4 and Q 2 of the sampling circuit instead of the outputs Q 3 and Q 1 .
- the state of the clock signal H in a time interval dt is analyzed on two consecutive transitions T n-k and T n of the data signal Din, instead of on a transition T n as in the phase comparator 2 .
- This analysis requires the four flip-flops 14 to 17 in the sampling circuit 1 to store, in response to each transition of the signal Din detected by the gate 10 , the states Q 2 and Q 4 of the clock signal H at successive times T n-k and T n-k +dt corresponding to a first transition preceding said each transition and the states Q 1 and Q 3 of the clock signal H at the successive times T n and T n +dt corresponding to a second transition coincident with said each transition.
- the phase of the signal H lags that of the data signal Din.
- the signals H and Din are substantially at the same frequency, in phase or in phase-quadrature, or exceptionally at very different frequencies (out of band).
- the frequency comparator 3 deduces that the signal H is too fast.
- the “out of band” decision signifies that the received data signal Din is at much too high or too low a frequency outside the lock-on band of the oscillator VCO or contains non-conform jitter.
- a logic circuit (not shown) implementing the logic function ( Q 1 .Q 3 .Q 2 . Q 4 +Q 1 . Q 3 . Q 2 .Q 4 ) and connected to the four outputs Q 1 to Q 4 of the sampling circuit 1 to produce an error signal.
- the frequency comparator 3 shown in FIG. 4 includes two EXCLUSIVE-OR gates 30 and 31 , two inverters 32 and 33 and two two-input AND gates 34 and 35 .
- the outputs Q 1 and Q 4 of the sampling circuit 1 are connected to the inputs of the gate 30
- the outputs Q 2 and Q 3 of the sampling circuit 1 are connected to the inputs of the gate 31 .
- the output of the gate 30 is connected directly to a first input of the gate 34 and via the inverter 32 to a second input of the gate 35 .
- the output of the gate 31 is connected directly to a first input of the gate 35 and via the inverter 33 to a second input of the gate 34 .
- the outputs of the gates 34 and 35 supply the logic signals H+ and H ⁇ , respectively.
- the frequency comparator 3 analyzes the sense of the timing error between the incoming data signal Din and the clock signal H from the oscillator VCO.
- the sense of this error is represented by the states of the logic signals H+ and H ⁇ which are respectively applied to an upcounting input U and a downcounting input D of the upcounter-downcounter 4 .
- the upcounting logic signal H+ sets the upcounter-downcounter 4 to the upcounting mode so that each pulse of the sampling signal HE increments the upcounter-downcounter by one unit and thereby increases the control voltage VC of the oscillator VCO to increase the frequency of the clock signal H, which was too slow.
- the downcounting logic signal H ⁇ sets the upcounter-downcounter 4 to the downcounting mode so that each pulse of the sampling signal HE decrements the upcounter-downcounter by one unit and thereby decreases the control voltage VC of the oscillator VCO to decrease the frequency of the clock signal H, which was too fast.
- the upcounter-downcounter thus “smoothes” fluctuations in the clock frequency of the incoming signal so that in the long term and on average the oscillator VCO operates at the mean frequency of this clock frequency.
- the digital-to-analog converter 5 converts the variable digital content of the upcounter-downcounter 4 into the control voltage VC applied to the control input of the oscillator VCO.
- the capacity of the upcounter-downcounter 4 depends on the precision required of the frequency produced by the oscillator VCO.
- a second embodiment of the frequency control system according to the invention is a frequency synthesizer SF as shown in FIG. 5.
- the synthesizer includes a sampling circuit 8 which is preferably modified compared to the sampling circuit 1 , in the manner explained hereinafter, the frequency comparator 3 , the upcounter-downcounter 4 , the digital-to-analog converter 5 , a low-pass loop filter FL and the voltage-controlled oscillator VCO.
- a fixed frequency divider 6 connects the output of the oscillator VCO, which produces a synthesized clock signal HS, to the clock signal input 1 H of the sampling circuit 8 .
- the divider 6 divides the frequency of the synthesized signal HS by an integer ratio M to produce a divided clock signal HD.
- the frequency synthesizer SF therefore uses loop circuits for the frequency comparison, like the clock extractor circuit EH.
- the frequency synthesizer SF also comprises a programmable frequency divider 7 for applying a reference clock signal Hr at a programmable frequency to the incoming data signal input 1 E of the sampling circuit 8 .
- the frequency FS of the clock signal HS from the oscillator VCO is divided by the fixed integer ratio M in the frequency divider 6 of the frequency synthesizer SF.
- M is an integer and is preferably a power of 2. If Fr denotes the frequency of the reference clock signal Fr, FS is equal to Fr.M when the oscillator VCO is operating under steady state conditions.
- the period TB corresponding to the frequency FB contains the greatest number of period units TU of all the periods corresponding to the reference frequencies Fr 1 to FrI; let N denote the aforementioned integer number.
- computing the period Tri of the reference signal Hri amounts to computing how many times the number Pi is contained in the number N.
- the invention proposes to add the number Pi to itself at the timing rate TU until the number N is obtained and on each computation to produce a sample at “0” if the computation result is less than N/2 and a sample with value “1” otherwise.
- the number Pi associated with the frequency Fri of the reference signal Hri to be synthesized is not necessarily an integer factor of the integer N after the computation.
- Let r 1 , r 2 , r 3 , . . . r Pi denote overflows less than Pi occurring in the last period unit TU for the first period Tri, then for the second period Tri succeeding the first period, then for the third period Tri succeeding the second period, and so on, up to the (Pi)th period.
- the successive “periods” Tri are written:
- T 1 TU(N + r 1 )/Pi
- second period Tri: T 2 TU(N ⁇ r 1 + r 2 )/Pi
- third period Tri: T 3 TU(N ⁇ r 2 + r 3 )/Pi
- Pth period Tri: T Pi TU(N ⁇ r Pi ⁇ 1 + r Pi )/Pi, the numbers (N+r 1 ), (N ⁇ r 1 +r 2 ), (N ⁇ r 2 +r 3 ), . . . , (N ⁇ r Pi-1 +r Pi ) being integer multiples of Pi.
- the mean of the periods generated by the synthesizer is indeed equal to the required value Tri.
- the generated signal is frequency-modulated because a period Tri is generated to within TU in each computation cycle that corresponds to the first, second, third, . . . or Pth period Tri.
- the maximum amplitude of the jitter is therefore equal to TU.
- the frequency comparator 3 allows a maximum jitter equal to the half-period of the reference signal Hr applied to the input 1 E of the sampling circuit 8 .
- the inegality TU ⁇ TrI/2 must be respective, TrI being the smallest period of the set of periods Tr 1 to TrI; thus the condition for the synthesizer to function is FU ⁇ 2.FrI.
- FIG. 6 shows the programmable frequency divider 7 having the functional characteristics explained hereinabove. It comprises an adder 70 having two input ports A 1 and A 2 , a buffer register 71 and a divide-by-2 frequency divider including a flip-flop 72 .
- the register 71 has an input port connected to the output port of the adder 70 , its q outputs connected to the second input port A 2 of the adder and its most significant bit output BR(q ⁇ 1) connected to the clock input of the flip-flop 72 .
- the register 71 is clocked by a clock signal HU having a frequency greater than 4.Fr.
- the clock signal HU is stable and is generated by a quartz-crystal-controlled clock, typically operating at a frequency of a few megahertz, constituting a very low noise source of pure frequency.
- the flip-flop 72 forms a divide-by-2 frequency divider and has a complimentary output Q connected to its input D and supplies the selected reference clock signal Hr at an output Q.
- the binary word Pi on q bits and the cumulative result R delivered by the register 71 which registers the word leaving the adder at the timing rate of the frequency unit FU of the period unit signal TU, are therefore added cyclically to the frequency FU.
- the programmable frequency divider 7 does not include any digital comparator to determine the frequency Fri of the clock signal Hri by comparing R and N prior to division by 2 in the flip-flop 72 .
- the invention utilizes the state of the most significant bit BR(q ⁇ 1) of the result word R at the output of the register 71 to form the signal Hri, BR(0) being the least significant bit of the word R.
- BR(q ⁇ 1) is equal to “0”; otherwise BR(q ⁇ 1) is equal to “1”; the reference clock signal Hr is then produced by the Q output of the flip-flop 72 by halving the frequency of the most significant bit signal BR(q ⁇ 1).
- Fr 1 2.34374; 2.44140625; 2.5390625; 2.63671875 et
- the pitch p of the synthesizer is equal to 0.09765625 MHz
- the periodic reference signal Hr is applied to the input 1 E for the data signal Din
- the clock signal HD from the divide-by-M frequency divider 6 connected to the oscillator VCO is applied to the input 1 H.
- Fr is the frequency of the clock signal Hr sampling the signal HD having the frequency FD after division by M of the frequency HS of the synthesized clock signal FS.
- the sampling circuit 8 comprises digital means for producing a transition signal H 1 and a delayed transition signal H 2 delayed by a delay dt for sampling the clock signal HD applied to the input 1 H.
- the sampling circuit 8 comprises the delay line 13 and the two pairs of flip-flops 14 - 15 and 16 - 17 , and entirely digital means 80 - 85 instead of the delay lines 11 and 12 and the EXCLUSIVE-OR gate 10 in circuit 1 (FIG. 2).
- the digital means are downstream of the input 1 E which receives the reference clock signal Hr supplied by the programmable frequency divider 5 , i.e.
- the digital means 80 - 85 use a frequency Fr higher than those of the transition signals H 1 and H 2 used for sampling and divide the frequency Fr to obtain the correct frequency FD at the clock inputs of the sampling flip-flops 14 to 17 . This division provides perfect control of the time-delay dt.
- the clock inputs of the flip-flops 80 and 81 , a first input of the AND gate 83 and the input of the inverter 84 receive the clock signal Hr.
- the flip-flops 80 and 81 forming a divide-by-4 frequency divider, the complemented output Q of the second flip-flop 81 is connected to the D input of the first flip-flop 80
- the outputs Q of the flip-flops 80 and 81 produce two logic signals at the frequency Fr/4 phase shifted by 2Tr and are connected to respective inputs of the EXCLUSIVE-OR gate 82
- the output of the gate 82 therefore produces a signal at the frequency Fr/2 and is connected to a second input of the AND gate 83 and to a first input of the AND gate 85 , which has a second input connected to the output of the inverter 84
- the pulses of width Tr of the signal of period 2Tr at the output of the EXCLUSIVE-OR gate 82 select one in two periods of the signal Hr in the AND gate 83 to constitute the transition signal H 1 of width Tr/2 and of period 2Tr applied to the clock inputs of the flip-flops 14 and 15 of the first pair.
- the two clock signals H 1 and H 2 sample the signal HD from the oscillator VCO after division by M at times T n and T n +Tr/2.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
| Q3 | Output | 24 | |
|
0 | 0 | unchanged | unchanged | ||
0 | 1 | 0 |
|
||
1 | 0 | 1 | |
||
1 | 1 | unchanged | unchanged | ||
Tn | Tn + dt | Tn−k | Tn−k + dt | |||
Q1 | Q3 | Q2 | Q4 | Decision | H− | |
0 | 0 | 1 | 0 | H too fast | 1 | 0 |
0 | 0 | 0 | 1 | H too slow | 0 | 1 |
0 | 0 | 0 | 0 | no |
0 | 0 |
0 | 0 | 1 | 1 | no |
0 | 0 |
0 | 1 | 1 | 1 | H too slow | 0 | 1 |
0 | 1 | 0 | 0 | H too fast | 1 | 0 |
0 | 1 | 0 | 1 | no |
0 | 0 |
0 | 1 | 1 | 0 | H out of |
0 | 0 |
1 | 0 | 1 | 1 | H too fast | 1 | 0 |
1 | 0 | 0 | 0 | H too slow | 0 | 1 |
1 | 0 | 1 | 0 | no |
0 | 0 |
1 | 0 | 0 | 1 | H out of |
0 | 0 |
1 | 1 | 1 | 0 | H too slow | 0 | 1 |
1 | 1 | 0 | 1 | H too fast | 1 | 0 |
1 | 1 | 1 | 1 | no |
0 | 0 |
1 | 1 | 0 | 0 | no |
0 | 0 |
H+=(Q1.
H−=(Q2.
-
- TB=N.TU=1/p
- frequency unit FU=1/TU=p.N, and
- the period of the selected reference signal Tri=1/Fri=TU.N/Pi.
first period | Tri: T1 = TU(N + r1)/Pi; | ||
second period | Tri: T2 = TU(N − r1 + r2)/Pi; | ||
third period | Tri: T3 = TU(N − r2 + r3)/Pi; | ||
Pth period | Tri: TPi = TU(N − rPi−1 + rPi)/Pi, | ||
the numbers (N+r1), (N−r1+r2), (N−r2+r3), . . . , (N−rPi-1+rPi) being integer multiples of Pi. The last overflow rPi is equal to zero since the sum of the latter numbers NPi=rPi is a multiple of Pi.
Mean of Tri=
-
- FUmin=2.FrI
- Nmin=FUmin/p,
- N being preferably as N=2q>Nmin;
- FU=p.N
- Tri=TU.N/Pi=1/(p.Pi)
- Fri=p.Pi.
N=26=64 et q=6
HQ=N.p=6.25 MHz
P1=24; P2=25; P3=26; P4=27; P5=28.
dt=TD/4−Tr/2
-
- where TD is the period of the clock signal at the
input 1H. Because the period TD is obtained from the period Tr of the reference signal Hr by integer division by M, the following equation applies:
TD=M.Tr, - from which the time-delay is deduced:
dt=M.Tr/4−Tr/2.
For the smallest time-delay dt=Tr/2 which can be obtained in a digital circuit from a signal of period Tr, the optimum solution deduced from the above equation is M=4.
- where TD is the period of the clock signal at the
Claims (56)
H+=(Q1.
H−=(Q2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/367,051 USRE41031E1 (en) | 1999-04-30 | 2006-03-02 | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9905627A FR2793091B1 (en) | 1999-04-30 | 1999-04-30 | FREQUENCY SERVO DEVICE |
US09/559,524 US6701445B1 (en) | 1999-04-30 | 2000-04-28 | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states |
US11/367,051 USRE41031E1 (en) | 1999-04-30 | 2006-03-02 | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/559,524 Reissue US6701445B1 (en) | 1999-04-30 | 2000-04-28 | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE41031E1 true USRE41031E1 (en) | 2009-12-01 |
Family
ID=9545176
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/559,524 Ceased US6701445B1 (en) | 1999-04-30 | 2000-04-28 | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states |
US11/367,051 Expired - Lifetime USRE41031E1 (en) | 1999-04-30 | 2006-03-02 | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/559,524 Ceased US6701445B1 (en) | 1999-04-30 | 2000-04-28 | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states |
Country Status (5)
Country | Link |
---|---|
US (2) | US6701445B1 (en) |
EP (1) | EP1049285B1 (en) |
JP (1) | JP4628517B2 (en) |
DE (1) | DE60031737T2 (en) |
FR (1) | FR2793091B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070223638A1 (en) * | 2004-05-12 | 2007-09-27 | Thine Electronics, Inc. | Isophase Multiphase Clock Signal Generation Circuit and Serial Digital Data Receiving Circuit Using the Same |
US20080122514A1 (en) * | 2006-11-29 | 2008-05-29 | Konica Minolta Business Technologies, Inc. | Variable frequency clock output circuit and apparatus, motor driving apparatus, and image forming apparatus |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10132403A1 (en) * | 2001-07-09 | 2003-01-23 | Alcatel Sa | Method and device for clock recovery from a data signal |
US6777993B1 (en) * | 2001-08-07 | 2004-08-17 | Altera Corporation | Method and apparatus for adjusting the phase and frequency of a periodic wave |
JP3559781B2 (en) * | 2001-12-27 | 2004-09-02 | エヌティティエレクトロニクス株式会社 | Phase locked loop |
AU2003302953A1 (en) * | 2002-12-13 | 2004-07-09 | Koninklijke Philips Electronics N.V. | Low lock time delay locked loops using time cycle supppressor |
KR100546327B1 (en) * | 2003-06-03 | 2006-01-26 | 삼성전자주식회사 | Feed control system and method thereof |
US7046057B1 (en) * | 2003-11-03 | 2006-05-16 | Hewlett-Packard Development Company, L.P. | System and method for synchronizing devices |
US7475270B1 (en) * | 2003-11-03 | 2009-01-06 | Hewlett-Packard Development Company, L.P. | System and method for waveform sampling |
US7855584B2 (en) * | 2003-12-09 | 2010-12-21 | St-Ericsson Sa | Low lock time delay locked loops using time cycle suppressor |
CN100338875C (en) * | 2004-11-12 | 2007-09-19 | 鸿富锦精密工业(深圳)有限公司 | Clock signal generator |
US7084790B2 (en) * | 2004-12-07 | 2006-08-01 | Stmicroelectronics S.R.L. | Device to effectuate a digital estimate of a periodic electric signal, related method and control system for an electric motor which comprises said device |
US7157953B1 (en) * | 2005-04-12 | 2007-01-02 | Xilinx, Inc. | Circuit for and method of employing a clock signal |
CN1960183B (en) * | 2005-10-31 | 2010-07-28 | 盛群半导体股份有限公司 | Automatic adjusted oscillator with high accuracy |
JP2009159038A (en) * | 2007-12-25 | 2009-07-16 | Hitachi Ltd | Pll circuit |
JP2010056888A (en) * | 2008-08-28 | 2010-03-11 | Elpida Memory Inc | Synchronization control circuit, semiconductor device and control method |
JP2011060364A (en) | 2009-09-08 | 2011-03-24 | Elpida Memory Inc | Clock generating circuit and semiconductor device including the same, and data processing system |
US8933733B2 (en) * | 2013-01-07 | 2015-01-13 | Mediatek Singapore Pte. Ltd. | Method and system for fast synchronized dynamic switching of a reconfigurable phase locked loop (PLL) for near field communications (NFC) peer to peer (P2P) active communications |
US9287884B2 (en) * | 2013-02-21 | 2016-03-15 | Microchip Technology Incorporated | Enhanced numerical controlled oscillator |
US9438204B2 (en) * | 2013-08-27 | 2016-09-06 | Mediatek Inc. | Signal processing device and signal processing method |
JP2022098601A (en) * | 2020-12-22 | 2022-07-04 | ルネサスエレクトロニクス株式会社 | Phase synchronization circuit |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4030045A (en) | 1976-07-06 | 1977-06-14 | International Telephone And Telegraph Corporation | Digital double differential phase-locked loop |
US4031478A (en) * | 1976-06-29 | 1977-06-21 | International Telephone And Telegraph Corporation | Digital phase/frequency comparator |
US4095267A (en) | 1975-11-29 | 1978-06-13 | Tokyo Electric Co., Ltd. | Clock pulse control system for microcomputer systems |
US4456890A (en) * | 1982-04-05 | 1984-06-26 | Computer Peripherals Inc. | Data tracking clock recovery system using digitally controlled oscillator |
US4572995A (en) | 1983-08-26 | 1986-02-25 | Victor Company Of Japan, Ltd. | Synchronism discriminating circuit |
JPS61216524A (en) | 1985-03-22 | 1986-09-26 | Hitachi Ltd | Phase lock detecting circuit |
US4682343A (en) * | 1984-09-11 | 1987-07-21 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Processing circuit with asymmetry corrector and convolutional encoder for digital data |
EP0302562A1 (en) | 1987-07-29 | 1989-02-08 | Philips Composants | Frequency synthesizer having a tuning indicator device |
US4912730A (en) | 1988-10-03 | 1990-03-27 | Harris Corporation | High speed reception of encoded data utilizing dual phase resynchronizing clock recovery |
US4932041A (en) * | 1987-07-07 | 1990-06-05 | Bts Broadcast Television Systems Gmbh | Circuit for obtaining a bit-rate clock signal from a serial digital data signal |
EP0433120A1 (en) | 1989-11-16 | 1991-06-19 | Fujitsu Limited | PLL synthesizer circuit |
EP0716511A1 (en) | 1994-12-05 | 1996-06-12 | Motorola, Inc. | Method and apparatus for a frequency detection circuit for use in a phase locked loop |
US5552727A (en) | 1993-10-06 | 1996-09-03 | Mitsubishi Denki Kabushiki Kaisha | Digital phase locked loop circuit |
US5910741A (en) * | 1996-08-29 | 1999-06-08 | Nec Corporation | PLL circuit with non-volatile memory |
US6060953A (en) | 1998-04-08 | 2000-05-09 | Winbond Electronics Corporation | PLL response time accelerating system using a frequency detector counter |
US6154071A (en) | 1997-08-27 | 2000-11-28 | Nec Corporation | PLL circuit |
US6266799B1 (en) | 1997-10-02 | 2001-07-24 | Xaqti, Corporation | Multi-phase data/clock recovery circuitry and methods for implementing same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58111527A (en) * | 1981-12-25 | 1983-07-02 | Fujitsu Ltd | Frequency comparison circuit |
JPS6070827A (en) * | 1983-09-27 | 1985-04-22 | Fujitsu Ltd | Phase adjusting system |
-
1999
- 1999-04-30 FR FR9905627A patent/FR2793091B1/en not_active Expired - Fee Related
-
2000
- 2000-04-19 EP EP00401100A patent/EP1049285B1/en not_active Expired - Lifetime
- 2000-04-19 DE DE60031737T patent/DE60031737T2/en not_active Expired - Lifetime
- 2000-04-28 US US09/559,524 patent/US6701445B1/en not_active Ceased
- 2000-04-28 JP JP2000129903A patent/JP4628517B2/en not_active Expired - Fee Related
-
2006
- 2006-03-02 US US11/367,051 patent/USRE41031E1/en not_active Expired - Lifetime
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4095267A (en) | 1975-11-29 | 1978-06-13 | Tokyo Electric Co., Ltd. | Clock pulse control system for microcomputer systems |
US4031478A (en) * | 1976-06-29 | 1977-06-21 | International Telephone And Telegraph Corporation | Digital phase/frequency comparator |
US4030045A (en) | 1976-07-06 | 1977-06-14 | International Telephone And Telegraph Corporation | Digital double differential phase-locked loop |
US4456890A (en) * | 1982-04-05 | 1984-06-26 | Computer Peripherals Inc. | Data tracking clock recovery system using digitally controlled oscillator |
US4572995A (en) | 1983-08-26 | 1986-02-25 | Victor Company Of Japan, Ltd. | Synchronism discriminating circuit |
US4682343A (en) * | 1984-09-11 | 1987-07-21 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Processing circuit with asymmetry corrector and convolutional encoder for digital data |
JPS61216524A (en) | 1985-03-22 | 1986-09-26 | Hitachi Ltd | Phase lock detecting circuit |
US4932041A (en) * | 1987-07-07 | 1990-06-05 | Bts Broadcast Television Systems Gmbh | Circuit for obtaining a bit-rate clock signal from a serial digital data signal |
EP0302562A1 (en) | 1987-07-29 | 1989-02-08 | Philips Composants | Frequency synthesizer having a tuning indicator device |
US4912730A (en) | 1988-10-03 | 1990-03-27 | Harris Corporation | High speed reception of encoded data utilizing dual phase resynchronizing clock recovery |
EP0433120A1 (en) | 1989-11-16 | 1991-06-19 | Fujitsu Limited | PLL synthesizer circuit |
US5552727A (en) | 1993-10-06 | 1996-09-03 | Mitsubishi Denki Kabushiki Kaisha | Digital phase locked loop circuit |
EP0716511A1 (en) | 1994-12-05 | 1996-06-12 | Motorola, Inc. | Method and apparatus for a frequency detection circuit for use in a phase locked loop |
US5910741A (en) * | 1996-08-29 | 1999-06-08 | Nec Corporation | PLL circuit with non-volatile memory |
US6154071A (en) | 1997-08-27 | 2000-11-28 | Nec Corporation | PLL circuit |
US6266799B1 (en) | 1997-10-02 | 2001-07-24 | Xaqti, Corporation | Multi-phase data/clock recovery circuitry and methods for implementing same |
US6060953A (en) | 1998-04-08 | 2000-05-09 | Winbond Electronics Corporation | PLL response time accelerating system using a frequency detector counter |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070223638A1 (en) * | 2004-05-12 | 2007-09-27 | Thine Electronics, Inc. | Isophase Multiphase Clock Signal Generation Circuit and Serial Digital Data Receiving Circuit Using the Same |
US20080122514A1 (en) * | 2006-11-29 | 2008-05-29 | Konica Minolta Business Technologies, Inc. | Variable frequency clock output circuit and apparatus, motor driving apparatus, and image forming apparatus |
US7913102B2 (en) * | 2006-11-29 | 2011-03-22 | Konica Minolta Business Technologies, Inc. | Variable frequency clock output circuit and apparatus, motor driving apparatus, and image forming apparatus |
Also Published As
Publication number | Publication date |
---|---|
EP1049285B1 (en) | 2006-11-08 |
FR2793091B1 (en) | 2001-06-08 |
US6701445B1 (en) | 2004-03-02 |
JP2000341113A (en) | 2000-12-08 |
DE60031737T2 (en) | 2007-09-20 |
EP1049285A1 (en) | 2000-11-02 |
FR2793091A1 (en) | 2000-11-03 |
DE60031737D1 (en) | 2006-12-21 |
JP4628517B2 (en) | 2011-02-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE41031E1 (en) | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states | |
US9768949B2 (en) | Method of establishing an oscillator clock signal | |
US8155256B2 (en) | Method and apparatus for asynchronous clock retiming | |
JP2630343B2 (en) | Variable frequency clock generator | |
CN101803196B (en) | Jitter suppression circuit and jitter suppression method | |
US6937685B2 (en) | Apparatus and method for counting high-speed early/late pulses from a high speed phase detector using a pulse accumulator | |
US8891725B2 (en) | Frequency divider with improved linearity for a fractional-N synthesizer using a multi-modulus prescaler | |
CA2284842A1 (en) | Frequency synthesis circuit tuned by digital words | |
US7965143B2 (en) | Digital phase detector and phase-locked loop | |
AU7577891A (en) | Fractional-division synthesizer for a voice/data communications system | |
US6993108B1 (en) | Digital phase locked loop with programmable digital filter | |
CN104601171A (en) | Fractional divider and fractional frequency-division phase locked loop | |
US4763342A (en) | Digital phase-locked loop circuits with storage of clock error signal | |
JPH09233061A (en) | Bit synchronization circuit | |
CN110581708B (en) | Frequency-locked loop type full digital frequency synthesizer | |
CN107294531B (en) | Phase locked loop and frequency divider | |
US5050195A (en) | Narrow range digital clock circuit | |
US4415933A (en) | Carrier wave recovery circuit | |
JP3900679B2 (en) | Digital PLL circuit | |
CN107294529B (en) | Digital phase-locked loop for realizing infinite precision | |
KR101582171B1 (en) | Video Clock Synthesis Scheme of DisplayPort Receiver Using Direct Digital Frequency Synthesizer | |
JPH0795051A (en) | Digital pll circuit | |
Wang | New strategies for low noise, agile PLL frequency synthesis |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FRANCE TELECOM, FRANCE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MAJOS, JACQUES;REEL/FRAME:023076/0972 Effective date: 20000623 Owner name: FAHRENHEIT THERMOSCOPE LLC, NEVADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FRANCE TELECOM S.A.;REEL/FRAME:023076/0930 Effective date: 20041203 |
|
AS | Assignment |
Owner name: FAHRENHEIT THERMOSCOPE LLC, NEVADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FRANCE TELECOM S.A.;REEL/FRAME:023147/0747 Effective date: 20051128 |
|
AS | Assignment |
Owner name: FAHRENHEIT THERMOSCOPE LLC, NEVADA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED ON REEL 023147 FRAME 0747. ASSIGNOR(S) HEREBY CONFIRMS THE EXECUTION DATE OF 12/03/2004, AND NOTES THAT THIS ASSIGNMENT IS DUPLICATIVE OF THE ONE RECORDED AT REEL/FRAME 023076/0930;ASSIGNOR:FRANCE TELECOM S.A.;REEL/FRAME:026594/0594 Effective date: 20041203 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: ZARBANA DIGITAL FUND LLC, DELAWARE Free format text: MERGER;ASSIGNOR:FAHRENHEIT THERMOSCOPE LLC;REEL/FRAME:037338/0316 Effective date: 20150811 |