USB461752I5 - - Google Patents

Info

Publication number
USB461752I5
USB461752I5 US46175274A USB461752I5 US B461752 I5 USB461752 I5 US B461752I5 US 46175274 A US46175274 A US 46175274A US B461752 I5 USB461752 I5 US B461752I5
Authority
US
United States
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to US05/461,752 priority Critical patent/US4016541A/en
Publication of USB461752I5 publication Critical patent/USB461752I5/en
Application granted granted Critical
Publication of US4016541A publication Critical patent/US4016541A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
US05/461,752 1972-10-10 1974-04-17 Memory unit for connection to central processor unit and interconnecting bus Expired - Lifetime US4016541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US05/461,752 US4016541A (en) 1972-10-10 1974-04-17 Memory unit for connection to central processor unit and interconnecting bus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US29581072A 1972-10-10 1972-10-10
US05/461,752 US4016541A (en) 1972-10-10 1974-04-17 Memory unit for connection to central processor unit and interconnecting bus

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US29581072A Continuation 1972-10-10 1972-10-10

Publications (2)

Publication Number Publication Date
USB461752I5 true USB461752I5 (es) 1976-04-20
US4016541A US4016541A (en) 1977-04-05

Family

ID=26969343

Family Applications (1)

Application Number Title Priority Date Filing Date
US05/461,752 Expired - Lifetime US4016541A (en) 1972-10-10 1974-04-17 Memory unit for connection to central processor unit and interconnecting bus

Country Status (1)

Country Link
US (1) US4016541A (es)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4257099A (en) * 1975-10-14 1981-03-17 Texas Instruments Incorporated Communication bus coupler
US4137565A (en) * 1977-01-10 1979-01-30 Xerox Corporation Direct memory access module for a controller
US4126893A (en) * 1977-02-17 1978-11-21 Xerox Corporation Interrupt request controller for data processing system
US4122520A (en) * 1977-05-23 1978-10-24 General Electric Company Microcomputer controller and direct memory access apparatus therefor
US4149238A (en) * 1977-08-30 1979-04-10 Control Data Corporation Computer interface
US4161024A (en) * 1977-12-22 1979-07-10 Honeywell Information Systems Inc. Private cache-to-CPU interface in a bus oriented data processing system
US4169284A (en) * 1978-03-07 1979-09-25 International Business Machines Corporation Cache control for concurrent access
US4589089A (en) * 1978-05-30 1986-05-13 Bally Manufacturing Corporation Computer-peripheral interface for a game apparatus
US4220990A (en) * 1978-09-25 1980-09-02 Bell Telephone Laboratories, Incorporated Peripheral processor multifunction timer for data processing systems
US4263649A (en) * 1979-01-05 1981-04-21 Mohawk Data Sciences Corp. Computer system with two busses
US4300194A (en) * 1979-01-31 1981-11-10 Honeywell Information Systems Inc. Data processing system having multiple common buses
US4245307A (en) * 1979-09-14 1981-01-13 Formation, Inc. Controller for data processing system
US4319338A (en) * 1979-12-12 1982-03-09 Allen-Bradley Company Industrial communications network with mastership determined by need
US4323967A (en) * 1980-04-15 1982-04-06 Honeywell Information Systems Inc. Local bus interface for controlling information transfers between units in a central subsystem
JPS5856277A (ja) * 1981-09-29 1983-04-02 Toshiba Corp 情報処理装置ならびに方法
US4649475A (en) * 1984-04-02 1987-03-10 Sperry Corporation Multiple port memory with port decode error detector
US4633434A (en) * 1984-04-02 1986-12-30 Sperry Corporation High performance storage unit
US4627030A (en) * 1985-02-04 1986-12-02 At&T Bell Laboratories Dual port memory word size expansion technique
US4858112A (en) * 1985-12-17 1989-08-15 General Electric Company Interface comprising message and protocol processors for interfacing digital data with a bus network
US4933836A (en) * 1986-10-29 1990-06-12 United Technologies Corporation n-Dimensional modular multiprocessor lattice architecture
US5434979A (en) * 1987-02-27 1995-07-18 Unisys Corporation Disk drive controller
US5125084A (en) * 1988-05-26 1992-06-23 Ibm Corporation Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller
US5327545A (en) * 1988-05-26 1994-07-05 International Business Machines Corporation Data processing apparatus for selectively posting write cycles using the 82385 cache controller
US5045998A (en) * 1988-05-26 1991-09-03 International Business Machines Corporation Method and apparatus for selectively posting write cycles using the 82385 cache controller
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
US5193193A (en) * 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
US5303362A (en) * 1991-03-20 1994-04-12 Digital Equipment Corporation Coupled memory multiprocessor computer system including cache coherency management protocols
KR960001273B1 (ko) * 1991-04-30 1996-01-25 가부시키가이샤 도시바 단일칩 마이크로컴퓨터
JPH0784918A (ja) * 1993-09-17 1995-03-31 Fujitsu Ltd データ入替回路
US6347350B1 (en) 1998-12-22 2002-02-12 Intel Corporation Driving the last inbound signal on a line in a bus with a termination
US6738844B2 (en) * 1998-12-23 2004-05-18 Intel Corporation Implementing termination with a default signal on a bus line
JP3963417B2 (ja) * 1999-11-19 2007-08-22 株式会社東芝 データ同期処理のための通信方法および電子機器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810114A (en) * 1971-12-29 1974-05-07 Tokyo Shibaura Electric Co Data processing system
US3828325A (en) * 1973-02-05 1974-08-06 Honeywell Inf Systems Universal interface system using a controller to adapt to any connecting peripheral device
US3845425A (en) * 1973-06-15 1974-10-29 Gte Automatic Electric Lab Inc Method and apparatus for providing conditional and unconditional access to protected memory storage locations

Also Published As

Publication number Publication date
US4016541A (en) 1977-04-05

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