US9912311B2 - Multimode reconfigurable amplifier and analog filter including the same - Google Patents

Multimode reconfigurable amplifier and analog filter including the same Download PDF

Info

Publication number
US9912311B2
US9912311B2 US15/164,389 US201615164389A US9912311B2 US 9912311 B2 US9912311 B2 US 9912311B2 US 201615164389 A US201615164389 A US 201615164389A US 9912311 B2 US9912311 B2 US 9912311B2
Authority
US
United States
Prior art keywords
amplifier
mode
feed forward
reconfigurable
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US15/164,389
Other versions
US20170026030A1 (en
Inventor
So-Young Kang
Thomas Byung-Hak CHO
Hee-Seon Shin
Su-Seob AHN
Jong-Mi Lee
Min-Gyu JO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020150135531A external-priority patent/KR102476218B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIN, HEE-SEON, CHO, THOMAS BYUNG-HAK, Ahn, Su-Seob, JO, MIN-GYU, KANG, SO-YOUNG, LEE, JONG-MI
Publication of US20170026030A1 publication Critical patent/US20170026030A1/en
Application granted granted Critical
Publication of US9912311B2 publication Critical patent/US9912311B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
    • H03F3/45641—Measuring at the loading circuit of the differential amplifier
    • H03F3/45659—Controlling the loading circuit of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/001—Digital control of analog signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G5/00—Tone control or bandwidth control in amplifiers
    • H03G5/16—Automatic control
    • H03G5/24—Automatic control in frequency-selective amplifiers
    • H03G5/28—Automatic control in frequency-selective amplifiers having semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/153—Feedback used to stabilise the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45264—Indexing scheme relating to differential amplifiers the dif amp comprising frequency or phase stabilisation means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45522—Indexing scheme relating to differential amplifiers the FBC comprising one or more potentiometers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45526—Indexing scheme relating to differential amplifiers the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45591—Indexing scheme relating to differential amplifiers the IC comprising one or more potentiometers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/1217—Frequency selective two-port networks using amplifiers with feedback using a plurality of operational amplifiers
    • H03H11/1252—Two integrator-loop-filters
    • H03H11/1256—Tow-Thomas biquad
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/126—Frequency selective two-port networks using amplifiers with feedback using a single operational amplifier

Definitions

  • the present disclosure relates generally to a multimode reconfigurable amplifier and an analog filter including the same, and more particularly, to a multimode reconfigurable amplifier which changes a compensation method according to a bandwidth of a supported band of an operating mode and an analog filter including the same.
  • An aspect of the present disclosure provides a reconfigurable amplifier having improved operational performance and stability by applying a different compensation method according to a bandwidth of a supported band of an operating mode.
  • Another aspect of the present disclosure provides an analog filter which can stably filter operations in various frequency bands without a reduction in performance.
  • the reconfigurable amplifier includes a gain circuit comprising a gain path configured to amplify an input signal, and a feed forward circuit including a feed forward path configured to receive the input signal and perform feed forward compensation on the input signal, and a first control circuit configured to perform the feed forward compensation in a first mode by activating the feed forward path, and deactivating the feed forward path in a second mode different from the first mode.
  • a reconfigurable amplifier includes a gain circuit including a first amplifier configured to amplify an input signal and a second amplifier configured to amplify an output of the first amplifier, a feed forward circuit connected to an input terminal of the first amplifier and an output terminal of the second amplifier and configured to perform feed forward compensation, a common feedback amplifier, and a control circuit configured to control the gain circuit to have a first capacitance configuration in a first mode and control the gain circuit to have a second capacitance configuration, which is different from the first capacitance configuration, in a second mode different from the first mode.
  • a reconfigurable amplifier includes a gain circuit including a first amplifier configured to amplify an input signal and a second amplifier configured to amplify an output of the first amplifier, and a feed forward circuit and a control circuit connected to an input terminal of the first amplifier and an output terminal of the second amplifier and configured to perform feed forward compensation, wherein the control circuit is further configured to perform feed forward compensation in a first mode using m first transistors and perform feed forward compensation in a second mode different from the first mode using n first transistors, wherein m is an integer greater than or equal to one, and n is an integer of greater than or equal to zero and less than m.
  • an analog filter includes a reconfigurable amplifier having an input terminal configured to receive an input signal; and a variable resistor connected to the input terminal, wherein the reconfigurable amplifier is configured to operate as a feed forward compensation amplifier when the variable resistor has a first resistance value and operate as a Miller compensation amplifier when the variable resistor has a second resistance value different from the first resistance value.
  • FIG. 1 is a circuit diagram of an analog filter
  • FIG. 2 is a circuit diagram of an amplifier of FIG. 1 ;
  • FIG. 3 is a diagram illustrating frequency characteristics of the amplifier of FIG. 2 ;
  • FIG. 4 is a circuit diagram of the amplifier of FIG. 1 ;
  • FIG. 5 is a diagram illustrating frequency characteristics of the amplifier of FIG. 2 and the amplifier of FIG. 4 ;
  • FIG. 6 is a circuit diagram of an analog filter according to an embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram of a reconfigurable amplifier of FIG. 6 ;
  • FIG. 8 is a circuit diagram of compensation control circuits of FIG. 7 ;
  • FIG. 9 is a circuit diagram of a feed forward control circuit of FIG. 7 ;
  • FIGS. 10 through 12 are diagrams illustrating the operation of the reconfigurable amplifier of FIG. 7 in a wideband mode
  • FIG. 13 is a diagram illustrating frequency characteristics of the reconfigurable amplifier of FIG. 7 operating in the wideband mode
  • FIGS. 14 through 17 are diagrams illustrating the operation of the reconfigurable amplifier of FIG. 7 in a middleband mode
  • FIGS. 18 and 19 are diagrams illustrating the operation of the reconfigurable amplifier of FIG. 7 in a narrowband mode.
  • FIG. 20 is a circuit diagram of an analog filter according to an embodiment of the present disclosure.
  • FIG. 1 is a circuit diagram of an analog filter 99 .
  • the analog filter 99 may include an amplifier 900 which receives input signals INn and INp through input resistors RG 1 and feedback resistors RM and feedback capacitors CM which are connected in parallel to an input terminal and an output terminal of the amplifier 900 , respectively.
  • the input signals INn and INp provided to the amplifier 900 may be amplified and then output as output signals OUTn and OUTp, respectively.
  • the input signals INn and INp may be, but are not limited to, differential signals.
  • Each of the input resistors RG 1 and the feedback resistors RM may include, for example, a variable resistor.
  • a gain and cutoff frequency of the analog filter 99 can be changed by varying resistance levels of the input resistors RG 1 and the feedback resistors RM.
  • the cutoff frequency of the analog filter 99 may be inversely proportional to the resistance levels of the feedback resistors RM.
  • the analog filter 99 may operate as a narrowband filter that passes an input signal having a low frequency.
  • the analog filter 99 may operate as a wideband filter that passes an input signal having a high frequency.
  • the analog filter 99 may operate as a middleband or bandpass filter that passes an input signal having a frequency between a first frequency and a second frequency.
  • the feedback resistors RM and the feedback capacitors CM may be controlled by, e.g., a digital code to increase or decrease linearly or exponentially.
  • the analog filter 99 may include a passive device, which includes the input resistors RG 1 , the feedback resistors RM and the feedback capacitors CM, and the amplifier 900 .
  • the performance of the analog filter 99 may be greatly affected by the amplifier 900 .
  • the amplifier 900 may be a two-stage amplifier that obtains a desired gain using two amplifiers.
  • the two-stage amplifier is described below in greater detail with reference to FIGS. 2 and 3 .
  • FIG. 2 is a circuit diagram of the amplifier 900 of FIG. 1 .
  • FIG. 3 is a diagram illustrating frequency characteristics of an amplifier 900 a of FIG. 2 .
  • FIGS. 2 and 3 are diagrams illustrating the equivalent circuit diagram and frequency characteristics of the amplifier 900 of FIG. 1 if the amplifier 900 is configured as the two-stage amplifier 900 a.
  • the two-stage amplifier 900 a may include a first amplifier 902 a which amplifies an input signal and a second amplifier 904 a which amplifies an output of the first amplifier 902 a.
  • the two-stage amplifier 900 a may have two poles in its frequency characteristics.
  • the two poles may reduce the phase of the two-stage amplifier 900 a , thus making the operation of the two-stage amplifier 900 a unstable.
  • a two-stage amplifier employing a Miller compensation method may be used.
  • a two-stage amplifier employing the Miller compensation method is described below in greater detail with reference to FIGS. 4 and 5 .
  • FIG. 4 is a circuit diagram of the amplifier 900 of FIG. 1 .
  • FIG. 5 is a diagram illustrating frequency characteristics of the amplifier 900 a of FIG. 2 and an amplifier 900 b of FIG. 4 .
  • FIGS. 4 and 5 are a circuit diagram and a diagram illustrating frequency characteristics of the amplifier 900 of FIG. 1 configured as the Miller compensation two-stage amplifier 900 b.
  • the Miller compensation two-stage amplifier 900 b may include a first amplifier 902 b which amplifies an input signal and a second amplifier 904 b which amplifies an output of the first amplifier 902 b .
  • a Miller capacitor Cc for Miller compensation may be disposed between an input terminal and an output terminal of the second amplifier 904 b.
  • a frequency characteristic curve ⁇ circle around ( 2 ) ⁇ of the Miller compensation two-stage amplifier 900 b is different from a frequency characteristic curve ⁇ circle around ( 1 ) ⁇ of the two-stage amplifier 900 a (see FIG. 2 ) not employing the Miller compensation method.
  • the Miller compensation two-stage amplifier 900 b two poles are split by the Miller capacitor Cc. That is, a first pole is moved to a low frequency band, and a second pole is moved to a high frequency band. Accordingly, the phase of the amplifier 900 of FIG. 1 configured as the Miller compensation two-stage amplifier 900 b increases, thereby improving the operational stability of the amplifier 900 .
  • FIG. 6 is a circuit diagram of an analog filter 1 according to an embodiment of the present disclosure.
  • the analog filter 1 may include a reconfigurable amplifier 100 which receives input signals INn and INp through input resistors RG 1 and feedback resistors RM and feedback capacitors CM which are connected in parallel to an input terminal and an output terminal of the reconfigurable amplifier 100 , respectively.
  • the input signals INn and INp provided to the reconfigurable amplifier 100 may be amplified differently according to an operating mode of the reconfigurable amplifier 100 and then output as output signals OUTn and OUTp, respectively.
  • the input signals INn and INp may be, but are not limited to, differential signals.
  • Each of the input resistors RG 1 and the feedback resistors RM may include, for example, a variable resistor.
  • a gain and cutoff frequency of the analog filter 1 may be changed by varying resistance levels of the input resistors RG 1 and the feedback resistors RM.
  • the cutoff frequency of the analog filter 1 may be inversely proportional to the resistance levels of the feedback resistors RM.
  • the analog filter 1 may operate as a narrowband filter that passes an input signal having a low frequency.
  • the reconfigurable amplifier 100 may operate in a narrowband mode.
  • the analog filter 1 may operate as a wideband filter that passes an input signal having a high frequency.
  • the reconfigurable amplifier 100 may operate in a wideband mode.
  • the analog filter 1 may operate as a middleband or bandpass filter that passes an input signal having a frequency between a first frequency and a second frequency.
  • the reconfigurable amplifier 100 may operate in a middleband mode.
  • the feedback resistors RM and the feedback capacitors CM may be controlled by, e.g., a digital code to increase or decrease linearly or exponentially.
  • FIG. 7 is a circuit diagram of the reconfigurable amplifier 100 of FIG. 6 .
  • FIG. 8 is a circuit diagram of a (compensation control circuits) 114 of FIG. 7 .
  • FIG. 9 is a circuit diagram of a feed forward control circuit 124 illustrated in FIG. 7 .
  • the reconfigurable amplifier 100 may include a gain circuit 110 and a feed forward circuit 120 .
  • the gain circuit 110 may include a first amplifier AP 1 which amplifies input signals INn and INp and a second amplifier AP 2 which amplifies outputs of the first amplifier AP 1 . That is, the gain circuit 110 according to the current embodiment may include a two-stage amplifier.
  • each of the first amplifier AP 1 and the second amplifier AP 2 may include a transistor pair.
  • the first amplifier AP 1 and the second amplifier AP 2 may form a gain path which amplifies the input signals INn and INp and outputs the amplified signals INn and INp as output signals OUTn and OUTp, respectively.
  • the gain circuit 110 may include the gate control circuit 114 .
  • the gain control circuit 114 may control a gain path to have a different capacitance configuration according to the operating mode of the reconfigurable amplifier 100 .
  • the gain control circuit 114 may control the capacitance configuration of the gain path when the reconfigurable amplifier 100 operates in the wideband mode to be different from the capacitance configuration of the gain path when the reconfigurable amplifier 100 operates in the middleband mode.
  • the gain control circuit 114 may control the reconfigurable amplifier 100 to operate as a Miller compensation amplifier. This is described in greater detail below.
  • the gain control circuit 114 may include first through third switches SW 1 through SW 3 and a control capacitor CP and nulling R (one of the Miller compensation parameters).
  • the first switch SW 1 may connect a first terminal of the control capacitor CP between the first amplifier AP 1 and the second amplifier AP 2 . Specifically, when the first switch SW 1 is turned on (e.g. closed), the first terminal of the control capacitor CP may be connected between the first amplifier AP 1 and the second amplifier AP 2 . When the first switch SW 1 is turned off (e.g. open), the first terminal of the control capacitor CP may not be connected between the first amplifier AP 1 and the second amplifier AP 2 .
  • the second switch SW 2 may connect a second terminal of the control capacitor CP to an output terminal of the second amplifier AP 2 . Specifically, when the second switch SW 2 is turned on, the second terminal of the control capacitor CP may be connected to the output terminal of the second amplifier AP 2 . When the second switch SW 2 is turned off, the second terminal of the control capacitor CP may not be connected to the output terminal of the second amplifier AP 2 .
  • the third switch SW 3 may connect the second terminal of the control capacitor CP between the first amplifier AP 1 and the second amplifier AP 2 . Specifically, when the third switch SW 3 is turned on, the second terminal of the control capacitor CP may be connected between the first amplifier AP 1 and the second amplifier AP 2 . When the third switch SW 3 is turned off, the second terminal of the control capacitor CP may not be connected between the first amplifier AP 1 and the second amplifier AP 2 .
  • the first through third switches SW 1 through SW 3 may be controlled as shown in Table 1 below.
  • the control capacitor CP may not be connected to the gain path.
  • control capacitor CP may be connected between the first amplifier AP 1 and the second amplifier AP 2 of the gain path.
  • control capacitor CP may be connected between an input terminal and the output terminal of the second amplifier AP 2 of the gain path and serve as a Miller capacitor.
  • the feed forward circuit 120 may include a feed forward path, which receives the input signals INn and INp and performs feed forward compensation on the input signals INn and INp, and the feed forward control circuit 124 .
  • the feed forward control circuit 124 may include a first transistor T 1 which is gated by a voltage of a first node VP of the feed forward path, a fourth transistor T 4 which is gated by a voltage of a second node VN of the feed forward path, and second and third transistors T 2 and T 3 which are gated by a voltage of a common mode node CM (or a common feedback loop such as a negative feedback loop of FIG. 14 described below).
  • Each of the first through fourth transistors T 1 through T 4 may include a plurality of transistors. In an embodiment of the present disclosure, each of the first through fourth transistors T 1 through T 4 may consist of a plurality of transistors, but the present disclosure is not limited thereto.
  • the first transistor T 1 gated by the voltage of the first node VP of the feed forward path and the fourth transistor T 4 gated by the voltage of the second node VN of the feed forward path may perform feed forward compensation, and the second and third transistors T 2 and T 3 gated by the voltage of the common mode node CM may function as a common feedback amplifier (CFA).
  • the first and fourth transistors T 1 and T 4 may be connected between an input terminal of the first amplifier AP 1 and the output terminal of the second amplifier AP 2 as illustrated in FIG. 7 to perform feed forward compensation, and the second and third transistors T 2 and T 3 may function as the CFA as illustrated in FIG. 7 .
  • the first transistor T 1 included in the feed forward control circuit 124 may consist of four transistors T 11 through T 14
  • the fourth transistor T 4 included in the feed forward control circuit 124 may consist of four transistors T 41 through T 44 .
  • the second transistor T 2 included in the feed forward control circuit 124 may consist of four transistors T 21 through T 24
  • the third transistor T 3 included in the feed forward control circuit 124 may consist of four transistors T 31 through T 34 .
  • each of the first through fourth transistors T 1 through T 4 included in the feed forward control circuit 124 consists of four transistors in FIG. 9 , the present disclosure is not limited thereto. The number of transistors that constitute each of the first through fourth transistors T 1 through T 4 included in the feed forward control circuit 124 may be changed.
  • Switches S 1 through S 8 may be disposed at respective terminals (e.g., drain terminals) of the transistors T 11 through T 14 , T 21 through T 24 , T 31 through T 34 , and T 41 through T 44 .
  • Each of the switches S 1 through S 8 may be controlled as shown in Table 2 below according to the operating mode of the reconfigurable amplifier 100 .
  • the feed forward control circuit 124 may adjust the number of transistors that operate as the CFA of the reconfigurable amplifier 100 by operating as described above. Further, the feed forward control circuit 124 may deactivate the feed forward path of the reconfigurable amplifier 100 .
  • the feed forward control circuit 124 activates the feed forward path of the reconfigurable amplifier 100 such that feed forward compensation can be performed.
  • the feed forward control circuit 124 deactivates the feed forward path of the reconfigurable amplifier 100 such that feed forward compensation is not performed in the reconfigurable amplifier 100 .
  • the feed forward control circuit 124 may also control a relatively large number of transistors to operate as the CFA when the reconfigurable amplifier 100 operates in the wideband mode and control a relatively small number of transistors to operate as the CFA when the reconfigurable amplifier 100 operates in the middleband mode.
  • the feedback forward control circuit 124 may change the number of transistors that operate as the CFA as desired when the reconfigurable amplifier 100 operates in the middleband mode.
  • the number of transistors that are turned on may always be the same regardless of the operating mode of the reconfigurable amplifier 100 .
  • eight transistors may always be turned on regardless of the operating mode of the reconfigurable amplifier 100 .
  • FIGS. 10 through 12 are diagrams illustrating the operation of the reconfigurable amplifier 100 of FIG. 7 in the wideband mode.
  • FIG. 10 is a circuit diagram of the reconfigurable amplifier 100 operating in the wideband mode.
  • FIG. 11 is a diagram illustrating the operation of the feed forward control circuit 124 when the reconfigurable amplifier 100 operates in the wideband mode.
  • FIG. 12 is a circuit diagram of the reconfigurable amplifier 100 operating in the wideband mode.
  • the reconfigurable amplifier 100 when the reconfigurable amplifier 100 operates in the wideband mode (e.g., when the analog filter 1 of FIG. 6 operates as a wideband filter that passes an input signal having a frequency of 10 MHz or more), all of the first through third switches SW 1 through SW 3 of the gain control circuit 114 are turned off.
  • control capacitor CP is not connected to the gain path of the reconfigurable amplifier 100 . Therefore, the gain path of the reconfigurable amplifier 100 does not include the control capacitor CP as illustrated in FIG. 10 .
  • the switches S 1 through S 8 of the feed forward control circuit 124 are controlled as illustrated in FIG. 11 .
  • the feed forward path of the reconfigurable amplifier 100 is activated to perform feed forward compensation.
  • three activated transistor pairs T 11 through T 13 and T 41 through T 43 in the feed forward path of the reconfigurable amplifier 100 operate as a feed forward compensation amplifier illustrated in FIG. 12 .
  • FIG. 13 is a diagram illustrating frequency characteristics of the reconfigurable amplifier 100 of FIG. 7 operating in the wideband mode.
  • a frequency characteristic curve ⁇ circle around ( 1 ) ⁇ of the two-stage amplifier 900 a (see FIG. 2 ) without employing the Miller compensation method and a frequency characteristic curve ⁇ circle around ( 2 ) ⁇ of the Miller compensation two-stage amplifier 900 b (see FIG. 4 ) are compared with a frequency characteristic curve ⁇ circle around ( 3 ) ⁇ of the reconfigurable amplifier 100 according to an embodiment of the present disclosure.
  • the reconfigurable amplifier 100 has a considerably improved gain of a high frequency band, because it performs feed forward compensation in the wideband mode as described above.
  • the reconfigurable amplifier 100 has better phase characteristics than the two-stage amplifier 900 a without employing the Miller compensation method.
  • FIGS. 14 through 17 are diagrams illustrating the operation of the reconfigurable amplifier 100 of FIG. 7 in the middleband mode.
  • FIG. 14 illustrates a circuit diagram of the reconfigurable amplifier 100 operating in the wideband mode from a common mode perspective.
  • the resistance levels of the feedback resistors RM of the analog filter 1 are generally low. Therefore, a gain of a positive feedback loop illustrated in FIG. 14 is always lower than that of a negative feedback loop.
  • the reconfigurable amplifier 100 when the reconfigurable amplifier 100 operates in the middleband mode, the resistance levels of the feedback resistors RM of the analog filter 1 increase. Therefore, if the above-described feed forward compensation is performed without any adjustment, the gain of the positive feedback loop may become higher than that of the negative feedback loop.
  • the operation of the reconfigurable amplifier 100 may become unstable. Therefore, when the reconfigurable amplifier 100 operates in the middleband mode, the gain of the negative feedback loop must be reinforced as compared to when the reconfigurable amplifier 100 operates in the wideband mode.
  • the feed forward control circuit 124 may be adjusted to improve a common mode rejection function for reinforcing the gain of the negative feedback loop. This is described in greater detail below with reference to FIGS. 15 through 17 .
  • FIG. 15 is a circuit diagram of the reconfigurable amplifier 100 operating in the middleband mode.
  • FIGS. 16 and 17 are diagrams illustrating the operation of the feed forward control circuit 124 when the reconfigurable amplifier 100 operates in the middleband mode.
  • the reconfigurable amplifier 100 when the reconfigurable amplifier 100 operates in the middleband mode (e.g., when the analog filter 1 of FIG. 6 operates as a middleband filter that passes an input signal having a frequency of 2 to 10 MHz), the first and third switches SW 1 and SW 3 of the gain control circuit 114 are turned on, and the second switch SW 2 is turned off.
  • the middleband mode e.g., when the analog filter 1 of FIG. 6 operates as a middleband filter that passes an input signal having a frequency of 2 to 10 MHz
  • the first and third switches SW 1 and SW 3 of the gain control circuit 114 are turned on, and the second switch SW 2 is turned off.
  • control capacitor CP may be connected between the first amplifier AP 1 and the second amplifier AP 2 of the gain path as illustrated in FIGS. 15 and 18 .
  • the switches S 1 through S 8 of the feed forward control circuit 124 may be controlled as illustrated in FIG. 16 .
  • the feed forward path of the reconfigurable amplifier 100 may be activated, and two activated transistor pairs T 11 and T 12 and T 41 and T 42 in the feed forward path of the reconfigurable amplifier 100 may perform feed forward compensation.
  • two transistor pairs T 23 and T 24 and T 33 and T 34 are placed in the common feedback loop. Therefore, the common mode rejection function for reinforcing the gain of the negative feedback loop can be improved as compared to when the reconfigurable amplifier 100 operates in the wideband mode as illustrated in FIG. 11 .
  • the switches S 1 through S 8 of the feed forward control circuit 124 may be controlled as illustrated in FIG. 17 .
  • the feed forward path of the reconfigurable amplifier 100 may be activated to perform feed forward compensation.
  • one activated transistor pair T 11 and T 41 in the feed forward path of the reconfigurable amplifier 100 may operate as the CFA illustrated in FIG. 15 .
  • three transistor pairs T 22 through T 24 and T 32 through T 34 are placed in the common feedback loop. Therefore, the common mode rejection function for reinforcing the gain of the negative feedback loop can be improved further.
  • FIGS. 18 and 19 are diagrams illustrating the operation of the reconfigurable amplifier 100 of FIG. 7 in the narrowband mode.
  • FIG. 18 is a circuit diagram of the reconfigurable amplifier 100 operating in the narrowband mode.
  • FIG. 19 is a diagram illustrating the operation of the feed forward control circuit 124 when the reconfigurable amplifier 100 operates in the narrowband mode.
  • the reconfigurable amplifier 100 when the reconfigurable amplifier 100 operates in the narrowband mode (e.g., when the analog filter 1 of FIG. 6 operates as a narrowband filter that passes an input signal having a frequency of 2 MHz), the first and second switches SW 1 and SW 2 of the gain control circuit 114 are turned on, and the third switch SW 3 is turned off.
  • the narrowband mode e.g., when the analog filter 1 of FIG. 6 operates as a narrowband filter that passes an input signal having a frequency of 2 MHz
  • the first and second switches SW 1 and SW 2 of the gain control circuit 114 are turned on, and the third switch SW 3 is turned off.
  • control capacitor CP may be connected between the input terminal and the output terminal of the second amplifier AP 2 of the gain path as illustrated in FIG. 19 . That is, the control capacitor CP may serve as the Miller capacitor Cc illustrated in FIG. 4 . Accordingly, the reconfigurable amplifier 100 may perform Miller compensation.
  • the switches S 1 through S 8 of the feed forward control circuit 124 may be controlled as illustrated in FIG. 19 .
  • the feed forward path of the reconfigurable amplifier 100 may be deactivated to not perform feed forward compensation.
  • the reconfigurable amplifier 100 can apply a different compensation method according to its operating mode, the operational performance and stability of the reconfigurable amplifier 100 can be improved.
  • a feed forward compensation method is applied when the reconfigurable amplifier 100 operates in the wideband mode. Therefore, gain characteristics of the reconfigurable amplifier 100 can be improved.
  • the gain of the positive feedback loop and the gain of the negative feedback loop are adaptively adjusted according to the cutoff frequency of the analog filter 1 . Therefore, the operational stability of the reconfigurable amplifier 100 can be improved.
  • FIG. 20 is a circuit diagram of an analog filter 2 according to an embodiment of the present disclosure. The embodiments of the present disclosure are described, focusing mainly on differences between other embodiments of the present disclosure.
  • the analog filter 2 may include additional reconfigurable amplifiers as compared with the analog filter 1 (see FIG. 6 ) described above.
  • the analog filter 2 may be a two-stage filter including a first reconfigurable amplifier 200 a and a second reconfigurable amplifier 200 b.
  • Each of the first and second reconfigurable amplifiers 200 a and 200 b may employ substantially the same configuration as the reconfigurable amplifier 100 (see FIG. 6 ) described above.
  • Each of input resistors RG 1 and feedback resistors RM and RMQ may include, for example, a variable resistor.
  • a gain and cutoff frequency of the analog filter 2 may be changed by varying resistance levels of the input resistors RG 1 and the feedback resistors RM and RMQ.
  • the feedback resistors RM and RMQ and feedback capacitors CM may be controlled by, e.g., a digital code to increase or decrease linearly or exponentially.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

Provided is a reconfigurable amplifier. The reconfigurable amplifier includes a gain circuit including a gain path configured to amplify an input signal, and a feed forward circuit including a feed forward path configured to receive the input signal and perform feed forward compensation on the input signal, and a first control circuit configured to perform the feed forward compensation in a first mode by activating the feed forward path, and deactivate the feed forward path in a second mode different from the first mode.

Description

PRIORITY
This application claims priority under 35 U.S.C. § 119(a) to a Korean Patent Application filed on Jul. 22, 2015 in the Korean Intellectual Property Office and assigned Serial No. 10-2015-0103861, a Korean Patent Application filed on Jul. 29, 2015 in the Korean Intellectual Property Office and assigned Serial No. 10-2015-0107229, and a Korean Patent Application filed on Sep. 24, 2015 in the Korean Intellectual Property Office and assigned Serial No. 10-2015-0135531, the entire contents of each of which are incorporated herein by reference.
BACKGROUND
1. Technical Field
The present disclosure relates generally to a multimode reconfigurable amplifier and an analog filter including the same, and more particularly, to a multimode reconfigurable amplifier which changes a compensation method according to a bandwidth of a supported band of an operating mode and an analog filter including the same.
2. Description of the Related Art
The development of wireless communication systems is increasing the need to rapidly process signals in various frequency bands. In line with this trend, there is a growing demand for the development of a reconfigurable broadband multi-communication terminal system that is efficiently compatible with frequency bands used in conventional communication systems and can satisfy next-generation wireless communication standards.
SUMMARY
An aspect of the present disclosure provides a reconfigurable amplifier having improved operational performance and stability by applying a different compensation method according to a bandwidth of a supported band of an operating mode.
Another aspect of the present disclosure provides an analog filter which can stably filter operations in various frequency bands without a reduction in performance.
According to an aspect of the present disclosure, there is provided a reconfigurable amplifier. The reconfigurable amplifier includes a gain circuit comprising a gain path configured to amplify an input signal, and a feed forward circuit including a feed forward path configured to receive the input signal and perform feed forward compensation on the input signal, and a first control circuit configured to perform the feed forward compensation in a first mode by activating the feed forward path, and deactivating the feed forward path in a second mode different from the first mode.
According to another aspect of the present disclosure, there is provided a reconfigurable amplifier. The reconfigurable amplifier includes a gain circuit including a first amplifier configured to amplify an input signal and a second amplifier configured to amplify an output of the first amplifier, a feed forward circuit connected to an input terminal of the first amplifier and an output terminal of the second amplifier and configured to perform feed forward compensation, a common feedback amplifier, and a control circuit configured to control the gain circuit to have a first capacitance configuration in a first mode and control the gain circuit to have a second capacitance configuration, which is different from the first capacitance configuration, in a second mode different from the first mode.
According to another aspect of the present disclosure, there is provided a reconfigurable amplifier. The reconfigurable amplifier includes a gain circuit including a first amplifier configured to amplify an input signal and a second amplifier configured to amplify an output of the first amplifier, and a feed forward circuit and a control circuit connected to an input terminal of the first amplifier and an output terminal of the second amplifier and configured to perform feed forward compensation, wherein the control circuit is further configured to perform feed forward compensation in a first mode using m first transistors and perform feed forward compensation in a second mode different from the first mode using n first transistors, wherein m is an integer greater than or equal to one, and n is an integer of greater than or equal to zero and less than m.
According to another aspect of the present disclosure, there is provided an analog filter. The analog filter includes a reconfigurable amplifier having an input terminal configured to receive an input signal; and a variable resistor connected to the input terminal, wherein the reconfigurable amplifier is configured to operate as a feed forward compensation amplifier when the variable resistor has a first resistance value and operate as a Miller compensation amplifier when the variable resistor has a second resistance value different from the first resistance value.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other aspects, features, and advantages of the present disclosure will become more apparent from the following description, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a circuit diagram of an analog filter;
FIG. 2 is a circuit diagram of an amplifier of FIG. 1;
FIG. 3 is a diagram illustrating frequency characteristics of the amplifier of FIG. 2;
FIG. 4 is a circuit diagram of the amplifier of FIG. 1;
FIG. 5 is a diagram illustrating frequency characteristics of the amplifier of FIG. 2 and the amplifier of FIG. 4;
FIG. 6 is a circuit diagram of an analog filter according to an embodiment of the present disclosure;
FIG. 7 is a circuit diagram of a reconfigurable amplifier of FIG. 6;
FIG. 8 is a circuit diagram of compensation control circuits of FIG. 7;
FIG. 9 is a circuit diagram of a feed forward control circuit of FIG. 7;
FIGS. 10 through 12 are diagrams illustrating the operation of the reconfigurable amplifier of FIG. 7 in a wideband mode;
FIG. 13 is a diagram illustrating frequency characteristics of the reconfigurable amplifier of FIG. 7 operating in the wideband mode;
FIGS. 14 through 17 are diagrams illustrating the operation of the reconfigurable amplifier of FIG. 7 in a middleband mode;
FIGS. 18 and 19 are diagrams illustrating the operation of the reconfigurable amplifier of FIG. 7 in a narrowband mode; and
FIG. 20 is a circuit diagram of an analog filter according to an embodiment of the present disclosure.
 DETAILED DESCRIPTION OF EMBODIMENTS OF THE PRESENT DISCLOSURE
The present disclosure is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The present disclosure may, however, be embodied in different forms and is not intended to be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Same reference numbers indicate the same components throughout the present disclosure. In the accompanying drawings, the thicknesses of layers and regions are exaggerated for clarity.
The terms “a,” “an,” “the” and similar referents in the context of describing the present disclosure (especially in the context of the appended claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted.
Unless defined otherwise, all terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It is noted that the use of any and all examples, or exemplary terms provided herein is intended merely to better illuminate the present disclosure and is not intended to be a limitation on the scope of the present disclosure unless otherwise specified. Further, unless defined otherwise, all terms defined in generally used dictionaries are not intended to be overly interpreted.
The present disclosure will be described with reference to perspective views, cross-sectional views, and/or plan views, in which preferred embodiments of the present disclosure are shown. Thus, the profile of a view may be modified according to manufacturing techniques and/or allowances. That is, the embodiments of the present disclosure are not intended to limit the scope of the present disclosure but are intended to cover all changes and modifications that may be caused due to a change in manufacturing process. Thus, regions shown in the accompanying drawings are illustrated in schematic form and the shapes of the regions are presented simply by way of illustration and not as a limitation.
FIG. 1 is a circuit diagram of an analog filter 99.
Referring to FIG. 1, the analog filter 99 may include an amplifier 900 which receives input signals INn and INp through input resistors RG1 and feedback resistors RM and feedback capacitors CM which are connected in parallel to an input terminal and an output terminal of the amplifier 900, respectively. The input signals INn and INp provided to the amplifier 900 may be amplified and then output as output signals OUTn and OUTp, respectively. The input signals INn and INp may be, but are not limited to, differential signals.
Each of the input resistors RG1 and the feedback resistors RM may include, for example, a variable resistor. A gain and cutoff frequency of the analog filter 99 can be changed by varying resistance levels of the input resistors RG1 and the feedback resistors RM.
The cutoff frequency of the analog filter 99 may be inversely proportional to the resistance levels of the feedback resistors RM.
That is, when the resistance levels of the feedback resistors RM increase, the cutoff frequency of the analog filter 99 may decrease. Therefore, the analog filter 99 may operate as a narrowband filter that passes an input signal having a low frequency.
In addition, when the resistance levels of the feedback resistors RM decrease, the cutoff frequency of the analog filter 99 may increase. Therefore, the analog filter 99 may operate as a wideband filter that passes an input signal having a high frequency.
Furthermore, when the resistance levels of the feedback resistors RM are maintained in a certain range, the analog filter 99 may operate as a middleband or bandpass filter that passes an input signal having a frequency between a first frequency and a second frequency.
The feedback resistors RM and the feedback capacitors CM may be controlled by, e.g., a digital code to increase or decrease linearly or exponentially.
The analog filter 99 may include a passive device, which includes the input resistors RG1, the feedback resistors RM and the feedback capacitors CM, and the amplifier 900. The performance of the analog filter 99 may be greatly affected by the amplifier 900.
The amplifier 900 may be a two-stage amplifier that obtains a desired gain using two amplifiers. The two-stage amplifier is described below in greater detail with reference to FIGS. 2 and 3.
FIG. 2 is a circuit diagram of the amplifier 900 of FIG. 1. FIG. 3 is a diagram illustrating frequency characteristics of an amplifier 900 a of FIG. 2.
FIGS. 2 and 3 are diagrams illustrating the equivalent circuit diagram and frequency characteristics of the amplifier 900 of FIG. 1 if the amplifier 900 is configured as the two-stage amplifier 900 a.
Referring to FIG. 2, the two-stage amplifier 900 a may include a first amplifier 902 a which amplifies an input signal and a second amplifier 904 a which amplifies an output of the first amplifier 902 a.
Referring to FIG. 3, the two-stage amplifier 900 a may have two poles in its frequency characteristics. The two poles may reduce the phase of the two-stage amplifier 900 a, thus making the operation of the two-stage amplifier 900 a unstable.
To resolve an operational instability issue, a two-stage amplifier employing a Miller compensation method may be used. A two-stage amplifier employing the Miller compensation method is described below in greater detail with reference to FIGS. 4 and 5.
FIG. 4 is a circuit diagram of the amplifier 900 of FIG. 1. FIG. 5 is a diagram illustrating frequency characteristics of the amplifier 900 a of FIG. 2 and an amplifier 900 b of FIG. 4.
FIGS. 4 and 5 are a circuit diagram and a diagram illustrating frequency characteristics of the amplifier 900 of FIG. 1 configured as the Miller compensation two-stage amplifier 900 b.
Referring to FIG. 4, the Miller compensation two-stage amplifier 900 b may include a first amplifier 902 b which amplifies an input signal and a second amplifier 904 b which amplifies an output of the first amplifier 902 b. A Miller capacitor Cc for Miller compensation may be disposed between an input terminal and an output terminal of the second amplifier 904 b.
Referring to FIG. 5, a frequency characteristic curve {circle around (2)} of the Miller compensation two-stage amplifier 900 b is different from a frequency characteristic curve {circle around (1)} of the two-stage amplifier 900 a (see FIG. 2) not employing the Miller compensation method.
Specifically, in the frequency characteristic curve {circle around (2)} of the Miller compensation two-stage amplifier 900 b, two poles are split by the Miller capacitor Cc. That is, a first pole is moved to a low frequency band, and a second pole is moved to a high frequency band. Accordingly, the phase of the amplifier 900 of FIG. 1 configured as the Miller compensation two-stage amplifier 900 b increases, thereby improving the operational stability of the amplifier 900.
However, referring to the frequency characteristic curve {circle around (2)} of the Miller compensation two-stage amplifier 900 b, a gain of the high frequency band becomes significantly lower than that of the low frequency band. Therefore, as an operating frequency of the analog filter 99 increases (that is, when the analog filter 99 operates as a wideband filter), the operating efficiency thereof may be reduced.
To resolve the efficiency issue, a high-performance amplifier having a high gain in the high frequency band should be designed. However, if the Miller compensation method is employed as it is to resolve the efficiency issue, the current consumption of the analog filter 99 (see FIG. 1) becomes too high.
An analog filter according to an embodiment of the present disclosure, which can resolve the above issue, is described below with reference to FIGS. 6 through 12.
FIG. 6 is a circuit diagram of an analog filter 1 according to an embodiment of the present disclosure.
Referring to FIG. 6, the analog filter 1 may include a reconfigurable amplifier 100 which receives input signals INn and INp through input resistors RG1 and feedback resistors RM and feedback capacitors CM which are connected in parallel to an input terminal and an output terminal of the reconfigurable amplifier 100, respectively. The input signals INn and INp provided to the reconfigurable amplifier 100 may be amplified differently according to an operating mode of the reconfigurable amplifier 100 and then output as output signals OUTn and OUTp, respectively. The input signals INn and INp may be, but are not limited to, differential signals.
Each of the input resistors RG1 and the feedback resistors RM may include, for example, a variable resistor. A gain and cutoff frequency of the analog filter 1 may be changed by varying resistance levels of the input resistors RG1 and the feedback resistors RM.
The cutoff frequency of the analog filter 1 may be inversely proportional to the resistance levels of the feedback resistors RM.
That is, when the resistance levels of the feedback resistors RM increase, the cutoff frequency of the analog filter 1 may decrease. Therefore, the analog filter 1 may operate as a narrowband filter that passes an input signal having a low frequency. In this case, the reconfigurable amplifier 100 may operate in a narrowband mode.
In addition, when the resistance levels of the feedback resistors RM decrease, the cutoff frequency of the analog filter 1 may increase. Therefore, the analog filter 1 may operate as a wideband filter that passes an input signal having a high frequency. In this case, the reconfigurable amplifier 100 may operate in a wideband mode.
Furthermore, when the resistance levels of the feedback resistors RM are maintained in a certain range, the analog filter 1 may operate as a middleband or bandpass filter that passes an input signal having a frequency between a first frequency and a second frequency. In this case, the reconfigurable amplifier 100 may operate in a middleband mode.
The feedback resistors RM and the feedback capacitors CM may be controlled by, e.g., a digital code to increase or decrease linearly or exponentially.
FIG. 7 is a circuit diagram of the reconfigurable amplifier 100 of FIG. 6. FIG. 8 is a circuit diagram of a (compensation control circuits) 114 of FIG. 7. FIG. 9 is a circuit diagram of a feed forward control circuit 124 illustrated in FIG. 7.
Referring to FIG. 7, the reconfigurable amplifier 100 may include a gain circuit 110 and a feed forward circuit 120.
The gain circuit 110 may include a first amplifier AP1 which amplifies input signals INn and INp and a second amplifier AP2 which amplifies outputs of the first amplifier AP1. That is, the gain circuit 110 according to the current embodiment may include a two-stage amplifier.
As illustrated in the FIG. 7, each of the first amplifier AP1 and the second amplifier AP2 may include a transistor pair. The first amplifier AP1 and the second amplifier AP2 may form a gain path which amplifies the input signals INn and INp and outputs the amplified signals INn and INp as output signals OUTn and OUTp, respectively.
In an embodiment of the present disclosure, the gain circuit 110 may include the gate control circuit 114. The gain control circuit 114 may control a gain path to have a different capacitance configuration according to the operating mode of the reconfigurable amplifier 100.
Specifically, the gain control circuit 114 may control the capacitance configuration of the gain path when the reconfigurable amplifier 100 operates in the wideband mode to be different from the capacitance configuration of the gain path when the reconfigurable amplifier 100 operates in the middleband mode.
In addition, when the reconfigurable amplifier 100 operates in the narrowband mode, the gain control circuit 114 may control the reconfigurable amplifier 100 to operate as a Miller compensation amplifier. This is described in greater detail below.
Referring to FIG. 8, the gain control circuit 114 may include first through third switches SW1 through SW3 and a control capacitor CP and nulling R (one of the Miller compensation parameters).
The first switch SW1 may connect a first terminal of the control capacitor CP between the first amplifier AP1 and the second amplifier AP2. Specifically, when the first switch SW1 is turned on (e.g. closed), the first terminal of the control capacitor CP may be connected between the first amplifier AP1 and the second amplifier AP2. When the first switch SW1 is turned off (e.g. open), the first terminal of the control capacitor CP may not be connected between the first amplifier AP1 and the second amplifier AP2.
The second switch SW2 may connect a second terminal of the control capacitor CP to an output terminal of the second amplifier AP2. Specifically, when the second switch SW2 is turned on, the second terminal of the control capacitor CP may be connected to the output terminal of the second amplifier AP2. When the second switch SW2 is turned off, the second terminal of the control capacitor CP may not be connected to the output terminal of the second amplifier AP2.
The third switch SW3 may connect the second terminal of the control capacitor CP between the first amplifier AP1 and the second amplifier AP2. Specifically, when the third switch SW3 is turned on, the second terminal of the control capacitor CP may be connected between the first amplifier AP1 and the second amplifier AP2. When the third switch SW3 is turned off, the second terminal of the control capacitor CP may not be connected between the first amplifier AP1 and the second amplifier AP2.
As the operating mode of the reconfigurable amplifier 100 changes, the first through third switches SW1 through SW3 may be controlled as shown in Table 1 below.
TABLE 1
Mode SW1 SW2 SW3
Wideband mode OFF OFF OFF
Middleband mode ON OFF ON
Narrowband mode ON ON OFF
According to the operation of the first through third switches SW1 through SW3, when the reconfigurable amplifier 100 operates in the wideband mode, the control capacitor CP may not be connected to the gain path.
In addition, when the reconfigurable amplifier 100 operates in the middleband mode, the control capacitor CP may be connected between the first amplifier AP1 and the second amplifier AP2 of the gain path.
In addition, when the reconfigurable amplifier 100 operates in the narrowband mode, the control capacitor CP may be connected between an input terminal and the output terminal of the second amplifier AP2 of the gain path and serve as a Miller capacitor.
Referring back to FIG. 7, the feed forward circuit 120 may include a feed forward path, which receives the input signals INn and INp and performs feed forward compensation on the input signals INn and INp, and the feed forward control circuit 124.
The feed forward control circuit 124 may include a first transistor T1 which is gated by a voltage of a first node VP of the feed forward path, a fourth transistor T4 which is gated by a voltage of a second node VN of the feed forward path, and second and third transistors T2 and T3 which are gated by a voltage of a common mode node CM (or a common feedback loop such as a negative feedback loop of FIG. 14 described below).
Each of the first through fourth transistors T1 through T4 may include a plurality of transistors. In an embodiment of the present disclosure, each of the first through fourth transistors T1 through T4 may consist of a plurality of transistors, but the present disclosure is not limited thereto.
The first transistor T1 gated by the voltage of the first node VP of the feed forward path and the fourth transistor T4 gated by the voltage of the second node VN of the feed forward path may perform feed forward compensation, and the second and third transistors T2 and T3 gated by the voltage of the common mode node CM may function as a common feedback amplifier (CFA). Specifically, the first and fourth transistors T1 and T4 may be connected between an input terminal of the first amplifier AP1 and the output terminal of the second amplifier AP2 as illustrated in FIG. 7 to perform feed forward compensation, and the second and third transistors T2 and T3 may function as the CFA as illustrated in FIG. 7.
Referring to FIG. 9, in an embodiment of the present disclosure, the first transistor T1 included in the feed forward control circuit 124 may consist of four transistors T11 through T14, and the fourth transistor T4 included in the feed forward control circuit 124 may consist of four transistors T41 through T44.
In addition, the second transistor T2 included in the feed forward control circuit 124 may consist of four transistors T21 through T24, and the third transistor T3 included in the feed forward control circuit 124 may consist of four transistors T31 through T34.
While each of the first through fourth transistors T1 through T4 included in the feed forward control circuit 124 consists of four transistors in FIG. 9, the present disclosure is not limited thereto. The number of transistors that constitute each of the first through fourth transistors T1 through T4 included in the feed forward control circuit 124 may be changed.
Switches S1 through S8 may be disposed at respective terminals (e.g., drain terminals) of the transistors T11 through T14, T21 through T24, T31 through T34, and T41 through T44.
Each of the switches S1 through S8 may be controlled as shown in Table 2 below according to the operating mode of the reconfigurable amplifier 100.
TABLE 2
Mode S1 S2 S3 S4 S5 S6 S7 S8
Wideband ON ON ON OFF OFF OFF OFF ON
mode
Middleband ON ON OFF OFF OFF OFF ON ON
mode
1
Middleband ON OFF OFF OFF OFF ON ON ON
mode
2
Narrowband OFF OFF OFF OFF ON ON ON ON
mode

(/Sx (e.g. Sx-bar) indicates a switch that is controlled opposite to Sx. For example, when S1 is ON, /S1 is OFF and vice versa.)
The feed forward control circuit 124 according to an embodiment of the present disclosure may adjust the number of transistors that operate as the CFA of the reconfigurable amplifier 100 by operating as described above. Further, the feed forward control circuit 124 may deactivate the feed forward path of the reconfigurable amplifier 100.
Specifically, while the reconfigurable amplifier 100 operates in the wideband mode or the middleband mode, the feed forward control circuit 124 activates the feed forward path of the reconfigurable amplifier 100 such that feed forward compensation can be performed. In addition, while the reconfigurable amplifier 100 operates in the narrowband mode, the feed forward control circuit 124 deactivates the feed forward path of the reconfigurable amplifier 100 such that feed forward compensation is not performed in the reconfigurable amplifier 100.
The feed forward control circuit 124 may also control a relatively large number of transistors to operate as the CFA when the reconfigurable amplifier 100 operates in the wideband mode and control a relatively small number of transistors to operate as the CFA when the reconfigurable amplifier 100 operates in the middleband mode.
Further, the feedback forward control circuit 124 may change the number of transistors that operate as the CFA as desired when the reconfigurable amplifier 100 operates in the middleband mode.
Of the transistors T11 through T14, T21 through T24, T31 through T34 and T41 through T44 included in the feed forward control circuit 124, the number of transistors that are turned on may always be the same regardless of the operating mode of the reconfigurable amplifier 100. For example, in an embodiment of the present disclosure, eight transistors may always be turned on regardless of the operating mode of the reconfigurable amplifier 100.
The operation of the gain control circuit 114 and the feed forward control circuit 124 are described below.
FIGS. 10 through 12 are diagrams illustrating the operation of the reconfigurable amplifier 100 of FIG. 7 in the wideband mode.
FIG. 10 is a circuit diagram of the reconfigurable amplifier 100 operating in the wideband mode. FIG. 11 is a diagram illustrating the operation of the feed forward control circuit 124 when the reconfigurable amplifier 100 operates in the wideband mode. FIG. 12 is a circuit diagram of the reconfigurable amplifier 100 operating in the wideband mode.
Referring to FIG. 8 and Table 1 above, when the reconfigurable amplifier 100 operates in the wideband mode (e.g., when the analog filter 1 of FIG. 6 operates as a wideband filter that passes an input signal having a frequency of 10 MHz or more), all of the first through third switches SW1 through SW3 of the gain control circuit 114 are turned off.
Accordingly, the control capacitor CP is not connected to the gain path of the reconfigurable amplifier 100. Therefore, the gain path of the reconfigurable amplifier 100 does not include the control capacitor CP as illustrated in FIG. 10.
Referring to FIG. 11 and Table 2 above, when the reconfigurable amplifier 100 operates in the wideband mode (e.g., when the analog filter 1 of FIG. 6 operates as a wideband filter that passes an input signal have a frequency of 10 MHz or more), the switches S1 through S8 of the feed forward control circuit 124 are controlled as illustrated in FIG. 11.
Therefore, the feed forward path of the reconfigurable amplifier 100 is activated to perform feed forward compensation. In addition, three activated transistor pairs T11 through T13 and T41 through T43 in the feed forward path of the reconfigurable amplifier 100 operate as a feed forward compensation amplifier illustrated in FIG. 12.
FIG. 13 is a diagram illustrating frequency characteristics of the reconfigurable amplifier 100 of FIG. 7 operating in the wideband mode.
Referring to FIG. 13, a frequency characteristic curve {circle around (1)} of the two-stage amplifier 900 a (see FIG. 2) without employing the Miller compensation method and a frequency characteristic curve {circle around (2)} of the Miller compensation two-stage amplifier 900 b (see FIG. 4) are compared with a frequency characteristic curve {circle around (3)} of the reconfigurable amplifier 100 according to an embodiment of the present disclosure.
If the frequency characteristic curve {circle around (2)} of the Miller compensation two-stage amplifier 900 b is compared with the frequency characteristic curve {circle around (3)} of the reconfigurable amplifier 100 the reconfigurable amplifier 100 has a considerably improved gain of a high frequency band, because it performs feed forward compensation in the wideband mode as described above.
Further, if the frequency characteristic curve {circle around (1)} of the two-stage amplifier 900 a without employing the Miller compensation method is compared with the frequency characteristic curve {circle around (3)} of the reconfigurable amplifier 100, the reconfigurable amplifier 100 has better phase characteristics than the two-stage amplifier 900 a without employing the Miller compensation method.
FIGS. 14 through 17 are diagrams illustrating the operation of the reconfigurable amplifier 100 of FIG. 7 in the middleband mode.
FIG. 14 illustrates a circuit diagram of the reconfigurable amplifier 100 operating in the wideband mode from a common mode perspective.
Referring to FIG. 6, when the reconfigurable amplifier 100 operates in the wideband mode, the resistance levels of the feedback resistors RM of the analog filter 1 are generally low. Therefore, a gain of a positive feedback loop illustrated in FIG. 14 is always lower than that of a negative feedback loop.
However, when the reconfigurable amplifier 100 operates in the middleband mode, the resistance levels of the feedback resistors RM of the analog filter 1 increase. Therefore, if the above-described feed forward compensation is performed without any adjustment, the gain of the positive feedback loop may become higher than that of the negative feedback loop.
In this case, the operation of the reconfigurable amplifier 100 may become unstable. Therefore, when the reconfigurable amplifier 100 operates in the middleband mode, the gain of the negative feedback loop must be reinforced as compared to when the reconfigurable amplifier 100 operates in the wideband mode.
Accordingly, in the reconfigurable amplifier 100 according to an embodiment of the present disclosure, the feed forward control circuit 124 may be adjusted to improve a common mode rejection function for reinforcing the gain of the negative feedback loop. This is described in greater detail below with reference to FIGS. 15 through 17.
FIG. 15 is a circuit diagram of the reconfigurable amplifier 100 operating in the middleband mode. FIGS. 16 and 17 are diagrams illustrating the operation of the feed forward control circuit 124 when the reconfigurable amplifier 100 operates in the middleband mode.
Referring to FIG. 8 and Table 1 above, when the reconfigurable amplifier 100 operates in the middleband mode (e.g., when the analog filter 1 of FIG. 6 operates as a middleband filter that passes an input signal having a frequency of 2 to 10 MHz), the first and third switches SW1 and SW3 of the gain control circuit 114 are turned on, and the second switch SW2 is turned off.
Accordingly, the control capacitor CP may be connected between the first amplifier AP1 and the second amplifier AP2 of the gain path as illustrated in FIGS. 15 and 18.
Referring to FIG. 16 and Table 2 above, when the reconfigurable amplifier 100 operates in a first middleband mode (e.g., when the analog filter 1 of FIG. 6 operates as a middleband filter that passes an input signal having a frequency of 6 to 10 MHz), the switches S1 through S8 of the feed forward control circuit 124 may be controlled as illustrated in FIG. 16.
Therefore, the feed forward path of the reconfigurable amplifier 100 may be activated, and two activated transistor pairs T11 and T12 and T41 and T42 in the feed forward path of the reconfigurable amplifier 100 may perform feed forward compensation. In addition, two transistor pairs T23 and T24 and T33 and T34 are placed in the common feedback loop. Therefore, the common mode rejection function for reinforcing the gain of the negative feedback loop can be improved as compared to when the reconfigurable amplifier 100 operates in the wideband mode as illustrated in FIG. 11.
Referring to FIG. 17 and Table 2 above, when the reconfigurable amplifier 100 operates in a second middleband mode (e.g., when the analog filter 1 of FIG. 6 operates as a middleband filter that passes an input signal having a frequency of 2 to 6 MHz), the switches S1 through S8 of the feed forward control circuit 124 may be controlled as illustrated in FIG. 17.
Therefore, the feed forward path of the reconfigurable amplifier 100 may be activated to perform feed forward compensation. In addition, one activated transistor pair T11 and T41 in the feed forward path of the reconfigurable amplifier 100 may operate as the CFA illustrated in FIG. 15. Further, three transistor pairs T22 through T24 and T32 through T34 are placed in the common feedback loop. Therefore, the common mode rejection function for reinforcing the gain of the negative feedback loop can be improved further.
FIGS. 18 and 19 are diagrams illustrating the operation of the reconfigurable amplifier 100 of FIG. 7 in the narrowband mode.
FIG. 18 is a circuit diagram of the reconfigurable amplifier 100 operating in the narrowband mode. FIG. 19 is a diagram illustrating the operation of the feed forward control circuit 124 when the reconfigurable amplifier 100 operates in the narrowband mode.
Referring to FIG. 8 and Table 1 above, when the reconfigurable amplifier 100 operates in the narrowband mode (e.g., when the analog filter 1 of FIG. 6 operates as a narrowband filter that passes an input signal having a frequency of 2 MHz), the first and second switches SW1 and SW2 of the gain control circuit 114 are turned on, and the third switch SW3 is turned off.
Accordingly, the control capacitor CP may be connected between the input terminal and the output terminal of the second amplifier AP2 of the gain path as illustrated in FIG. 19. That is, the control capacitor CP may serve as the Miller capacitor Cc illustrated in FIG. 4. Accordingly, the reconfigurable amplifier 100 may perform Miller compensation.
Referring to FIG. 19 and Table 2 above, when the reconfigurable amplifier 100 operates in the narrowband mode (e.g., when the analog filter 1 of FIG. 6 operates as a narrowband filter that passes an input signal have a frequency of 2 MHz or less), the switches S1 through S8 of the feed forward control circuit 124 may be controlled as illustrated in FIG. 19.
That is, the feed forward path of the reconfigurable amplifier 100 may be deactivated to not perform feed forward compensation.
Since the reconfigurable amplifier 100 according to the current embodiment can apply a different compensation method according to its operating mode, the operational performance and stability of the reconfigurable amplifier 100 can be improved.
Specifically, a feed forward compensation method is applied when the reconfigurable amplifier 100 operates in the wideband mode. Therefore, gain characteristics of the reconfigurable amplifier 100 can be improved.
In addition, a Miller compensation method is applied when the reconfigurable amplifier 100 operates in the narrowband mode. Therefore, the operational stability of the reconfigurable amplifier 100 can be improved.
Furthermore, when the reconfigurable amplifier 100 operates in the middleband mode, the gain of the positive feedback loop and the gain of the negative feedback loop are adaptively adjusted according to the cutoff frequency of the analog filter 1. Therefore, the operational stability of the reconfigurable amplifier 100 can be improved.
FIG. 20 is a circuit diagram of an analog filter 2 according to an embodiment of the present disclosure. The embodiments of the present disclosure are described, focusing mainly on differences between other embodiments of the present disclosure.
Referring to FIG. 20, the analog filter 2 may include additional reconfigurable amplifiers as compared with the analog filter 1 (see FIG. 6) described above.
Specifically, the analog filter 2 may be a two-stage filter including a first reconfigurable amplifier 200 a and a second reconfigurable amplifier 200 b.
Each of the first and second reconfigurable amplifiers 200 a and 200 b may employ substantially the same configuration as the reconfigurable amplifier 100 (see FIG. 6) described above.
Each of input resistors RG1 and feedback resistors RM and RMQ may include, for example, a variable resistor. A gain and cutoff frequency of the analog filter 2 may be changed by varying resistance levels of the input resistors RG1 and the feedback resistors RM and RMQ.
The feedback resistors RM and RMQ and feedback capacitors CM may be controlled by, e.g., a digital code to increase or decrease linearly or exponentially.
While the present disclosure has been shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope and spirit of the present disclosure as defined by the appended claims and their equivalents.

Claims (16)

What is claimed is:
1. A reconfigurable amplifier, comprising:
a gain circuit comprising a gain path configured to amplify an input signal; and
a feed forward circuit comprising a feed forward path configured to receive the input signal and perform feed forward compensation on the input signal,
and a first control circuit configured to perform the feed forward compensation in a first mode by activating the feed forward path, and deactivate the feed forward path in a second mode different from the first mode, wherein the first control circuit comprises a plurality of first transistors gated by the feed forward path and a plurality of second transistors gated by a common feedback loop.
2. The reconfigurable amplifier of claim 1, wherein the gain circuit further comprises a first amplifier configured to amplify the input signal and a second amplifier configured to further amplify the amplified input signal.
3. The reconfigurable amplifier of claim 1, wherein the first control circuit is further configured to perform the feed forward compensation in a third mode different from the first and second modes by activating the feed forward path and perform the feed forward compensation in the first mode and the third mode using different numbers of transistors.
4. The reconfigurable amplifier of claim 1, wherein a sum of the plurality of first transistors configured to be turned on and the second transistors configured to be turned on is constant regardless of the first or second mode.
5. The reconfigurable amplifier of claim 1, wherein m of the plurality of first transistors are turned on in the first mode, and n of the plurality of first transistors are turned on in the second mode, wherein m is an integer greater than or equal to one, and n is an integer greater than or equal to zero and less than m.
6. The reconfigurable amplifier of claim 1, wherein the gain circuit further comprises a second control circuit configured to control the gain path to have different capacitance configurations in the first mode and the second mode, wherein the capacitance configurations indicate which element of the second control circuit connects to a capacitance.
7. The reconfigurable amplifier of claim 6, wherein the second control circuit is configured to control the gain path to have a different capacitance configuration in a third mode, which is different from the first and second modes, from the capacitance configurations in the first and second modes.
8. A reconfigurable amplifier, comprising:
a gain circuit comprising a first amplifier configured to amplify an input signal and a second amplifier configured to amplify an output of the first amplifier;
a feed forward circuit connected to an input terminal of the first amplifier and an output terminal of the second amplifier and configured to perform feed forward compensation;
a common feedback amplifier; and
a control circuit configured to control the gain circuit to have a first capacitance configuration in a first mode and control the gain circuit to have a second capacitance configuration, which is different from the first capacitance configuration, in a second mode different from the first mode, wherein the capacitance configurations indicate which element of the second control circuit connects to a capacitance.
9. The reconfigurable amplifier of claim 8, wherein the control circuit comprises a capacitor having a first terminal connected to an input terminal of the second amplifier, and having a second terminal of the capacitor that is not connected to the output terminal of the second amplifier in the first mode but is connected to the output terminal of the second amplifier in the second mode.
10. The reconfigurable amplifier of claim 8, wherein the control circuit comprises a switch having a first terminal connected to the input terminal of the second amplifier and a second terminal connected to a capacitor, wherein the switch is configured to be turned off in the first mode and turned on in the second mode.
11. The reconfigurable amplifier of claim 8, wherein the control circuit is further configured to control the gain circuit to have a third capacitance configuration, which is different from the first and second capacitance configurations, in a third mode different from the first and second modes.
12. The reconfigurable amplifier of claim 11, wherein the control circuit comprises:
a first switch configured to be turned off in the first mode and turned on in the second and third modes;
a capacitor connected in series with the first switch;
a second switch configured to be turned off in the first and third modes and turned on in the second mode to connect the capacitor between the input terminal and the output terminal of the second amplifier; and
a third switch configured to be turned off in the first and second modes and turned on in the third mode to connect the capacitor between an output terminal of the first amplifier and the input terminal of the second amplifier.
13. A reconfigurable amplifier, comprising:
a gain circuit comprising a first amplifier configured to amplify an input signal and a second amplifier configured to amplify an output of the first amplifier; and
a feed forward circuit and a control circuit connected to an input terminal of the first amplifier and an output terminal of the second amplifier and configured to perform feed forward compensation,
wherein the control circuit is further configured to perform feed forward compensation in a first mode using m first transistors and perform feed forward compensation in a second mode different from the first mode using n first transistors, wherein m is an integer greater than or equal to one, and n is an integer greater than or equal to zero and less than m.
14. The reconfigurable amplifier of claim 13, wherein the first mode is a mode in which an input signal having a first frequency is passed and an input signal having a second frequency less than the first frequency is filtered, and the second mode is a mode in which the input signal having the second frequency is passed and the input signal having the first frequency is filtered.
15. The reconfigurable amplifier of claim 13, wherein m is a natural number, and n is zero in the second mode.
16. The reconfigurable amplifier of claim 13, wherein the control circuit further comprises k second transistors gated by a voltage level of a first node and connected in parallel to each other, and the n first transistors are gated by a voltage level of a second node different from the first node and connected in parallel to each other, wherein k is an integer greater than or equal to zero.
US15/164,389 2015-07-22 2016-05-25 Multimode reconfigurable amplifier and analog filter including the same Active US9912311B2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR10-2015-0103861 2015-07-22
KR20150103861 2015-07-22
KR10-2015-0107229 2015-07-29
KR20150107229 2015-07-29
KR10-2015-0135531 2015-09-24
KR1020150135531A KR102476218B1 (en) 2015-07-22 2015-09-24 Multi mode reconfigurable amplifier and analog filter comprising the same

Publications (2)

Publication Number Publication Date
US20170026030A1 US20170026030A1 (en) 2017-01-26
US9912311B2 true US9912311B2 (en) 2018-03-06

Family

ID=57738912

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/164,389 Active US9912311B2 (en) 2015-07-22 2016-05-25 Multimode reconfigurable amplifier and analog filter including the same

Country Status (3)

Country Link
US (1) US9912311B2 (en)
CN (1) CN106374856B (en)
DE (1) DE102016211037A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10594278B2 (en) 2017-09-06 2020-03-17 Samsung Electronics Co., Ltd. Pole-splitting and feedforward capacitors in common mode feedback of fully differential amplifier
US10873304B2 (en) 2017-09-06 2020-12-22 Samsung Electronics Co., Ltd. Pole-splitting and feedforward capacitors in common mode feedback of fully differential amplifier
TWI738575B (en) * 2020-11-27 2021-09-01 達發科技股份有限公司 Filter circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199995B2 (en) * 2016-03-30 2019-02-05 Mediatek Inc. Programmable amplifier circuit capable of providing large or larger resistance for feedback path of its amplifier

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155447A (en) 1991-02-11 1992-10-13 Signetics Company Multi-stage amplifier with capacitive nesting and multi-path forward feeding for frequency compensation
US6300816B1 (en) * 2000-10-24 2001-10-09 Rosun Technologies, Inc. Feedforward-controlled sense amplifier
US6392481B1 (en) 1999-11-30 2002-05-21 Nokia Networks Oy Method and apparatus for improved fed forward amplification
US6573790B2 (en) 1998-07-13 2003-06-03 Esion Llc Wide-bandwidth operational amplifier
US6573791B2 (en) 2001-09-28 2003-06-03 Koninklijke Philips Electronics N.V. Multipath nested Gm nested miller compensation
US20030122621A1 (en) 2001-05-18 2003-07-03 Stefanos Sidiropoulos Reconfigurable dual-mode multiple stage operational amplifiers
US6989716B2 (en) 2002-12-12 2006-01-24 Electronics And Telecommunications Research Institute Variable gain amplifier
US20060121873A1 (en) * 2003-09-18 2006-06-08 Xytrans, Inc. Multi-channel radiometer imaging system and MMIC chips for use thereof
KR100613428B1 (en) 2004-08-19 2006-08-17 한양대학교 산학협력단 Differential operational amplifier with current re-using feedforward frequency compensation
KR100652207B1 (en) 2006-01-11 2006-12-01 한양대학교 산학협력단 Voltage negative feedback low noise amplifier for multi-mode and multi-band rf receiver
US7403070B2 (en) 2005-06-03 2008-07-22 Ntt Docomo, Inc. Band selection type feed forward amplifier
US7466205B1 (en) 2007-06-20 2008-12-16 National Taiwan University Ultra-wideband low noise amplifier and amplification method thereof
KR20090047619A (en) 2007-11-08 2009-05-13 엘지전자 주식회사 Wide band amplifier
US7911269B2 (en) * 2009-01-19 2011-03-22 Qualcomm Incorporated Ultra low noise high linearity LNA for multi-mode transceiver
KR101038854B1 (en) 2008-06-24 2011-06-02 어윤성 Wide-band low noise amplifier
US8604879B2 (en) 2012-03-30 2013-12-10 Integrated Device Technology Inc. Matched feedback amplifier with improved linearity
US20140266433A1 (en) * 2013-03-14 2014-09-18 Peregrine Semiconductor Corporation Systems and Methods for Optimizing Amplifier Operations
JP2015033083A (en) 2013-08-06 2015-02-16 三菱電機株式会社 Multiband amplifier

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5830201B2 (en) 2013-08-06 2015-12-09 株式会社ダイセル Curable resin composition and semiconductor device using the same
KR101573362B1 (en) 2014-03-04 2015-12-02 전자부품연구원 Fast and Flexible Digital Hologram Generation Method and Apparatus
KR102134159B1 (en) 2014-03-13 2020-07-15 엘지전자 주식회사 Mobile terminal
CN204103873U (en) * 2014-10-28 2015-01-14 李梦雄 A kind of active feed forward circuit forms frequency compensated differential operational amplifier

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155447A (en) 1991-02-11 1992-10-13 Signetics Company Multi-stage amplifier with capacitive nesting and multi-path forward feeding for frequency compensation
US6573790B2 (en) 1998-07-13 2003-06-03 Esion Llc Wide-bandwidth operational amplifier
US6392481B1 (en) 1999-11-30 2002-05-21 Nokia Networks Oy Method and apparatus for improved fed forward amplification
US6300816B1 (en) * 2000-10-24 2001-10-09 Rosun Technologies, Inc. Feedforward-controlled sense amplifier
US20030122621A1 (en) 2001-05-18 2003-07-03 Stefanos Sidiropoulos Reconfigurable dual-mode multiple stage operational amplifiers
US6573791B2 (en) 2001-09-28 2003-06-03 Koninklijke Philips Electronics N.V. Multipath nested Gm nested miller compensation
US6989716B2 (en) 2002-12-12 2006-01-24 Electronics And Telecommunications Research Institute Variable gain amplifier
US20060121873A1 (en) * 2003-09-18 2006-06-08 Xytrans, Inc. Multi-channel radiometer imaging system and MMIC chips for use thereof
KR100613428B1 (en) 2004-08-19 2006-08-17 한양대학교 산학협력단 Differential operational amplifier with current re-using feedforward frequency compensation
US7403070B2 (en) 2005-06-03 2008-07-22 Ntt Docomo, Inc. Band selection type feed forward amplifier
KR100652207B1 (en) 2006-01-11 2006-12-01 한양대학교 산학협력단 Voltage negative feedback low noise amplifier for multi-mode and multi-band rf receiver
US7466205B1 (en) 2007-06-20 2008-12-16 National Taiwan University Ultra-wideband low noise amplifier and amplification method thereof
KR20090047619A (en) 2007-11-08 2009-05-13 엘지전자 주식회사 Wide band amplifier
KR101038854B1 (en) 2008-06-24 2011-06-02 어윤성 Wide-band low noise amplifier
US7911269B2 (en) * 2009-01-19 2011-03-22 Qualcomm Incorporated Ultra low noise high linearity LNA for multi-mode transceiver
US8604879B2 (en) 2012-03-30 2013-12-10 Integrated Device Technology Inc. Matched feedback amplifier with improved linearity
US20140266433A1 (en) * 2013-03-14 2014-09-18 Peregrine Semiconductor Corporation Systems and Methods for Optimizing Amplifier Operations
JP2015033083A (en) 2013-08-06 2015-02-16 三菱電機株式会社 Multiband amplifier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10594278B2 (en) 2017-09-06 2020-03-17 Samsung Electronics Co., Ltd. Pole-splitting and feedforward capacitors in common mode feedback of fully differential amplifier
US10873304B2 (en) 2017-09-06 2020-12-22 Samsung Electronics Co., Ltd. Pole-splitting and feedforward capacitors in common mode feedback of fully differential amplifier
TWI738575B (en) * 2020-11-27 2021-09-01 達發科技股份有限公司 Filter circuit

Also Published As

Publication number Publication date
DE102016211037A1 (en) 2017-01-26
US20170026030A1 (en) 2017-01-26
CN106374856B (en) 2021-06-11
CN106374856A (en) 2017-02-01

Similar Documents

Publication Publication Date Title
CN105375885B (en) System and method for low-noise amplifier
US9912311B2 (en) Multimode reconfigurable amplifier and analog filter including the same
US8395448B2 (en) Apparatus and method for miller compensation for multi-stage amplifier
US7551033B2 (en) Dynamic bandwidth compensating method and associated apparatus
CN106656068B (en) Dual operation mode power amplifier
US7420423B2 (en) Active balun device
US9219452B2 (en) Dual mode receiver with RF splitter using programmable passive components
US7385442B1 (en) System and method for constant bandwidth DC offset correction in an amplifier
US8648652B2 (en) Band pass filter and calibration method for band pass filter
US9263995B2 (en) Multi-mode OPAMP-based circuit
TWI756258B (en) Low-noise amplifier having programmable-phase gain stage
CN108540102B (en) Programmable gain amplifier
US20160173063A1 (en) Analog baseband filtering apparatus of multimode multiband wireless transceiver and control method thereof
Im et al. A CMOS active feedback wideband single-to-differential LNA using inductive shunt-peaking for saw-less SDR receivers
JP2009005092A (en) Variable-gain low noise amplifier
US6831506B1 (en) Reconfigurable filter architecture
KR102476218B1 (en) Multi mode reconfigurable amplifier and analog filter comprising the same
KR20240001041A (en) Radio frequency, rf, amplifier circuit with a feedback circuit and method for adjusting a gain mode of a rf amplifier circuit
US7928800B2 (en) Programmable compensation network for operational amplifiers
US20200059210A1 (en) Amplification device with isolation characteristics
US10938357B2 (en) Audio amplifier with integrated filter
WO2013166238A1 (en) Compensation technique for feedback amplifiers
KR20150096193A (en) low noise amplifier supporting multiple gain modes
US9698738B2 (en) Bandpass filter providing wide gain control range
TWI683533B (en) Amplification circuit

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KANG, SO-YOUNG;CHO, THOMAS BYUNG-HAK;SHIN, HEE-SEON;AND OTHERS;SIGNING DATES FROM 20160518 TO 20160620;REEL/FRAME:039175/0986

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4