US9857532B2 - Semiconductor device packages - Google Patents

Semiconductor device packages Download PDF

Info

Publication number
US9857532B2
US9857532B2 US15/406,509 US201715406509A US9857532B2 US 9857532 B2 US9857532 B2 US 9857532B2 US 201715406509 A US201715406509 A US 201715406509A US 9857532 B2 US9857532 B2 US 9857532B2
Authority
US
United States
Prior art keywords
sidewall
substrate
optical
semiconductor device
optical element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US15/406,509
Other versions
US20170336561A1 (en
Inventor
Yi-Min Chin
Jia-Hao ZHANG
Chi-han Chen
Mei-Ju Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to US15/406,509 priority Critical patent/US9857532B2/en
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC. reassignment ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, CHI-HAN, CHIN, YI-MIN, LU, Mei-ju, ZHANG, Jia-hao
Priority to CN201710128162.7A priority patent/CN107403766B/en
Publication of US20170336561A1 publication Critical patent/US20170336561A1/en
Application granted granted Critical
Publication of US9857532B2 publication Critical patent/US9857532B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
    • G02B6/4214—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G02B6/423—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using guiding surfaces for the alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
    • H01L31/167—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers

Definitions

  • the present disclosure relates to a semiconductor device package.
  • the present disclosure relates to a semiconductor device package including optical devices.
  • a waveguide can be used to guide light from a light emitter to an optical sensor in a semiconductor device package.
  • distance between a light emitter and an optical sensor may result in lower optical transmission efficiency and lower accuracy of a coupling facet.
  • a comparable manufacturing process includes singulating or cutting a wafer including a waveguide into a plurality of optical devices by using a blade saw.
  • an uneven sidewall of each optical device may degrade quality of light transmission when integrating or coupling the optical device to an optical fiber or laser diode.
  • One approach to address the above problem may be to polish the sidewall of the optical devices and to subsequently coat an anti-reflection film on the sidewall.
  • cost of a manufacturing process would increase and the process would become more complicated.
  • a semiconductor device in some embodiments, includes a substrate, a passivation layer and an optical element.
  • the substrate includes a surface and a sidewall.
  • the passivation layer is disposed on the surface of the substrate.
  • the optical element is disposed in the substrate and exposed from the sidewall of the substrate.
  • the sidewall of the substrate is inclined towards the surface of the substrate at an angle of approximately 87 degrees to approximately 89 degrees.
  • a semiconductor device package includes a first optical device and a second optical device.
  • the first optical device includes a first substrate including a first surface and a first sidewall, a passivation layer on the first surface of the first substrate, and a first optical element in the first substrate and exposed from the first sidewall of the first substrate, the first optical element comprising a sidewall.
  • the second optical device includes a second substrate including a second sidewall, a second optical element in the second substrate and exposed from the second sidewall of the second substrate, the second optical element comprising a sidewall.
  • a lateral distance between the first sidewall of the first optical element of the first optical device and the second sidewall of the second optical element of the second optical device is less than about 2 micrometers ( ⁇ m).
  • a semiconductor wafer includes a semiconductor body, a passivation layer and a trench.
  • the semiconductor body includes a surface and a plurality of optical devices, wherein each of the plurality of optical devices includes a plurality of edges.
  • the passivation layer is disposed on each of the optical devices.
  • the trench corresponds to each of the plurality of optical devices and is recessed from the first surface of the semiconductor body, and the trench is adjacent to one of the plurality of edges of each of the optical devices.
  • a semiconductor device in some embodiments, includes a substrate, a passivation layer and an optical element.
  • the substrate includes a surface and a sidewall.
  • the passivation layer is disposed on the surface of the substrate.
  • the optical element is disposed in the substrate and is exposed from the sidewall of the substrate.
  • the passivation layer includes a curved sidewall adjacent to the sidewall of the substrate.
  • FIG. 1 is a perspective view of a semiconductor device package in accordance with some embodiments of the present disclosure.
  • FIG. 2 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure.
  • FIG. 3 is an example of an inclined structure in accordance with some embodiments of the present disclosure.
  • FIG. 4A , FIG. 4B and FIG. 4C illustrate a method of manufacturing a semiconductor device in accordance with some embodiments of the present disclosure.
  • FIG. 5A and FIG. 5B are side-sectional views of a semiconductor wafer in accordance with some embodiments of the present disclosure.
  • FIG. 5C and FIG. 5D are side-sectional views of the semiconductor device shown in FIG. 5B in accordance with some embodiments of the present disclosure.
  • FIG. 6A and FIG. 6B are side-sectional views of a semiconductor device package in accordance with some embodiments of the present disclosure.
  • optical devices according to some embodiments having improved quality of light transmission. Moreover, the optical devices according to some embodiments may reduce the large distances between a light emitter and an optical sensor that lower optical transmission efficiency and lower accuracy of a coupling facet.
  • FIG. 1 is a perspective view of a semiconductor device package 1 in accordance with some embodiments of the present disclosure.
  • the semiconductor device package 1 includes two optical devices 22 and 24 .
  • the optical device 22 includes a substrate (or first substrate) 10 , an optical element (or first optical element) 30 , a passivation layer 16 and a semiconductor oxide layer 18 .
  • the substrate 10 may include, for example, silicon (Si) or one or more other suitable materials.
  • the passivation layer 16 may include, for example, silicon dioxide (SiO 2 ), or one or more other suitable materials.
  • the semiconductor oxide layer 18 may include, for example, silicon oxide (SiO x ), or one or more other suitable materials.
  • the optical element 30 may be a waveguide.
  • the optical element 30 may include, for example, Si or one or more other suitable materials.
  • a thickness of the optical element 30 may be less than about 10 micrometers ( ⁇ m).
  • the optical device 24 includes a substrate (or second substrate) 20 and an optical element (or second optical element) 40 .
  • the substrate 20 may include, for example, Si or one or more other suitable materials.
  • the optical element 40 may be an optical fiber, laser diode or other suitable element.
  • the laser diode or optical fiber of the optical element 40 may be optically coupled to the optical element 30 (e.g., waveguide).
  • the optical device 24 may be suspended on the substrate 20 .
  • the optical device 24 may be latched on the substrate 20 .
  • the substrate 10 includes a surface (or first surface) 101 and a sidewall (or first sidewall) 103 .
  • the passivation layer 16 is disposed on the surface 101 of the substrate 10 .
  • the optical element 30 includes a sidewall 303 .
  • the sidewall 303 of the optical element 30 is continuous with and substantially coplanar with the sidewall 103 of the substrate 10 .
  • a shape of an opening of the optical element 30 at the sidewall 303 is a square or rectangle.
  • a roughness of the sidewall 103 of the substrate 10 may be less than about 1.5 such as about 1.4 ⁇ m or less, about 1.2 ⁇ m or less, or about 1 ⁇ m or less in terms of root-mean-square surface roughness.
  • the semiconductor oxide layer 18 includes a sidewall 503 .
  • the substrate 20 includes a sidewall (or second sidewall) 203 .
  • the optical element 40 includes a sidewall 403 .
  • a distance D 1 is defined between the sidewall 303 of the optical element 30 and the sidewall 403 of the optical element 40 .
  • the distance D 1 between the exposed portion of the first optical device 22 and the exposed portion of the second optical device 24 may be less than about 2 such as about 1.9 ⁇ m or less, about 1.8 ⁇ m or less, or about 1.7 ⁇ m or less.
  • FIG. 2 is a cross-sectional view of a semiconductor device (e.g., optical device 22 ) in accordance with some embodiments of the present disclosure.
  • the optical element 30 of the optical device 22 is disposed in the substrate 10 and exposed from the first sidewall 103 .
  • the first sidewall 103 is inclined or curved towards the first surface 101 at an angle of less than 90 degrees or approximately 87 degrees to approximately 89 degrees.
  • the passivation layer 16 includes a curved sidewall adjacent to the first sidewall 103 .
  • a thickness of the substrate 10 e.g., a particular layer of the substrate 10
  • may be greater than about 400 ⁇ m and a thickness of the passivation layer 16 may be about 10 ⁇ m to about 15 ⁇ m.
  • FIG. 3 is an example of an inclined structure in accordance with some embodiments of the present disclosure. As shown in FIG. 3 , the angle of the upper corner of the inclined structure may be approximately 87 degrees to approximately 89 degrees.
  • FIGS. 4A, 4B and 4C illustrate a method of manufacturing a semiconductor device (e.g., optical device 22 ) in accordance with some embodiments of the present disclosure.
  • a semiconductor body (e.g., substrate) 10 is provided.
  • the semiconductor body 10 may include, for example, Si or one or more other suitable materials.
  • the patterned passivation layer 16 is formed on the first surface 101 of the semiconductor body 10 .
  • the optical element 30 and the semiconductor oxide layer 18 are formed in the semiconductor body 10 .
  • the semiconductor oxide layer 18 may include, for example, SiO x or one or more other suitable materials.
  • the optical element 30 may include, for example, Si or one or more other suitable materials.
  • a warpage of the semiconductor body 10 may be about 5 ⁇ m to about 10 ⁇ m.
  • the semiconductor body 10 and a portion of the passivation layer 16 are etched (e.g., using Deep Reactive Ion Etching (DRIE)).
  • the passivation layer 16 includes a curved sidewall adjacent to the first sidewall 103 .
  • a trench 52 is recessed from the first surface 103 of the semiconductor body 10 .
  • the first surface 103 is exposed within the trench 52 .
  • a backside grinding 92 is performed to reduce a thickness of the semiconductor body 10 .
  • a portion of the semiconductor body 10 is removed from the bottom surface of the semiconductor body 10 , such as by backside grinding 92 , until the trench 52 penetrates fully through the semiconductor body 10 such that the optical devices 22 are singulated to form individual optical device 22 as shown in FIG. 1 and FIG. 2 .
  • the optical devices 22 are separated using the backside grinding.
  • the backside grinding may be performed by using a rotatable polishing pad.
  • the first surface 101 of the semiconductor body 10 is partially covered by the passivation layer 16 and the semiconductor body 10 thus includes a protruding portion not covered by the passivation layer 16 .
  • Using DRIE in the manufacturing process may reduce steps of the manufacturing process and accordingly the roughness of the first sidewall 103 of the substrate 10 may be less than about 1.5 ⁇ m.
  • the distance D 1 between the sidewall 303 of the optical element 30 and the sidewall 403 of the optical element 40 may be reduced to be less than about 2 ⁇ m.
  • FIGS. 5A and 5B are side-sectional views of a semiconductor wafer 2 in accordance with some embodiments of the present disclosure.
  • the semiconductor wafer 2 is shown prior to singulation.
  • the semiconductor wafer 2 includes a surface 501 and a plurality of optical devices 22 .
  • Each of the plurality of optical devices 22 includes a plurality of edges.
  • a plurality of passivation layers 16 are disposed on each of the optical devices 22 .
  • the passivation layer 16 includes the curved sidewall.
  • the trench 52 is recessed from a first surface 501 of a semiconductor body 50 .
  • An opening 220 of the trench 52 includes a plurality of edges, and one of the plurality of edges of the opening 220 has a length L 1 .
  • One of the edges of the optical devices 22 has a length L 2 .
  • the trench 52 is adjacent to one of the plurality of edges of each of the optical devices 22 .
  • the trench 52 passes through or penetrates through the semiconductor body 50 .
  • the length L 1 of the opening 220 of the trench 52 may be equal to or less than the length L 2 of the edge of the optical devices 22 .
  • the optical devices 22 are separated after the backside grinding 92 is performed (e.g., by using a rotatable polishing pad).
  • FIGS. 5C and 5D are side-sectional views of a semiconductor device (e.g., optical device 22 ) of FIG. 5B in accordance with some embodiments of the present disclosure.
  • the optical devices 22 are separated by the backside grinding 92 .
  • the optical elements 30 are exposed by the first sidewall 103 .
  • the edges of the substrate 10 can be used to support or engage other suitable optical elements.
  • the opening 220 of the substrate 10 can be used to support or engage other suitable inserted optical elements.
  • FIGS. 6A and 6B are side-sectional views of semiconductor device packages 3 and 4 , respectively, in accordance with some embodiments of the present disclosure.
  • the semiconductor device package 3 includes optical devices 22 and 24 .
  • the optical element 30 e.g., waveguide
  • the optical element 30 is precisely aligned with the optical element 40 by inserting the optical device 24 into the opening 220 .
  • the semiconductor device package 4 includes optical devices 22 and 24 .
  • the optical element 30 (e.g., waveguide) is precisely aligned with the optical element 40 by engaging the optical device 24 .
  • the terms “approximately” and “about” are used to describe and account for small variations.
  • the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
  • the terms can encompass a range of variation of less than or equal to ⁇ 10% of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • a first angle may be approximately the same as a second angle if a difference between the first angle and the second angle is less than or equal to ⁇ 10°, such as ⁇ 5°, ⁇ 4°, ⁇ 3°, ⁇ 2°, ⁇ 1°, ⁇ 0.5°, ⁇ 0.1°, or ⁇ 0.05°.
  • Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 ⁇ m, no greater than 2 ⁇ m, no greater than 1 ⁇ m, or no greater than 0.5 ⁇ m.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Optical Integrated Circuits (AREA)

Abstract

A semiconductor device includes a substrate, a passivation layer and an optical element. The substrate includes a surface and a sidewall. The passivation layer is disposed on the surface of the substrate. The optical element is disposed in the substrate and exposed from the sidewall of the substrate. The sidewall of the substrate is inclined towards the surface of the substrate at an angle of approximately 87 degrees to approximately 89 degrees.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of and priority to U.S. Provisional Application No. 62/338,993, filed 19 May 2016, and U.S. Provisional Application No. 62/341,555, filed 25 May 2016, the contents of which are incorporated herein by reference in their entireties.
BACKGROUND 1. Technical Field
The present disclosure relates to a semiconductor device package. In particular, the present disclosure relates to a semiconductor device package including optical devices.
2. Description of the Related Art
In comparable optical devices, a waveguide can be used to guide light from a light emitter to an optical sensor in a semiconductor device package. However, distance between a light emitter and an optical sensor may result in lower optical transmission efficiency and lower accuracy of a coupling facet.
A comparable manufacturing process includes singulating or cutting a wafer including a waveguide into a plurality of optical devices by using a blade saw. However, an uneven sidewall of each optical device may degrade quality of light transmission when integrating or coupling the optical device to an optical fiber or laser diode. One approach to address the above problem may be to polish the sidewall of the optical devices and to subsequently coat an anti-reflection film on the sidewall. However, cost of a manufacturing process would increase and the process would become more complicated.
SUMMARY
In some embodiments, a semiconductor device includes a substrate, a passivation layer and an optical element. The substrate includes a surface and a sidewall. The passivation layer is disposed on the surface of the substrate. The optical element is disposed in the substrate and exposed from the sidewall of the substrate. The sidewall of the substrate is inclined towards the surface of the substrate at an angle of approximately 87 degrees to approximately 89 degrees.
In some embodiments, a semiconductor device package includes a first optical device and a second optical device. The first optical device includes a first substrate including a first surface and a first sidewall, a passivation layer on the first surface of the first substrate, and a first optical element in the first substrate and exposed from the first sidewall of the first substrate, the first optical element comprising a sidewall. The second optical device includes a second substrate including a second sidewall, a second optical element in the second substrate and exposed from the second sidewall of the second substrate, the second optical element comprising a sidewall. A lateral distance between the first sidewall of the first optical element of the first optical device and the second sidewall of the second optical element of the second optical device is less than about 2 micrometers (μm).
In some embodiments, a semiconductor wafer includes a semiconductor body, a passivation layer and a trench. The semiconductor body includes a surface and a plurality of optical devices, wherein each of the plurality of optical devices includes a plurality of edges. The passivation layer is disposed on each of the optical devices. The trench corresponds to each of the plurality of optical devices and is recessed from the first surface of the semiconductor body, and the trench is adjacent to one of the plurality of edges of each of the optical devices.
In some embodiments, a semiconductor device includes a substrate, a passivation layer and an optical element. The substrate includes a surface and a sidewall. The passivation layer is disposed on the surface of the substrate. The optical element is disposed in the substrate and is exposed from the sidewall of the substrate. The passivation layer includes a curved sidewall adjacent to the sidewall of the substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view of a semiconductor device package in accordance with some embodiments of the present disclosure.
FIG. 2 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure.
FIG. 3 is an example of an inclined structure in accordance with some embodiments of the present disclosure.
FIG. 4A, FIG. 4B and FIG. 4C illustrate a method of manufacturing a semiconductor device in accordance with some embodiments of the present disclosure.
FIG. 5A and FIG. 5B are side-sectional views of a semiconductor wafer in accordance with some embodiments of the present disclosure.
FIG. 5C and FIG. 5D are side-sectional views of the semiconductor device shown in FIG. 5B in accordance with some embodiments of the present disclosure.
FIG. 6A and FIG. 6B are side-sectional views of a semiconductor device package in accordance with some embodiments of the present disclosure.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. Embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.
DETAILED DESCRIPTION
Described in the present disclosure are optical devices according to some embodiments having improved quality of light transmission. Moreover, the optical devices according to some embodiments may reduce the large distances between a light emitter and an optical sensor that lower optical transmission efficiency and lower accuracy of a coupling facet.
Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.
FIG. 1 is a perspective view of a semiconductor device package 1 in accordance with some embodiments of the present disclosure. The semiconductor device package 1 includes two optical devices 22 and 24. The optical device 22 includes a substrate (or first substrate) 10, an optical element (or first optical element) 30, a passivation layer 16 and a semiconductor oxide layer 18. The substrate 10 may include, for example, silicon (Si) or one or more other suitable materials. The passivation layer 16 may include, for example, silicon dioxide (SiO2), or one or more other suitable materials. The semiconductor oxide layer 18 may include, for example, silicon oxide (SiOx), or one or more other suitable materials. The optical element 30 may be a waveguide. The optical element 30 may include, for example, Si or one or more other suitable materials. A thickness of the optical element 30 may be less than about 10 micrometers (μm).
The optical device 24 includes a substrate (or second substrate) 20 and an optical element (or second optical element) 40. The substrate 20 may include, for example, Si or one or more other suitable materials. The optical element 40 may be an optical fiber, laser diode or other suitable element. The laser diode or optical fiber of the optical element 40 may be optically coupled to the optical element 30 (e.g., waveguide). The optical device 24 may be suspended on the substrate 20. The optical device 24 may be latched on the substrate 20.
The substrate 10 includes a surface (or first surface) 101 and a sidewall (or first sidewall) 103. The passivation layer 16 is disposed on the surface 101 of the substrate 10. The optical element 30 includes a sidewall 303. The sidewall 303 of the optical element 30 is continuous with and substantially coplanar with the sidewall 103 of the substrate 10. A shape of an opening of the optical element 30 at the sidewall 303 is a square or rectangle. A roughness of the sidewall 103 of the substrate 10 may be less than about 1.5 such as about 1.4 μm or less, about 1.2 μm or less, or about 1 μm or less in terms of root-mean-square surface roughness.
The semiconductor oxide layer 18 includes a sidewall 503. The substrate 20 includes a sidewall (or second sidewall) 203. The optical element 40 includes a sidewall 403. A distance D1 is defined between the sidewall 303 of the optical element 30 and the sidewall 403 of the optical element 40. The distance D1 between the exposed portion of the first optical device 22 and the exposed portion of the second optical device 24 may be less than about 2 such as about 1.9 μm or less, about 1.8 μm or less, or about 1.7 μm or less.
FIG. 2 is a cross-sectional view of a semiconductor device (e.g., optical device 22) in accordance with some embodiments of the present disclosure. The optical element 30 of the optical device 22 is disposed in the substrate 10 and exposed from the first sidewall 103. In some embodiments, the first sidewall 103 is inclined or curved towards the first surface 101 at an angle of less than 90 degrees or approximately 87 degrees to approximately 89 degrees. In some embodiments, the passivation layer 16 includes a curved sidewall adjacent to the first sidewall 103. A thickness of the substrate 10 (e.g., a particular layer of the substrate 10) may be greater than about 400 μm and a thickness of the passivation layer 16 may be about 10 μm to about 15 μm.
FIG. 3 is an example of an inclined structure in accordance with some embodiments of the present disclosure. As shown in FIG. 3, the angle of the upper corner of the inclined structure may be approximately 87 degrees to approximately 89 degrees.
FIGS. 4A, 4B and 4C illustrate a method of manufacturing a semiconductor device (e.g., optical device 22) in accordance with some embodiments of the present disclosure. Referring to FIG. 4A, a semiconductor body (e.g., substrate) 10 is provided. The semiconductor body 10 may include, for example, Si or one or more other suitable materials. The patterned passivation layer 16 is formed on the first surface 101 of the semiconductor body 10. The optical element 30 and the semiconductor oxide layer 18 are formed in the semiconductor body 10. The semiconductor oxide layer 18 may include, for example, SiOx or one or more other suitable materials. The optical element 30 may include, for example, Si or one or more other suitable materials. A warpage of the semiconductor body 10 may be about 5 μm to about 10 μm.
Referring to FIG. 4B, the semiconductor body 10 and a portion of the passivation layer 16 are etched (e.g., using Deep Reactive Ion Etching (DRIE)). After etching, the passivation layer 16 includes a curved sidewall adjacent to the first sidewall 103. A trench 52 is recessed from the first surface 103 of the semiconductor body 10. The first surface 103 is exposed within the trench 52. Next, a backside grinding 92 is performed to reduce a thickness of the semiconductor body 10.
Referring to FIG. 4C, then, a portion of the semiconductor body 10 is removed from the bottom surface of the semiconductor body 10, such as by backside grinding 92, until the trench 52 penetrates fully through the semiconductor body 10 such that the optical devices 22 are singulated to form individual optical device 22 as shown in FIG. 1 and FIG. 2. The optical devices 22 are separated using the backside grinding. In some embodiments, the backside grinding may be performed by using a rotatable polishing pad. The first surface 101 of the semiconductor body 10 is partially covered by the passivation layer 16 and the semiconductor body 10 thus includes a protruding portion not covered by the passivation layer 16.
Using DRIE in the manufacturing process may reduce steps of the manufacturing process and accordingly the roughness of the first sidewall 103 of the substrate 10 may be less than about 1.5 μm. In addition, using this manufacturing process, the distance D1 between the sidewall 303 of the optical element 30 and the sidewall 403 of the optical element 40 may be reduced to be less than about 2 μm.
FIGS. 5A and 5B are side-sectional views of a semiconductor wafer 2 in accordance with some embodiments of the present disclosure. Referring to FIG. 5A, the semiconductor wafer 2 is shown prior to singulation. The semiconductor wafer 2 includes a surface 501 and a plurality of optical devices 22. Each of the plurality of optical devices 22 includes a plurality of edges. A plurality of passivation layers 16 are disposed on each of the optical devices 22. The passivation layer 16 includes the curved sidewall.
Referring to FIG. 5B, the trench 52 is recessed from a first surface 501 of a semiconductor body 50. An opening 220 of the trench 52 includes a plurality of edges, and one of the plurality of edges of the opening 220 has a length L1. One of the edges of the optical devices 22 has a length L2. The trench 52 is adjacent to one of the plurality of edges of each of the optical devices 22. The trench 52 passes through or penetrates through the semiconductor body 50. The length L1 of the opening 220 of the trench 52 may be equal to or less than the length L2 of the edge of the optical devices 22. The optical devices 22 are separated after the backside grinding 92 is performed (e.g., by using a rotatable polishing pad).
FIGS. 5C and 5D are side-sectional views of a semiconductor device (e.g., optical device 22) of FIG. 5B in accordance with some embodiments of the present disclosure. Referring to FIG. 5C, the optical devices 22 are separated by the backside grinding 92. The optical elements 30 are exposed by the first sidewall 103. The edges of the substrate 10 can be used to support or engage other suitable optical elements. Referring to FIG. 5D, the opening 220 of the substrate 10 can be used to support or engage other suitable inserted optical elements.
FIGS. 6A and 6B are side-sectional views of semiconductor device packages 3 and 4, respectively, in accordance with some embodiments of the present disclosure. Referring to FIG. 6A, the semiconductor device package 3 includes optical devices 22 and 24. The optical element 30 (e.g., waveguide) is precisely aligned with the optical element 40 by inserting the optical device 24 into the opening 220. Referring to FIG. 6B, the semiconductor device package 4 includes optical devices 22 and 24. The optical element 30 (e.g., waveguide) is precisely aligned with the optical element 40 by engaging the optical device 24.
As used herein, the terms “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For another example, a first angle may be approximately the same as a second angle if a difference between the first angle and the second angle is less than or equal to ±10°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°.
Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.

Claims (26)

What is claimed is:
1. A semiconductor device comprising:
a substrate including a surface and a sidewall;
a passivation layer on the surface; and
an optical element in the substrate and exposed from the sidewall of the substrate,
wherein the sidewall of the substrate is inclined such that the sidewall of the substrate and the surface of the substrate form an internal angle of approximately 87 degrees to approximately 89 degrees, and
wherein the passivation layer comprises a curved sidewall adjacent to the sidewall of the substrate.
2. The semiconductor device of claim 1, wherein a thickness of the substrate is greater than about 400 micrometers (μm) and a thickness of the passivation layer is about 10 μm to about 15 μm.
3. The semiconductor device of claim 1, wherein the optical element further comprises a sidewall continuous with the sidewall of the substrate.
4. The semiconductor device of claim 1, wherein the optical element further comprises a sidewall substantially coplanar with the sidewall of the substrate.
5. The semiconductor device of claim 1, wherein the substrate further includes a protruding portion not covered by the passivation layer.
6. The semiconductor device of claim 1, wherein the optical element comprises a waveguide.
7. The semiconductor device of claim 1, wherein a roughness of the sidewall of the substrate is less than about 1.5 μm.
8. A semiconductor device package, comprising:
a first optical device; and
a second optical device,
wherein the first optical device comprises:
a first substrate including a first surface and a first sidewall;
a passivation layer on the first surface of the first substrate; and
a first optical element in the first substrate and exposed from the first sidewall of the first substrate, the first optical element comprising a sidewall,
wherein the second optical device comprises:
a second substrate including a second sidewall;
a second optical element in the second substrate and exposed from the second sidewall of the second substrate, the second optical element comprising a sidewall, and
wherein a lateral distance between the first sidewall of the first optical element of the first optical device and the second sidewall of the second optical element of the second optical device is less than about 2 micrometers (μm).
9. The semiconductor device package of claim 8, wherein the first sidewall of the first substrate is inclined such that the sidewall of the first substrate and the first surface of the first substrate form an internal angle of approximately 87 degrees to approximately 89 degrees.
10. The semiconductor device package of claim 8, wherein the passivation layer comprises a curved sidewall adjacent to the first sidewall of the first substrate.
11. The semiconductor device package of claim 8, wherein the first optical element of the first optical device comprises a waveguide.
12. The semiconductor device package of claim 8, wherein a thickness of the first optical element of the first optical device is less than about 10 μm.
13. The semiconductor device package of claim 8, wherein a roughness of the first sidewall of the first substrate of the first optical device is less than about 1.5 μm.
14. The semiconductor device package of claim 8, wherein a distance between an exposed portion of the first optical device and an exposed portion of the second optical device is less than about 2 μm.
15. The semiconductor device package of claim 8, wherein the second optical device includes a laser diode or an optical fiber optically coupled to the first optical element the first optical device.
16. The semiconductor device package of claim 8, wherein the second optical device is suspended on the second substrate.
17. The semiconductor device package of claim 8, wherein the second optical device is latched on the second substrate.
18. A semiconductor wafer comprising:
a semiconductor body including a surface and a plurality of optical devices, wherein each of the plurality of optical devices includes a plurality of edges;
a passivation layer disposed on each of the optical devices and on the surface of the semiconductor body; and
a trench corresponding to each of the plurality of optical devices and recessed from the first surface of the semiconductor body,
wherein the trench is adjacent to one of the plurality of edges of each of the optical devices.
19. The semiconductor wafer of claim 18, wherein the trench passes through the semiconductor body.
20. The semiconductor wafer of claim 18, wherein the trench penetrates through the semiconductor body.
21. The semiconductor wafer of claim 18, wherein the passivation layer comprises a curved sidewall.
22. The semiconductor wafer of claim 18, wherein a sidewall of each of the optical devices is exposed within the trench.
23. The semiconductor wafer of claim 18, wherein a warpage of the semiconductor body is about 5 μm to about 10 μm.
24. A semiconductor device, comprising:
a substrate including a surface and a sidewall;
a passivation layer on the surface; and
an optical element in the substrate and exposed from the sidewall,
wherein the passivation layer comprises a curved sidewall adjacent to the sidewall of the substrate.
25. The semiconductor device of claim 24, wherein the optical element further comprises a sidewall continuous with the sidewall of the substrate.
26. The semiconductor device of claim 24, wherein a roughness of the sidewall of the substrate is less than about 1.5 μm.
US15/406,509 2016-05-19 2017-01-13 Semiconductor device packages Active US9857532B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/406,509 US9857532B2 (en) 2016-05-19 2017-01-13 Semiconductor device packages
CN201710128162.7A CN107403766B (en) 2016-05-19 2017-03-06 Semiconductor packages

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662338993P 2016-05-19 2016-05-19
US201662341555P 2016-05-25 2016-05-25
US15/406,509 US9857532B2 (en) 2016-05-19 2017-01-13 Semiconductor device packages

Publications (2)

Publication Number Publication Date
US20170336561A1 US20170336561A1 (en) 2017-11-23
US9857532B2 true US9857532B2 (en) 2018-01-02

Family

ID=60330062

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/406,509 Active US9857532B2 (en) 2016-05-19 2017-01-13 Semiconductor device packages

Country Status (2)

Country Link
US (1) US9857532B2 (en)
CN (1) CN107403766B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11835757B2 (en) 2021-10-01 2023-12-05 Advanced Semiconductor Engineering, Inc. Optoelectronic package and method for manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10930627B2 (en) * 2018-12-28 2021-02-23 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10985149B2 (en) * 2019-01-15 2021-04-20 Omnivision Technologies, Inc Semiconductor device package and method of manufacturing the same

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331382B1 (en) * 1998-03-06 2001-12-18 Telefonaktiebolaget Lm Ericsson (Publ) Method of fabricating mirrors in polymer waveguides
US20130320567A1 (en) * 2012-06-05 2013-12-05 Oracle International Corporation Batch process for three-dimensional integration
US20130330035A1 (en) * 2012-06-07 2013-12-12 Samsung Electronics Co., Ltd. Semiconductor Package and Semiconductor Device Including the Same
US8798410B2 (en) * 2012-06-12 2014-08-05 Laxense Inc. Optical system with integrated photodetector using a self-aligned double U-groove structure
US20150036970A1 (en) * 2013-08-01 2015-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing
US8975672B2 (en) * 2011-11-09 2015-03-10 United Microelectronics Corp. Metal oxide semiconductor transistor and manufacturing method thereof
US20150234137A1 (en) * 2012-02-23 2015-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Optical bench on substrate and method of making the same
US9323014B2 (en) * 2012-05-28 2016-04-26 Mellanox Technologies Ltd. High-speed optical module with flexible printed circuit board
US9482831B2 (en) * 2012-12-28 2016-11-01 Wuhan Telecommunication Devices Co., Ltd. Silica-on-silicon-based hybrid integrated optoelectronic chip and manufacturing method therefor
US9484482B2 (en) * 2014-06-26 2016-11-01 International Business Machines Corporation Efficient optical (light) coupling
US9543208B2 (en) * 2014-02-24 2017-01-10 Infineon Technologies Ag Method of singulating semiconductor devices using isolation trenches
US9606231B2 (en) * 2012-08-23 2017-03-28 Osram Opto Semiconductors Gmbh Optoelectronic apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2334344B (en) * 1998-05-01 2000-07-12 Bookham Technology Ltd Coupling optical fibre to waveguide
JP2006253391A (en) * 2005-03-10 2006-09-21 Sharp Corp Semiconductor laser apparatus
CN101082687A (en) * 2007-07-09 2007-12-05 陈铭义 Optical waveguides on piece total compatible with standard CMOS process and method for making same
US8637967B2 (en) * 2010-11-15 2014-01-28 Infineon Technologies Ag Method for fabricating a semiconductor chip and semiconductor chip
CN102956652A (en) * 2011-08-19 2013-03-06 深圳光启高等理工研究院 Photoelectric sensor
CN203855403U (en) * 2014-01-21 2014-10-01 华进半导体封装先导技术研发中心有限公司 Silicon-based photonic interconnection device

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331382B1 (en) * 1998-03-06 2001-12-18 Telefonaktiebolaget Lm Ericsson (Publ) Method of fabricating mirrors in polymer waveguides
US8975672B2 (en) * 2011-11-09 2015-03-10 United Microelectronics Corp. Metal oxide semiconductor transistor and manufacturing method thereof
US20150234137A1 (en) * 2012-02-23 2015-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Optical bench on substrate and method of making the same
US9323014B2 (en) * 2012-05-28 2016-04-26 Mellanox Technologies Ltd. High-speed optical module with flexible printed circuit board
US20130320567A1 (en) * 2012-06-05 2013-12-05 Oracle International Corporation Batch process for three-dimensional integration
US20130330035A1 (en) * 2012-06-07 2013-12-12 Samsung Electronics Co., Ltd. Semiconductor Package and Semiconductor Device Including the Same
US8798410B2 (en) * 2012-06-12 2014-08-05 Laxense Inc. Optical system with integrated photodetector using a self-aligned double U-groove structure
US9606231B2 (en) * 2012-08-23 2017-03-28 Osram Opto Semiconductors Gmbh Optoelectronic apparatus
US9482831B2 (en) * 2012-12-28 2016-11-01 Wuhan Telecommunication Devices Co., Ltd. Silica-on-silicon-based hybrid integrated optoelectronic chip and manufacturing method therefor
US20150036970A1 (en) * 2013-08-01 2015-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing
US9543208B2 (en) * 2014-02-24 2017-01-10 Infineon Technologies Ag Method of singulating semiconductor devices using isolation trenches
US9484482B2 (en) * 2014-06-26 2016-11-01 International Business Machines Corporation Efficient optical (light) coupling

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11835757B2 (en) 2021-10-01 2023-12-05 Advanced Semiconductor Engineering, Inc. Optoelectronic package and method for manufacturing the same

Also Published As

Publication number Publication date
CN107403766B (en) 2019-08-30
US20170336561A1 (en) 2017-11-23
CN107403766A (en) 2017-11-28

Similar Documents

Publication Publication Date Title
US9589812B2 (en) Fabrication method of semiconductor piece
US9857532B2 (en) Semiconductor device packages
US11177306B2 (en) Support structure for integrated circuitry
US10197733B2 (en) Edge coupling device fabrication
US8765578B2 (en) Edge protection of bonded wafers during wafer thinning
US9324682B2 (en) Method and system for height registration during chip bonding
US9329348B2 (en) Arrangement of photonic chip and optical adaptor for coupling optical signals
TWI695970B (en) Optical device, electrical device and passive optical component
US20200185451A1 (en) Semiconductor package with chamfered corners and related methods
US10615568B2 (en) Antireflection structure for integrated laser diode/photonic chip interface
CN105390579B (en) Semiconductor light-emitting elements chip, semiconductor light-emitting elements and its manufacturing method
US10325808B2 (en) Crack prevent and stop for thin glass substrates
US10106399B1 (en) Multi-layer single chip MEMS WLCSP fabrication
US11215762B2 (en) Optical device package and method for manufacturing the same
US9105644B2 (en) Apparatus and method for forming alignment features for back side processing of a wafer
US20220043205A1 (en) An ultra-thin integrated and manufacture of the same
US20120241916A1 (en) Wafer edge conditioning for thinned wafers
CN103035515B (en) The fill method of groove
US9165831B2 (en) Dice before grind with backside metal
JP2016004920A (en) Semiconductor device manufacturing method and structure
US20230296994A1 (en) Back Side to Front Side Alignment on a Semiconductor Wafer with Special Structures
US6881600B2 (en) Etching in combination with other processing techniques to facilitate alignment of a die in a system and structures formed thereby
US10770306B2 (en) Method of etching a cavity in a stack of layers
US20160093544A1 (en) Packaging of Semiconductor Devices
WO2019162062A1 (en) Optical chip for coupling light and fabrication method

Legal Events

Date Code Title Description
AS Assignment

Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHIN, YI-MIN;ZHANG, JIA-HAO;CHEN, CHI-HAN;AND OTHERS;REEL/FRAME:041001/0802

Effective date: 20170110

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4