US9742426B2 - Signal transfer function equalization in multi-stage delta-sigma analog-to-digital converters - Google Patents

Signal transfer function equalization in multi-stage delta-sigma analog-to-digital converters Download PDF

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US9742426B2
US9742426B2 US15/359,240 US201615359240A US9742426B2 US 9742426 B2 US9742426 B2 US 9742426B2 US 201615359240 A US201615359240 A US 201615359240A US 9742426 B2 US9742426 B2 US 9742426B2
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stage
transfer function
digital
response
filter
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US20170170841A1 (en
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Jose Barreiro Silva
Donald W. Paterson
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Analog Devices Inc
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Priority to JP2016242460A priority patent/JP6542185B2/ja
Priority to CN201611149082.1A priority patent/CN106888023B/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/346—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by suppressing active signals at predetermined times, e.g. muting, using non-overlapping clock phases
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/358—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0248—Filters characterised by a particular frequency response or filtering method
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0294—Variable filters; Programmable filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step

Definitions

  • the present disclosure relates generally to analog-to-digital converters (ADCs) and, more particularly, to signal transfer function equalization in multi-stage delta-sigma analog-to-digital converters (MASH ADCs).
  • ADCs analog-to-digital converters
  • MASH ADCs signal transfer function equalization in multi-stage delta-sigma analog-to-digital converters
  • an analog input signal is converted to a digital output signal (e.g., for further digital signal processing).
  • a digital output signal e.g., for further digital signal processing.
  • electronics are provided with one or more sensors to make measurements, and these sensors may generate an analog signal.
  • the analog signal would then be provided to an analog-to-digital converter (ADC) as input to generate a digital output signal for further processing.
  • ADC analog-to-digital converter
  • an antenna generates an analog signal based on the electromagnetic waves carrying information/signals in the air.
  • the analog signal generated by the antenna is then provided as input to an ADC to generate a digital output signal for further processing.
  • ADCs can be found in many places such as broadband communication systems, audio systems, receiver systems, etc.
  • ADCs can translate analog electrical signals representing real-world phenomena, e.g., light, sound, temperature or pressure for data processing purposes.
  • ADCs are used in a broad range of applications including Communications, Energy, Healthcare, Instrumentation and Measurement, Motor and Power Control, Industrial Automation and Aerospace/Defense. Designing an ADC is a non-trivial task because each application may have different needs in speed, performance, power, cost and size. As the applications needing ADCs grow, the need for accurate and reliable conversion performance also grows.
  • FIG. 1 is an illustrative system diagram of a delta sigma analog-to-digital converter (DS ADC);
  • FIG. 2 shows an exemplary two-stage MASH ADC with digital quantization noise cancellation
  • FIG. 3 is a wireless receiver system having a separate equalizer at the output of the ADC
  • FIG. 4A shows an exemplary two-stage MASH ADC with digital quantization noise cancellation
  • FIG. 4B shows an exemplary two-stage MASH ADC with digital quantization noise cancellation and equalization, according to some embodiments of the disclosure.
  • FIG. 5 shows an exemplary method for generating digital noise quantization cancellation and equalization filters, according to some embodiments of the disclosure
  • FIG. 6 shows exemplary DSTF2 and DNTF1 examples, according to some embodiments of the disclosures
  • FIG. 7 shows desired STF and the equalizer response that achieves the desired STF, according to some embodiments of the disclosure
  • FIG. 8 shows exemplary programmable filter responses, according to some embodiments of the disclosure.
  • FIG. 9 shows an exemplary method for digital noise quantization cancellation and equalization, according to some embodiments of the disclosure.
  • FIGS. 10A-C show methods for digital noise quantization cancellation and equalization, according to some embodiments of the disclosure.
  • FIG. 11 shows an exemplary method for digital noise quantization cancellation and equalization, according to some embodiments of the disclosure.
  • the effective Signal Transfer Function (STF) of a Multi-stAge noise SHaping (MASH) ADC can be modified by leveraging available digital filtering hardware necessary for quantization noise cancellation.
  • the modification can involves adding calculations in the software previously provided for computing digital quantization noise cancellation filter coefficients, where the calculations are added to take into account equalization as well.
  • the signal transfer function can be modified to meet ADC or system-level signal-chain specifications without additional equalization hardware. The method is especially attractive for high-speed applications where magnitude and phase responses are more challenging to meet.
  • ADCs are electronic devices that convert a continuous physical quantity carried by an analog signal to a digital number that represents the quantity's amplitude (or to a digital signal carrying that digital number).
  • the conversion involves quantization of the analog input signal, so it would introduce a small amount of error. Typically the quantization occurs through periodic sampling of the analog input signal.
  • the result is a sequence of digital values (i.e., a digital signal) that has converted a continuous-time and continuous-amplitude analog input signal to a discrete-time and discrete-amplitude digital signal.
  • An ADC can be defined by the following application requirements: its bandwidth (the range of frequencies of analog signals it can properly convert to a digital signal) and its resolution (the number of discrete levels the maximum analog signal can be divided into and represented in the digital signal).
  • An ADC also has various specifications for quantifying ADC dynamic performance, including signal-to-noise-and-distortion ratio (SINAD), effective number of bits (ENOB), signal to noise ratio (SNR), total harmonic distortion (THD), total harmonic distortion plus noise (THD+N), and spurious free dynamic range (SFDR).
  • SINAD signal-to-noise-and-distortion ratio
  • ENOB effective number of bits
  • SNR signal to noise ratio
  • TDD total harmonic distortion
  • TTD+N total harmonic distortion plus noise
  • SFDR spurious free dynamic range
  • FIG. 1 is an illustrative system diagram of a delta sigma analog-to-digital converter (DS ADC), or sometimes referred herein as a delta sigma modulator.
  • the DS ADC includes loop filter 102 , quantizer 104 , and feedback digital-to-analog converter (DAC) 106 (i.e., a DAC in the feedback path of the DS ADC).
  • DAC digital-to-analog converter
  • a DS ADC usually provides the advantage of being able to convert an analog input signal to a digital signal with high resolution at low cost.
  • a DS ADC encodes an analog signal u using a DS modulator.
  • Quantizer 104 can be used for this purpose, employing, e.g., a low resolution ADC, as a 1-bit ADC, Flash ADC, Flash quantizer, etc. Then, if applicable, the DS ADC can apply a digital filter (not shown) to the output of the DS modulator (i.e., Quantizer 104 ) to form a higher-resolution digital output.
  • Loop filter 102 having one or more integrators, may be included to provide error feedback for the DS ADC and to help shape the noise from the quantizer 104 out of baseband to higher frequencies.
  • the error is usually generated by taking the difference between the original analog input signal u and a reconstructed version of the original analog input signal generated using the feedback DAC 106 (where digitized signal v is converted back into an analog signal).
  • One key characteristic of a DS ADC is its ability to push the quantization noise q (from quantizer 104 ) to higher frequencies, also referred to as noise shaping.
  • the amount of noise shaping depends on the order of the loop filter 102 .
  • DS ADCs are generally able to achieve high resolution analog-to-digital conversion. Due to its popularity, many variations on the DS ADC and structures employing the DS ADC have been proposed.
  • DS ADCs have been adapted to meet power concerns, while some other DS ADCs have been adapted to reduce complexity.
  • DS ADCs have been adapted to meet precision concerns by providing increased control over errors and/or noise.
  • a higher order DS modulator may be used, i.e., more integrators and feedback paths are used in the loop filter for shaping even more of the quantization noise to high frequencies.
  • Delta-sigma ADCs e.g., FIG. 1
  • High-order noise shaping and multi-bit implementations allow for more aggressive tradeoffs, but at the risk of making the ADC unstable.
  • MASH ADCs having multiple DS ADCs have been introduced.
  • MASH ADCs has a plurality of stages, e.g., a plurality of DS ADCs.
  • a MASH ADC can have two stages, e.g., a front end and a back end. Each of the stages receive a respective analog input and outputs a respective digital output. In some cases, the stages receive the same analog output. In some cases, the stages receive different analog inputs.
  • some MASH ADCs have a front-end and a back-end where inputs to each modulator differ.
  • Some MASH ADCs have stages where the implementation of the stage may differ.
  • MASH ADCs address the issue of unstability by relying on the cascading of individually stable delta-sigma modulators. However, MASH ADCs rely on the cancellation of quantization noise, which requires accurate matching between analog and digital transfer functions.
  • MASH ADCs can include a plurality of stages (cascaded delta sigma modulators) for digitizing the signal and errors of the system in order to meet design requirements related to bandwidth, resolution, and the signal to noise ratios.
  • stages cascaded delta sigma modulators
  • One advantage of MASH ADCs is that the design cascades stable low-order loops while achieving the good performance of (potentially unstable) higher-order loops.
  • the first stage generates, from the analog input signal, a digital output signal using a first ADC.
  • the input to the quantizer in the first stage (or equivalently, the output from the first loop filter/integrator) can be subtracted from the first DAC analog output to yield the first stage quantization noise.
  • the first stage quantization noise is digitized by the second stage.
  • the first stage generates an analog signal representing its quantization noise
  • the second stage quantizes the quantization noise of the first stage using a second ADC.
  • the multi-stage approach allows the quantization noise to be reduced and thus allows the MASH ADC to achieve higher performance. If more stages are used, the input to the quantizer in the second stage (or equivalently, the output from the second loop filter or integrator) can be subtracted from the second DAC analog output to yield the second stage quantization noise which can be in turn quantized by a third stage. Input to the quantizer or output from the loop filter/integrator may be delayed by a delay element prior to the subtraction.
  • the delay element can be provided match possible transconductance and group delay of a signal path used for generating the DAC analog output from the analog signal at the input of the delay element.
  • the respective outputs are combined. Effectively, the result is that the quantization noise of the first stage is suppressed by the second stage, and the quantization noise from the second stage is suppressed by the third stage (yielding the same suppression of noise as a single third-order loop, when three cascaded first-order loops are used).
  • FIG. 2 shows (a high level diagram of) an exemplary two-stage MASH ADC with digital quantization noise cancellation, which can provide cancellation of quantization noise. While the example shows two stages, it is envisioned by the disclosure that digital quantization noise cancellation can be applied to MASH ADCs with more than two stages.
  • Two ADCs, ADC1 202 , and ADC2 204 are arranged in cascade, representing the ADCs in two separate stages.
  • Each ADC has a signal transfer function (STF), STF 1 and STF 2 , from its input to its output.
  • STF signal transfer function
  • STF 1 and STF 2 The quantization noise q introduced by ADC1 202 appears at its output.
  • the quantization noise is shaped by a noise transfer function (NTF) of the same stage.
  • NTF noise transfer function
  • the quantization noise of the first stage q 1 is shaped by the noise transfer function of the first stage NTF 1 .
  • the quantization noise of the second stage q 2 is shaped by the noise transfer function of the second stage NTF 2 .
  • the transfer functions denoted by DSTF 2 206 and DNTF 1 208 correspond to digital implementations or estimations of their corresponding analog counterparts, NTF 2 and NTF 1 .
  • DSTF 2 and DNTF 1 are discrete-time transfer functions or equivalent discrete-time representations of continuous-time transfer functions.
  • the digital signals are combined, e.g., by summation node 210 (or some other suitable summing circuit or adder), to generate a final digital output v c .
  • the quantization noise from the first stage q 1 is cancelled out (no longer appears in the combined output v c ) by means of providing the digital filters DSTF 2 206 and DNTF 1 208 filtering the digital outputs v 1 , v 2 of the two-stages respectively.
  • the quantization noise from the second stage q 2 is shaped by the product of the two noise transfer functions (i.e., NTF 2 DNTF 1 ). If the analog and digital transfer functions do not match, the quantization noise from the first stage would appear at the combined output shaped by the (NTF 1 DSTF 2 -STF 2 DNTF 1 ) term. This undesirable effect is called quantization noise leakage, and can significantly degrade the achievable Signal-to-Noise Ratio (SNR) performance of the ADC.
  • SNR Signal-to-Noise Ratio
  • the estimation of transfer function impulse responses may be performed in the background by cross-correlating the ADC outputs with a known random signal injected at the quantizer of the first stage, or in the foreground by injecting known signals.
  • the programmable digital filters or cancellation filters can be implemented as programmable finite-impulse response (FIR) filters.
  • FIG. 3 is a wireless receiver system having a separate equalizer 302 downstream from the ADC 304 and digital filter 306 .
  • the wireless receiver system can include an antenna 308 for receiving a signal, a low noise amplifier (LNA) 310 ,
  • LNA low noise amplifier
  • the equalizer 302 compensates for distortions in the response introduced by the various signal processing blocks in the receiver signal path.
  • Equalizers may also be required in less complex applications, such as for receivers where ADCs therein do not have a flat signal transfer function or linear phase response. For example, a continuous-time delta-sigma modulator may show undesirable effects in its signal transfer function (STF) (e.g., peaking at some frequencies).
  • STF signal transfer function
  • An equalizer like equalizer 302 may be added as a separate component to equalize the signal transfer function.
  • an equalizer may be required in a system for correction of any signal transfer function magnitude or phase (and indirectly, group delay) response issues. If such a system includes a MASH ADC as part of its signal path (as the ADC), then the digital quantization noise cancellation described above may be extended to implement the equalization filter as well. The extension involves a software-based modification to the hardware digital filters are already included in the system to provide digital quantization noise cancellation. Accordingly, equalization can be implemented at no extra hardware cost. Even if a separate equalizer is provided in the signal chain, the requirements of the equalizer can be relaxed.
  • FIG. 4A shows an exemplary two-stage MASH ADC with digital quantization noise cancellation, similar to FIG. 2 .
  • the equalization filter EQF 412 is applied at the final output v C of the MASH ADC or downstream from the final output of the MASH ADC.
  • PSTF 408 is a programmable STF filter, implementing DSTF 2 .
  • PNTF 410 denotes a programmable NTF filter implementing DNTF 1 .
  • the programmable STF filter DSTF 2 aims to match the actual STF of the second stage; the programmable NTF filter DNTF 1 aims to match the actual noise transfer function of the first stage.
  • FIG. 4B shows an exemplary two-stage MASH ADC with combined digital noise cancellation and equalization, according to some embodiments of the disclosure.
  • the updated filter PSTF* 414 now implements both DSTF 2 and EQF (short for equalization filter), and the updated filter PNTF* 416 implements DNTF 1 and EQF.
  • Combining the digital quantization noise cancellation filters with the equalization filters is not trivial.
  • the updated digital filter has to be determined properly for each of the filters, e.g., DSTF 2 +EQF and DNTF 1 +EQF.
  • these filters are applied to v 1 and v 2 prior to the combination of the two filtered signals (shown as the addition/subtraction block) forming the final output of the MASH ADC v C .
  • This is in contrast to adding a separate additional equalization filter to the output of the MASH ADC v C (as illustrated by FIG. 4A ).
  • FIG. 5 shows an exemplary method for generating digital noise cancellation and equalization filters, according to some embodiments of the disclosure.
  • the method for combining the noise cancellation filter and equalization filter includes several parts. The method is described in relation to the two-stage MASH ADC shown in FIG. 4B , but other MASH ADCs having more stages can also leverage this method. Circuitry and systems illustrated in FIGS. 4B and 11 can implement the method illustrated by FIG. 5 .
  • the digital signal transfer function of the second stage DSTF 2 and the digital noise transfer function of the first stage DNTF 1 are determined.
  • the digital transfer functions estimates the actual transfer functions.
  • the desired ADC or full system signal transfer function is determined from target specifications (which can vary depending on the application).
  • target specifications which can vary depending on the application.
  • the full system STF can be expressed as an impulse response. If a linear phase response is desired, the STF can be determined to guarantee that property (e.g., its coefficients should be symmetric or antisymmetric).
  • an equalization filter response is determined.
  • the determined EQF would produce the desired full system STF.
  • the DSTF 2 is combined with EQF as a new digital filter and DNTF 1 is combined with EQF as another new digital filter.
  • the new digital filter coefficients are determined to ensure the desired full system STF is achieved while maintaining the noise cancellation function.
  • the determined digital filter coefficients are written to the two programmable digital filters PSTF* 414 and PNTF* 416 as seen in FIG. 4B , or PSTF* 1110 and PNTF* 1112 as seen in FIG. 11 .
  • the following example illustrates a possible methodology to calculate the response of the programmable digital filters PSTF* and PNTF* so that the programmable digital filters can achieve both quantization noise cancellation and signal path equalization.
  • the example is described with respect to the two-stage MASH ADC illustrated in FIG. 4B or the two-stage MASH ADC illustrated in FIG. 11 .
  • FIG. 6 shows exemplary DSTF 2 and DNTF 1 , according to some embodiments of the disclosures.
  • the impulse response of DSTF 2 is shown in plot 602 .
  • the frequency response of DSTF 2 is shown in plot 604 .
  • the impulse response of DNTF 1 is shown in plot 606 .
  • the frequency response of DNTF 1 is shown in plot 608 .
  • the STF 2 and NTF 1 transfer functions are assumed to ideal and thus the DSTF 2 and DNTF 1 matches the equations for the analog counterparts (Equation set (3)).
  • the desired full-system STF response STF(z) is determined to be 0.25+0.5z ⁇ 1 +0.25 z ⁇ 2 ( 504 of FIG. 5 ), which corresponds a well-behaved low-pass filter response.
  • the equalization filter response EQF that, e.g., when cascaded with STF 1 and DSTF 2 , achieving the desired full system STF response.
  • EQF(z) ⁇ STF1(z) ⁇ DSTF2(z) STF(z). Therefore, EQF(z) can be determined from the following equation ( 506 of FIG. 5 ):
  • FIG. 7 shows desired full system STF(z) and the equalizer response EQF(z) that achieves the desired STF, according to some embodiments of the disclosure.
  • the impulse response and frequency response of the desired full system STF are shown in plots 702 and 704 respectively.
  • the impulse response and frequency response of the EQF which achieves the full system STF response are shown in plots 706 and 708 respectively. Since the combined noise-cancellation and equalization responses are intended to be implemented as FIR filters, result of EQF(z) from Equation (4) can be converted to an impulse response. This can be done by calculating the behavior of the filter when an impulse is applied to its input.
  • the responses can be convolved together ( 508 of FIG. 5 ), in the time domain:
  • EQF ⁇ ( z ) STF ⁇ ( z ) STF ⁇ ⁇ 1 ⁇ ( z ) ⁇ DSTF ⁇ ⁇ 2 ⁇ ( z ) ( 4 )
  • Convolution combines the responses DSTF 2 and EQF, and also combines the responses DNTF 1 and EQF, so that new digital filters PSTF* and PNTF* seen in FIG. 4B can be determined, i.e., filter coefficients can be determined. Accordingly, with the new coefficients can be implemented by the programmable digital filters. Equivalently, the responses can be multiplied with each other in the frequency domain for the same result.
  • FIG. 8 shows exemplary programmable filter responses, according to some embodiments of the disclosure.
  • the impulse response and the frequency response of the digital filter PSTF* are shown in plots 802 and 804 respectively.
  • the impulse response and the frequency response of the digital filter PNTF* are shown in plots 806 and 808 respectively.
  • the new coefficients for the digital filters PSTF* and PNTF* can be written to the programmable filters ( 510 of FIG. 5 ). For this example, the number of taps in each of the programmable filters is 12 (this is N in Equations (5) and (6)). Using these programmable digital filters PSTF* and PNTF*, the resulting full system STF can match the desired STF exactly while maintaining the quantization noise cancellation function.
  • FIG. 9 shows an exemplary method for digital noise quantization cancellation and equalization for a system having MASH ADC, according to some embodiments of the disclosure. The method is similar to the method illustrated by FIG. 5 , and the scheme illustrated by FIGS. 6-8 . Circuitry and systems illustrated in FIGS. 4B and 11 can implement the method illustrated by FIG. 9 .
  • digital transfer function response of a particular stage in the MASH ADC is determined.
  • the digital transfer function of a particular stage is a digital signal transfer function estimating an actual signal transfer function of the particular stage.
  • the digital transfer function is the digital signal transfer function of the second stage DSTF 2 estimating the actual signal transfer function of the second stage STF 2 .
  • the digital transfer function of a particular stage is a digital noise transfer function estimating an actual noise transfer function of the particular stage.
  • the digital transfer function is a digital noise transfer function of the first stage DNTF 1 estimating the actual noise transfer function of the first stage NTF 1 .
  • the determination of digital transfer function responses may be performed in the background by cross-correlating the ADC outputs with a known random signal injected at the quantizer of the first stage, or in the foreground by injecting known signals.
  • an equalization filter response EQF is determined.
  • the equalization filter response corresponds to an equalization filter response that achieves a desired full system STF response.
  • the method can further include determining a desired signal transfer function response for the system having the MASH ADC, which can differ depending on the application. Determining the equalization filter response can include determining the equalization filter response based on the desired signal transfer function response (desired full system STF) and transfer functions in a signal path of the MASH ADC. This operation is illustrated by equation (4).
  • the digital transfer function response (from 902 ) and the equalization filter response EQF (from 904 ) are combined into a combined or merged digital filter.
  • the combination operation is illustrated by FIGS. 5-8 and their accompanying description.
  • the combined/merged digital filter can combine DSTF 2 and EQF.
  • the combined/merged digital filter can combine DNTF 1 and EQF.
  • combining the digital transfer function response and the equalization filter response may be a multiplication of the two responses to obtain the combined or merged digital filter.
  • combining the digital transfer function response and the equalization filter response comprises convolving the digital transfer function response with the equalization filter response to determine filter coefficients of the combined/merged digital filter (illustrated by equations (5) and (6)).
  • the results from 906 can include filter coefficients for programmable filters PSTF* and PNTF* of FIGS. 4B and 11 .
  • the method can further include writing filter coefficients of the combined digital filter to a programmable finite impulse response filter.
  • the combined digital filter filters a digital output of a different stage in the MASH ADC.
  • the combined digital filter filters the digital output prior to combining a result from the combined digital filter with other results from other stages of the MASH ADC.
  • the combined digital filter can be placed upstream from a summation node which combines results of the stages in the MASH ADC.
  • programmable filter PSTF* which combines DSTF 2 and EQF
  • programmable filter PNTF* which combines DNTF 1 and EQF
  • Outputs of the programmable filters are subsequently combined by summation node 210 or 1120 .
  • This filtering architecture is distinctly different from the one using a separate equalizer (downstream from the summation node) seen in FIGS. 3 and 4A .
  • FIGS. 10A-C show methods for digital noise quantization cancellation and equalization, according to some embodiments of the disclosure. The method is similar to the method illustrated by FIG. 5 , and the scheme illustrated by FIGS. 6-8 . Circuitry and systems illustrated in FIGS. 4B and 11 can implement the methods illustrated by FIGS. 10A-C .
  • the circuitry and systems would generally include a multi-stage noise shaping analog-to-digital converter (MASH ADC).
  • MASH ADC multi-stage noise shaping analog-to-digital converter
  • programmable means may filter a digital output of a particular stage of the MASH ADC.
  • Examples include programmable filters PSTF* and PNTF* of FIG. 4B and FIG. 11 , for filtering the digital output v 1 of the first stage and the digital output v 2 of the second stage respectively.
  • the programmable means may include a programmable digital filter, or programmable finite impulse response filter having a suitable number of taps.
  • coefficients of the programmable means are computed, e.g., by digital means, based on an estimated transfer function response of a further stage of the MASH ADC (e.g., DSTF 2 and DNTF 1 ) and a determined equalization filter response.
  • a further stage of the MASH ADC e.g., DSTF 2 and DNTF 1
  • FIG. 10B illustrates how to determine the estimated transfer function.
  • the further stage of MASH ADC is measured.
  • the estimated transfer function response which estimates an actual signal transfer function of the further stage of MASH ADC, is determined from the measurements. Process for measuring and estimating the responses are explained in relation to FIG. 2 .
  • the determination of digital transfer function responses may be performed in the background by cross-correlating the ADC outputs with a known random signal injected at the quantizer of the first stage, or in foreground by injecting known signals.
  • FIG. 10C illustrates details of 1004 .
  • Computing coefficients of the programmable filter can include 1010 , where the determined equalization filter response is determined from a desired signal transfer function response of the system and transfer functions in a signal path of the MASH ADC (illustrated by equation (4)), and 1012 , where the estimated transfer function response of the further stage of the MASH ADC and the determined equalization filter response are combined (illustrated by equations (5) and (6)).
  • FIG. 11 shows an exemplary system having digital noise quantization cancellation and equalization, according to some embodiments of the disclosure.
  • the system can implement the methods described herein.
  • the system includes MASH ADC 1102 having at least two stages, comprising at least a first stage (stage 1 1104 ) and a subsequent second stage (stage 2 1106 ).
  • Digital outputs of the stage 1 1104 and the stage 2 1106 are combined by a summation node 1120 (e.g., suitable summation circuitry, or adder).
  • a summation node 1120 e.g., suitable summation circuitry, or adder
  • the system further includes circuitry 1108 for estimating a transfer function response of a particular stage of the MASH ADC.
  • the particular stage is the subsequent second stage in the MASH ADC (stage 2 1106 )
  • the circuitry 1108 for estimating the transfer function response comprises circuitry for making measurements of the subsequent second stage of MASH ADC and determining a digital signal transfer function response (DSTF 2 ) as the estimated transfer function response, which estimates an actual signal transfer function of the subsequent second stage of MASH ADC (STF 2 ), from the measurements.
  • DSTF 2 digital signal transfer function response
  • the particular stage is the first stage in the MASH ADC (stage 1 1104 )
  • the circuitry 1108 for estimating the transfer function response comprises circuitry for making measurements of the first stage of MASH ADC and determining a digital noise transfer function response (DNTF 1 ) as the estimated transfer function response, which estimates an actual noise transfer function of the first stage of MASH ADC (NTF 1 ), from the measurements.
  • the circuitry 1108 can estimate of transfer function impulse responses in the background by cross-correlating the ADC outputs with a known random signal injected at the quantizer of the first stage, or in the foreground by injecting known signals.
  • the system further includes a programmable filter for filtering a further stage of the MASH ADC.
  • the programmable filter can include PSTF* 1110 .
  • the programmable filter can include PNTF* 1112 .
  • the programmable filter processes a digital output (e.g., v 1 , v 2 ) generated by the other stage prior to combining results from the stages of the MASH ADC for a final digital output (e.g., v c ).
  • the programmable filter can be a programmable finite impulse response filter.
  • the system further includes logic 1114 , e.g., digital processing logic or circuitry, for computing coefficients of the programmable filter based on the estimated transfer function response and a determined equalization filter response.
  • the logic for computing coefficients of the programmable filter can include logic for determining the determined equalization filter response from a desired signal transfer function response of the system and transfer functions in a signal path of the MASH ADC. This operation is illustrated by equation (4).
  • the logic for computing coefficients of the programmable filter can include combining the estimated transfer function response and the determined equalization filter response into a single digital filter. This operation is illustrated by equations (5) and (6).
  • Logic 1114 or the system can include logic for writing the computed coefficients to the programmable finite impulse response filter.
  • Example 1 is a method for digital quantization noise cancellation and equalization for a system having a multi-stage noise shaping analog-to-digital converter (MASH ADC), the method comprising: determining a digital transfer function response of a particular stage in the MASH ADC, determining an equalization filter response, combining the digital transfer function response and the equalization filter response into a combined digital filter.
  • MASH ADC multi-stage noise shaping analog-to-digital converter
  • any one of the above examples can further include filtering, by the combined digital filter, a digital output of a different stage in the MASH ADC.
  • any one of the above examples can further include the digital transfer function of the particular stage being a digital signal transfer function estimating an actual signal transfer function of the particular stage.
  • any one of the above examples can further include the digital transfer function of the particular stage being a digital noise transfer function estimating an actual noise transfer function of the particular stage.
  • Example 5 any one of the above examples can further include determining a desired signal transfer function response for the system having the MASH ADC.
  • any one of the above examples can further include determining the equalization filter response comprising determining the equalization filter response based on a desired signal transfer function response and transfer functions in a signal path of the MASH ADC.
  • any one of the above examples can further include combining the digital transfer function response and the equalization filter response comprising convolving the digital transfer function response with the equalization filter response in a time domain to determine filter coefficients of the combined digital filter.
  • any one of the above examples can further include writing filter coefficients of the combined digital filter to a programmable finite impulse response filter.
  • Example 9 is system having digital quantization noise cancellation and equalization, the system comprising: multi-stage noise shaping analog-to-digital converter (MASH ADC), circuitry for estimating a transfer function response of a particular stage of the MASH ADC, a programmable filter for filtering a further stage of the MASH ADC, and logic for computing coefficients of the programmable filter based on the estimated transfer function response and a determined equalization filter response.
  • MASH ADC multi-stage noise shaping analog-to-digital converter
  • any one of the above examples can further include the MASH ADC being a continuous-time MASH ADC.
  • any one of the above examples can further include the MASH ADC comprising at least a first stage and a subsequent second stage, the particular stage being the subsequent second stage in the MASH ADC, and the circuitry for estimating the transfer function response comprising circuitry for making measurements of the subsequent second stage of MASH ADC and determining a digital signal transfer function response as the estimated transfer function response, which estimates an actual signal transfer function of the subsequent second stage of MASH ADC, from the measurements.
  • any one of the above examples can further include the MASH ADC comprising at least a first stage and a subsequent second stage, the particular stage being the first stage in the MASH ADC, and the circuitry for estimating the transfer function response comprising circuitry for making measurements of the first stage of MASH ADC and determining a digital noise transfer function response as the estimated transfer function response, which estimates an actual noise transfer function of the first stage of MASH ADC, from the measurements.
  • any one of the above examples can further include the programmable filter processing a digital output generated by the other stage prior to combining results from the stages of the MASH ADC for a final digital output.
  • any one of the above examples can further include the logic for computing coefficients of the programmable filter comprising logic for determining the determined equalization filter response from a desired signal transfer function response of the system and transfer functions in a signal path of the MASH ADC.
  • any one of the above examples can further include the logic for computing coefficients of the programmable filter comprising combining the estimated transfer function response and the determined equalization filter response into a single digital filter.
  • any one of the above examples can further include the programmable filter being a programmable finite impulse response filter.
  • any one of the above examples can further include logic for writing the computed coefficients to the programmable finite impulse response filter.
  • Example 18 is an apparatus having digital quantization noise cancellation and equalization, the apparatus comprising: multi-stage noise shaping analog-to-digital converter (MASH ADC), programmable means for filtering a digital output of a particular stage of the MASH ADC, means for computing coefficients of the programmable means based on an estimated transfer function response of a further stage of the MASH ADC and a determined equalization filter response.
  • MASH ADC multi-stage noise shaping analog-to-digital converter
  • programmable means for filtering a digital output of a particular stage of the MASH ADC
  • means for computing coefficients of the programmable means based on an estimated transfer function response of a further stage of the MASH ADC and a determined equalization filter response.
  • any one of the above examples can further include means for measuring of the further stage of MASH ADC, means for determining the estimated transfer function response, which estimates an actual signal transfer function of the further stage of MASH ADC, from the measurements.
  • any one of the above examples can further include means for computing coefficients of the programmable filter comprising means for determining the determined equalization filter response from a desired signal transfer function response of the system and transfer functions in a signal path of the MASH ADC, and means for combining the estimated transfer function response of the further stage of the MASH ADC and the determined equalization filter response.
  • the digital quantization noise cancellation and equalization features can be used in a continuous-time (CT) multi-stage noise-shaping (MASH) ADC integrated circuit which achieves 69 dB of DR over a 465 MHz signal bandwidth with a combined power consumption of 930 mW from ⁇ 1.0V/1.8V supplies.
  • CT continuous-time
  • MASH multi-stage noise-shaping
  • the ADC integrated circuit can be implemented in 28 nm CMOS and achieves a peak SNDR of 64 dB, a small-signal noise-spectral density (NSD) of ⁇ 156 dBFS/Hz, and a figure-of-merit (FOM) of 156 dB over a signal bandwidth of 465 MHz.
  • NSD noise-spectral density
  • FOM figure-of-merit
  • OSR oversampling ratio
  • a 1-2 MASH architecture can be chosen to achieve aggressive noise-shaping at a low OSR.
  • the use of low-order sub-loops also contributes to the robustness of the overall ADC.
  • the first stage can be a first-order modulator to minimize the power of amplifiers for a given thermal noise requirement under a low OSR scenario.
  • the first stage can include an active-RC integrator, a 17-level flash ADC (FLASH1), a current-steering DAC (IDAC1), and a capacitive-DAC (CDAC1).
  • CDAC1 implements a fast direct-feedback (DFB) loop to compensate for the excess loop delay associated with the chosen FLASH-IDAC timing.
  • a differential 200 ⁇ R1U and a 625 uA IDAC1 LSB can set a 2V differential p-p input full-scale.
  • a dither block adds a 1-bit 1 ⁇ 2-LSB dither signal to the output of FLASH1.
  • the quantization residue of the first-stage is injected into the second-stage via R21 and current-steering DAC (IDAC2A).
  • R21 is implemented as an all-pass RC lattice filter to provide both accurate transconductance and a group delay that approximately matches the delay through the FLASH1-IDAC2A path.
  • the residue current is then digitized by the second-order second stage.
  • the second stage consists of an active-RC resonator, a 17-level flash ADC (FLASH2), current steering DACs (IDAC2B and IDAC3), and a capacitive-DAC (CDAC2) used to provide a DFB loop.
  • FLASH2 17-level flash ADC
  • IDAC2B and IDAC3 current steering DACs
  • CDAC2 capacitive-DAC
  • the second stage uses a feedback topology to minimize STF peaking and the input full-scale of the second stage is scaled down to provide an inter-stage gain of six to minimize the overall quantization noise floor while preventing the residue of the first stage from saturating the second stage.
  • the digital outputs of both stages, V1 and V2 are fed to the digital backend for further processing.
  • a 10-tap programmable FIR filter can implement digital quantization noise cancellation and equalization after decimation (DEC) by a factor of four.
  • DNCF coefficients can be generated using an off-chip LMS algorithm during an integrated start-up calibration phase.
  • delta-sigma ADCs are typically followed by decimation filters that remove high-frequency noise and provide the converted signals at the required higher resolution and lower data rates.
  • the digital noise cancellation filter may be implemented after these decimation filters, and without any loss of generality, the equalization filter can still be made a part of the digital noise cancellation filter.
  • the embodiments described herein is applicable for continuous-time MASH ADC (which uses continuous-time circuits), discrete-time MASH ADCs (which uses switched-capacitor circuits), or a hybrid continuous-time and discrete-time MASH ADC.
  • the embodiments described here are particularly applicable when the noise cancellation includes programmable filters on both the signal and noise paths. Having programmable digital filters on both signal and noise paths ensures that a filter response modification can be made commonly to both paths. If the cancellation uses a fixed filter on one of the paths, a separate, dedicated equalization filter with may be implemented for that path, while a programmable filter used on another one of the paths can be updated to combine the transfer function and EQF that achieves the full system STF (thus still benefiting from some area and power savings). Quantization noise cancellation is generally done at the output of the first two stages, but may not be performed for the third or later stages. The combining of the quantization noise cancellation and equalization can still be done for the programmable filters filtering the respective outputs of the first and second stages.
  • any number of electrical circuits of the FIGURES may be implemented on a board of an associated electronic device.
  • the board can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically.
  • Any suitable processors (inclusive of digital signal processors, microprocessors, supporting chipsets, etc.), computer-readable non-transitory memory elements, etc. can be suitably coupled to the board based on particular configuration needs, processing demands, computer designs, etc.
  • components such as transmitters, receivers, transceivers, processors, external storage, additional sensors, controllers for audio/video display, and peripheral devices may be attached to the board as plug-in cards, via cables, or integrated into the board itself.
  • the functionalities described herein may be implemented in emulation form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure that supports these functions.
  • the software or firmware providing the emulation may be provided on non-transitory computer-readable storage medium comprising instructions to allow a processor to carry out those functionalities.
  • the electrical circuits of the FIGURES may be implemented as stand-alone modules (e.g., a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic devices.
  • SOC system on chip
  • An SOC represents an IC that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio frequency functions: all of which may be provided on a single chip substrate.
  • MCM multi-chip-module
  • ASICs Application Specific Integrated Circuits
  • FPGAs Field Programmable Gate Arrays
  • the present architecture for digital noise cancellation and equalization are particularly suitable for high speed, continuous-time, high precision applications where MASH ADCs are used.
  • Applications which can greatly benefit from the architecture include: instrumentation, testing, spectral analyzers, military purposes, radar, wired or wireless communications, mobile telephones (especially because standards continue to push for higher speed communications), and base stations.
  • references to various features e.g., elements, structures, modules, components, steps, operations, characteristics, etc.
  • references to various features e.g., elements, structures, modules, components, steps, operations, characteristics, etc.
  • references to various features are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments.

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