US9575552B2 - Device, method and system for operation of a low power PHY with a PCIe protocol stack - Google Patents

Device, method and system for operation of a low power PHY with a PCIe protocol stack Download PDF

Info

Publication number
US9575552B2
US9575552B2 US14/129,545 US201314129545A US9575552B2 US 9575552 B2 US9575552 B2 US 9575552B2 US 201314129545 A US201314129545 A US 201314129545A US 9575552 B2 US9575552 B2 US 9575552B2
Authority
US
United States
Prior art keywords
state
interface
physical layer
protocol stack
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/129,545
Other languages
English (en)
Other versions
US20150220140A1 (en
Inventor
Choon Gun Por
Su Wei Lim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIM, SU WEI, POR, CHOON GUN
Publication of US20150220140A1 publication Critical patent/US20150220140A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION CORRECTIVE ASSIGNMENT TO CORRECT THE THE SPELLING OF INVENTOR 1 ON THE SIGNATURE PAGE: CHUN GUN POR PREVIOUSLY RECORDED ON REEL 034400 FRAME 0221. ASSIGNOR(S) HEREBY CONFIRMS THE THE SPELLING OF INVENTOR 1 ON THE SIGNATURE PAGE: CHOON GUN POR. Assignors: LIM, SU WEI, POR, CHOON GUN
Application granted granted Critical
Publication of US9575552B2 publication Critical patent/US9575552B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • Y02B60/1228—
    • Y02B60/1235—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments discussed herein relate generally to interconnect technologies.
  • interconnect mechanism To provide communication between different devices within a system, some type of interconnect mechanism is used. A wide variety of such interconnects are possible depending on a system implementation. Oftentimes to enable two devices to communicate with each other, they share a common communication protocol.
  • PCI ExpressTM Peripheral Component Interconnect Express
  • PCIeTM Peripheral Component Interconnect Express
  • IO input/output
  • FIG. 1 is a block diagram illustrating elements of a device for exchanging data packets according to an embodiment.
  • FIG. 2 is a flow diagram illustrating elements of a method for communicating with physical (PHY) layer circuitry according to an embodiment.
  • FIG. 3 is a block diagram illustrating elements of a device for processing data packets according to an embodiment.
  • FIG. 4 is a table illustrating elements of PHY layer interface signal translation according to an embodiment.
  • FIG. 5 is a state diagram illustrating elements of PHY layer interface signal translation according to an embodiment.
  • FIG. 6 is a state diagram illustrating power state transitions of a PHY layer according to an embodiment.
  • FIG. 7A is a state diagram illustrating operations for generation of an electric idle control signal according to an embodiment.
  • FIG. 7B is a block diagram illustrating elements of a circuit for generation of an electric idle control signal according to an embodiment.
  • FIG. 7C is a timing diagram illustrating generation of an electric idle control signal according to an embodiment.
  • FIG. 8 is a block diagram illustrating elements of a computer system according to one embodiment.
  • Embodiments discussed herein variously provide for an input/output (IO) interconnect architecture exhibiting low power operational characteristics which, for example, are particularly suited to use in mobile devices including tablet computers, cellular telephones such as smartphones, electronic readers, UltrabooksTM, and so forth.
  • IO input/output
  • a protocol stack for a given communication protocol may be used with a physical (PHY) unit of a different communication protocol, or at least a PHY unit different than the PHY unit for the given communication protocol.
  • a PHY unit may include a logical layer and a physical or electrical layer that provides for the actual, physical communication of information signals over an interconnect such as a link that networks two devices or, alternatively, that links two independent semiconductor die.
  • Such semiconductor die may be within a single integrated circuit (IC) package or separate packages, coupled, e.g., via a circuit board routing, trace or so forth.
  • the PHY unit may perform framing/deframing of data packets, perform link training and initialization, and process the data packets for delivery onto/receipt from a physical interconnect, and/or the like.
  • the protocol stack may be of a conventional personal computer (PC)-based communication protocol such as a PCIeTM communication protocol (hereafter a PCIeTM specification) in accordance with a PCIeTM specification such as the PCI ExpressTM Base Specification version 3.0 (published Nov. 18, 2010), a further version that applies protocol extensions, or another such protocol, while the PHY unit is not according to such a PCIeTM communication protocol.
  • PCIeTM communication protocol hereafter a PCIeTM specification
  • PCIeTM specification such as the PCI ExpressTM Base Specification version 3.0 (published Nov. 18, 2010)
  • This PHY unit may interface with translation circuitry specially designed for purposes of enabling low power operation to allow incorporation of a conventional PCIeTM upper protocol stack with this low power PHY circuitry.
  • this PHY unit may be a PHY unit adapted from a mobile platform such as a so-called M-PHY according to the M-PHY Specification Version 1.00.00—8 Feb. 2011 (MIPI Board Approved 28 Apr. 2011) of the Mobile Industry Processor Interface (MIPI) Alliance (hereafter MIPI specification), which is a group that sets standards for mobile computing devices.
  • M-PHY Mobile Industry Processor Interface
  • low power PHY units such as according to other low power specifications such as used to couple together individual dies within a multi-chip package, or a custom low power solution may be used.
  • low power means at a power consumption level below a conventional PC system, and which may be applicable to a wide variety of mobile and portable devices.
  • low power may be a PHY unit that consumes less power than a conventional PCIeTM PHY unit.
  • embodiments may be software compatible with ubiquitous PCIeTM architectures that have a large legacy base.
  • embodiments may also enable direct PHY re-use of a mobile-designed PHY, e.g., a M-PHY.
  • a system-on-chip may operate as a root complex that is implemented in a first IC, and is coupled directly or indirectly to a second IC that may include a radio solution, which may include one or more devices of multiple wireless communication devices.
  • Such devices may range from low power short range communication systems such as in accordance with a BluetoothTM specification, local wireless communications such as a so-called WiFiTM system in accordance with a given Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard, to a higher power wireless system such as a given cellular communication protocol such as a 3G or 4G communication protocol.
  • a BluetoothTM specification such as in accordance with a BluetoothTM specification
  • local wireless communications such as a so-called WiFiTM system in accordance with a given Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard
  • IEEE 802.11 Institute of Electrical and Electronics Engineers
  • FIG. 1 illustrates elements of a device 100 for exchanging data packets according to an embodiment.
  • Device 100 may include a combination of software, firmware and/or hardware within one or more semiconductor components such as an integrated circuit (IC) to provide for handling of data communication between device 100 and another device (not shown) coupled thereto.
  • device 100 includes PHY layer 130 for device 100 to participate in low power communications via a link 140 coupled to device 100 . Communications with low power PHY layer 130 may, in one or more respects, require a lower amount of power than that for communications with a PHY which is for PCIeTM communication.
  • PHY layer 130 may be for communications according to a specification other than a PCIeTM communication protocol, where such communications are for device 100 to exchange information with a MIPI (or other) low-power device.
  • Device 100 may further comprise protocol stack logic which, for example, includes PCIe protocol stack 150 to exchange communications with PHY layer 130 via translation circuitry 110 .
  • PCIe protocol stack 150 may operate to variously process packets exchanged via link 140 according to a low power communication standard.
  • Interconnect 140 may include a physical link coupling the device 100 with another device or component.
  • PCIe protocol stack 150 may be according to one or more conventional PCIeTM packet processing techniques.
  • portions of PCIeTM stack 150 may include a transaction layer 154 , a data link layer 152 and/or a media access control (MAC) layer 120 which variously provide at least some functionality for implementing PCIeTM communications.
  • transaction layer 154 may operate under higher level software 160 (e.g. including an OS) at least in part to generate transaction layer packets (TLP), which may be request or response-based packets separated by time, allowing the link to carry other traffic while the target device gathers data for the response.
  • the transaction layer 154 may further handle credit-based flow control, in an embodiment.
  • one responsibility of transaction layer 154 may be the assembly and disassembly of packets (i.e., transaction layer packets (TLPs)), as well as handling credit-based flow control.
  • TLPs transaction layer packets
  • link layer 152 may sequence TLPs that are generated by transaction layer 154 and ensure reliable delivery of TLPs between two endpoints (including handling error checking) and acknowledgement processing.
  • link layer 152 may act as one intermediate stage between transaction layer 154 and PHY layer 130 , and provide a reliable mechanism for exchanging TLPs between two components by a link.
  • One side of link layer 152 may accept TLPs assembled by transaction layer 154 , apply identifiers, calculate and apply an error detection code, e.g., cyclic recovery codes (CRC), and send the modified TLPs toward PHY layer 130 .
  • error detection code e.g., cyclic recovery codes (CRC)
  • MAC layer 120 exchanges such packets with link layer 152 and performs one or more operations for MAC processing thereof.
  • the packet processing performed by MAC layer 120 may include, for example, one or more scramble/de-scramble processing, stiping/de-striping processing, lane-lane deskew processing and/or the like.
  • MAC layer 120 may alternatively be a component of link layer 152 , in certain embodiments. Packets processed by MAC layer 120 may be the basis for communications which PHY layer 130 is to send from device 100 via interconnect 140 . Additionally or alternatively, communications which PHY layer 130 receives via interconnect 140 may result in other packet processing by MAC layer 120
  • the physical layer represented by PHY layer 130 physically transmits a packet to an external device.
  • a physical layer may include a transmit section to prepare outgoing information for transmission and a receiver section to identify and prepare received information before passing it to link layer 152 .
  • the transmitter may be supplied with symbols that are serialized and transmitted to an external device.
  • the receiver may be supplied with serialized symbols from the external device and transforms the received signals into a bitstream.
  • the bitstream may be de-serialized and supplied to a logical sub-block.
  • the processing of packets performed by PHY layer 130 may be according to one or more conventional packet processing techniques of a low power communication standard—e.g. a MIPI M-PHY specification.
  • the particular mechanisms of PHY layer 130 for implementing conventional MIPI M-PHY packet processing techniques, which can vary according to implementation-specific details, are outside the scope of this document and may not be limiting on certain embodiments.
  • Interconnect 140 may be implemented as differential pairs of wires that may be two pairs of unidirectional wires. In some implementations, multiple sets of differential pairs may be used to increase bandwidth. Note that according to the PCIeTM communication protocol, the number of differential pairs in each direction is required to be the same. According to various embodiments, however, different numbers of pairs may be provided in each direction, which allows more efficient and lower power operation.
  • translation circuitry 110 of device 100 is to facilitate communications between MAC layer 120 and PHY layer 130 .
  • Translation circuitry 110 may include logic for variously converting signaling between two or more PHY interface standards.
  • the two or more PHY interface standards includes a first interface standard for interfacing a PHY layer which is compatible with the PCIeTM standard with a MAC layer, data link layer or other protocol stack logic which is also compatible with a PCIeTM standard.
  • a first interface may include a PHY Interface for PCI Express (PIPE) specification such as the PHY Interface for the PCI Express Architecture, PCI Express 3.0, revision 0.5, August 2008, Intel Corporation.
  • MAC layer 120 may include PIPE interface logic 125 for an interface 170 with PIPE interface logic 112 of translation circuitry 110 , which is compatible with a PIPE specification.
  • the two or more PHY interface standards may include a second interface standard for interfacing a protocol stack according to a low power specification (e.g. MIPI) with a PHY layer which is to exchange communications according to that low power specification.
  • a second interface may include a Reference M-PHY Module Interface (RMMI) specification such as that set forth in the Specification for M-PHYSM, Version 2.0 of the MIPI Alliance, released Jun. 22, 2012.
  • RMMI Reference M-PHY Module Interface
  • PHY layer 130 may include RMMI interface logic 135 for an interface 175 with RMMI interface logic 114 of translation circuitry 110 which is compatible with a RMMI specification.
  • translation circuitry 110 provides for conversion between one or more communications exchanged by interface 112 according to the PIPE specification and one or more corresponding communications exchanged by interface 114 according to the RMMI specification.
  • Such translation, or conversion, by translation circuitry 110 may allow for PCIeTM functionality and low power communication standard (e.g. MIPI) functionality to be integrated without requiring modification to either conventional hardware of PCIe protocol stack 150 or conventional hardware of PHY layer 130 .
  • MIPI low power communication standard
  • FIG. 2 illustrates elements of a method 200 for exchanging communications with a protocol stack and a physical layer according to an embodiment.
  • method 200 may be performed for communications exchanged with a protocol stack which operates according to one communication standard—e.g. that of a PCIeTM specification—and physical layer circuitry which operates according to a comparatively low power communication standard such as a MIPI PHY specification.
  • method 200 is performed by a device which includes some or all of the features of translation circuitry 110 .
  • Method 200 may include, at 210 , translation circuitry sending information describing a state of a physical layer, wherein the information is sent from the translation circuitry via a first communication path to a protocol stack.
  • the translation circuitry may receive from the protocol stack a request for such state information. The request may be received by the communication path, although certain embodiments are not limited in this regard.
  • the translation circuitry may access one or more registers of the PHY to determine capability state or configuration state. Such register access may, for example, include the translation circuitry exchanging one or more RMMI control interface signals via a second interface.
  • Method 200 may further comprise, at 220 , the translation circuitry receiving from the protocol stack first signals based on the information describing the state of the physical layer.
  • the first signals may be based on one or more of the protocol stack identifying a capability of the physical layer and the protocol stack getting or setting a configuration of the physical layer.
  • the first signal may be to control the physical layer logic for transmission and/or reception of data with the physical layer logic.
  • the first signals may be received via a first interface of the translation circuitry which is compatible with a physical interface for Peripheral Component Interconnect Express (PIPE) specification.
  • PIPE Peripheral Component Interconnect Express
  • the first interface is distinct from—e.g. is in parallel with, a sideband channel with respect to, etc.—the first communication path used at 210 .
  • Method 200 may further comprise, at 230 , the translation circuitry sending to the physical layer second signals based on the first signals, the second signals for the physical layer to exchange communications for the protocol stack.
  • the translation circuitry may include logic to perform a translation, conversion and/or other process to generate the second signals based on the first signals.
  • the translation circuitry may provide intelligent conversion between RMMI signals and PIPE signals based on current state of the protocol stack and/or the PHY layer.
  • the second signals are sent via a second interface of the translation circuitry which is compatible with a reference mobile physical module interface (RMMI) specification.
  • RMMI reference mobile physical module interface
  • Method 200 may include one or more other operations (not shown) to further facilitate communications with the physical layer on behalf of the protocol stack.
  • the translation circuitry may receive via the second interface a control signal identifying a power state of the physical layer—e.g. a power state described in a MIPI PHY specification.
  • State machine logic of the translation circuitry may transition between a set of states including a plurality of states which each correspond to a different respective power state of a PCIeTM specification.
  • One or more state transitions of such state machine logic may be based on the received control signal, in an embodiment.
  • the state machine logic may transition to a state which causes the translation circuitry to indicate to the protocol stack the completion of a PHY power state transition.
  • the translation circuitry may indicate an associated transition between PCIeTM power states, including pulsing a PhyStatus signal of the PIPE interface.
  • the protocol stack may transition between a second set of states which, for example, each correspond to a respective power state according to a PCIeTM specification.
  • method 200 may further comprise the translation circuitry receiving from the protocol stack a first control signal based on a transition of the protocol stack between the second set of states. Based on the first control signal, the translation circuitry may further send via the second interface a second control signal to transition the physical layer from a first power state to a second power state.
  • the first power state and the second power state may each be according to a MIPI specification, for example.
  • the translation circuitry may, in an embodiment, correspond different power states which are according to the PCIeTM specification each with the same power state according to the MIPI specification.
  • FIG. 3 illustrates elements of a device 300 for exchanging data packets according to an embodiment.
  • Device 300 may include some or all of the features of device 100 , for example.
  • device 300 includes logic to perform the operations of method 200 .
  • Device 300 may include PHY layer logic 330 for device 300 to participate in low power communications with another device (not shown).
  • Device 300 may further comprise a PCIeTM protocol stack and translation circuitry 310 for the PCIeTM protocol stack to communicate with PHY layer logic 330 .
  • the PCIeTM protocol stack may include MAC layer logic 320 , link layer circuitry 360 and, in an embodiment, one or more higher level protocol stack layers (not shown).
  • MAC layer logic 320 includes transmit packet logic MAC Tx 322 to receive packets from link layer circuitry 360 and to perform MAC processing of such packets. Packet processing by MAC layer logic 320 may result in the generation of one or more signals PIPE TX 342 to be communicated in an interface with translation circuitry 310 which is compatible with a PIPE specification. Alternatively or in addition, MAC layer logic 320 may include receive logic MAC Rx 324 to receive one or more signals PIPE RX 344 communicated in such a PIPE interface with translation circuitry 310 . MAC Rx 324 may perform other MAC packet processing for generating packets to subsequently be provided to link layer circuitry 360 .
  • Translation circuitry 310 may perform one or more operations to translate or otherwise convert signals conforming to one PHY interface standard into corresponding signals which conform to a different PHY interface standard.
  • translation circuitry 310 includes transmit (Tx) logic 312 to receive PIPE TX 342 and to generate one or more signals RMMI TX 350 which represent information in PIPE TX 342 .
  • Tx logic 312 may then communicate RMMI TX 350 via an interface with PHY layer logic 330 which is compatible with an RMMI specification.
  • translation circuitry 310 may include receive (Rx) logic 314 to receive one or more signals RMMI RX 354 via such a RMMI interface with PHY layer logic 330 .
  • Rx logic 314 may generate some or all of PIPE RX 344 for representing information in RMMI RX 354 , and communicate PIPE RX 344 via the PIPE interface with MAC layer logic 320 .
  • PHY layer logic 330 includes transmitter M-PHY Tx 332 to transmit a differential signal pair TXDP, TXDN based on RMMI TX 350 .
  • PHY layer logic 330 may include receiver M-PHY Rx 334 to receive a differential signal pair RXDP, RXDN, where M-PHY Rx 334 generates RMMI RX 354 based on signal pair RXDP, RXDN.
  • Signals TXDP, TXDN and/or signals RXDP, RXDN may be exchanged according to a MIPI M-PHY specification, in an embodiment.
  • Translation circuitry 310 may further provide one or more signals to configure PHY layer logic 330 for variously receiving, generating and/or transmitting signals.
  • Tx logic 312 may provide one or more configuration signals RMMI Ctrl 352 for configuring M-PHY Tx 332 .
  • RX logic 314 may provide one or more configuration signals RMMI Ctrl 356 for configuring M-PHY Rx 334 .
  • Configuration of M-PHY Tx 332 based on RMMI Ctrl 352 may determine one or more characteristics of TXPD, TXPN for representing information in RMMI TX 350 .
  • configuration of M-PHY Rx 334 based on RMMI Ctrl 356 may determine one or more characteristics of RMMI RX 354 for representing information in RXPD, RXPN.
  • some or all signals of RMMI TX 350 may each correspond to a respective one of the M-TX-DATA interface signals of a MIPI PHY specification.
  • some or all signals of RMMI Ctrl 352 may each correspond to a respective one of the M-TX-CTRL interface signals of a MIPI PHY specification.
  • some or all signals of RMMI RX 354 may each correspond to a respective one of the M-RX-DATA interface signals of a MIPI PHY specification
  • some or all signals of RMMI Ctrl 356 may each correspond to a respective one of the M-RX-CTRL interface signals of a MIPI PHY specification.
  • one or more of PIPE RX 344 , RMMI TX 350 , RMMI Ctrl 352 , and RMMI Cfg 356 may be based on a state of device 300 and/or a state of a device in communication with device 300 via PHY layer logic 330 .
  • translation circuitry 310 may include control logic 316 to retrieve state information using communications of RMMI Ctrl 352 and/or communications of RMMI Ctrl 356 .
  • control logic 316 may evaluate information represented in PIPE TX 342 or RMMI RX 354 to detect system state including, but not limited to, one or more of a power state of PHY layer logic 330 , a presence or activity of a device coupled to device 300 via PHY layer logic 330 , and/or the like.
  • control logic 316 may be coupled to protocol stack logic of device 300 , such as link layer circuitry 360 , by a communication path 370 which is distinct from the PIPE interface with MAC layer logic 320 .
  • communication path 370 may be considered a sideband path which, for example, is used to provide the protocol stack with access one or more registers (not shown) of PHY layer logic 330 .
  • Control logic 316 may access such registers to retrieve PHY state information which may then be communicated to link layer circuitry 360 via communication path 370 .
  • PIPE-to-RMMI translation and/or RMMI-to-PIPE translation by translation circuitry 310 may be further based on such information exchanged via communication path 370 .
  • a request sent from link layer circuitry 360 via communication path 370 may be translated into RMMI based M-CTRL signaling for communication via RMMI Ctrl 352 and/or RMMI Ctrl 356 .
  • RMMI signaling may be to access capability, configuration and/or status attributes of PHY layer logic 330 .
  • the MIPI PHY standards variously specify such attributes for signal transmission (M-TX) and for signal reception (M-RX), as well as a M-TX-CTRL Service Access Point (SAP) and a M-RX-CTRL SAP to provide protocol stack logic with access to such attributes.
  • link layer circuitry 360 may exchange communications via path 370 to variously get, set or otherwise access attribute information in one or more registers (not shown) of PHY layer logic 330 . Such access may be performed—e.g. during the establishing of a link or runtime operation of the link—for the protocol stack to discover one or more PHY capabilities and/or to program PHY layer logic 330 to work in a particular high speed (HS) GEAR or other desired configuration.
  • Communication path 370 may bypass one or more protocol stack layers—e.g. including MAC layer logic 320 —although certain embodiments are not limited in this regard.
  • FIG. 4 shows a table 400 illustrating how translation circuitry, according to an embodiment, variously provides for conversion between PIPE signals 410 to be exchanged with MAC layer logic and corresponding RMMI signals 420 to be exchanged with PHY layer logic.
  • PIPE signals 410 may be signals of an interface such as that which includes PIPE TX 342 and/or PIPE RX 344 , for example.
  • RMMI signals 420 may be signals of an interface such as that which includes RMMI TX 350 , RMMI Ctrl 352 , RMMI RX 354 and/or RMMI Ctrl 356 .
  • a parallel interface clock signal PCLK of PIPE signals 410 may be received from a MAC layer to synchronize data transfers.
  • RMMI signals 420 may include one or more corresponding clock signals such as a receive control interface clock RX_CfgClk, a transmit control interface clock TX_CfgClk and/or a symbol clock TX_SymbolClk.
  • the translation circuitry may pass and output the received PCLK as both RX_CfgClk and TX_CfgClk.
  • the MAC layer may provide a reset signal Reset#, according to a PIPE specification, for resetting a PHY transmitter and/or a PHY receiver.
  • the translation logic may generate one or both of a RX_Reset signal and a TX_Reset for variously resetting a M-PHY receiver and a M-PHY transmitter, respectively.
  • RESET# may be an active low signal which is inverted by the translation circuitry and provided as each of active high signals TX_Reset, RX_Reset.
  • the translation circuitry may provide the MAC layer with a PIPE status signal PhyStatus to communicate the completion of one or more PHY layer operations including, for example, power management state transitions, rate change, and receiver detection.
  • PhyStatus may be generated by the translation circuitry as a function of a TX_SaveState_Status_N signal, which indicates that a M-PHY transmitter is entering or exiting a SAVE state, and/or a TX_PhyDIRDY signal which indicates whether a M-PHY transmitter is ready to accept new data on a TX_Symbol bus.
  • TX_SaveState_Status_N which indicates that a M-PHY transmitter is entering or exiting a SAVE state
  • TX_PhyDIRDY which indicates whether a M-PHY transmitter is ready to accept new data on a TX_Symbol bus.
  • the translation circuitry may provide to the MAC layer parallel PCIeTM data output signals RxData[19:0] based on corresponding symbols Rx_Symbol[19:0] received from the PHY layer according to the RMMI specification.
  • PIPE signals RxDataK[1:0] may be further provided to communicate to the MAC layer whether particular bits of RxData[19:0], at a given time, are control bits or data bits.
  • RxDataK[1:0] may include or otherwise be based on RMMI signals Rx_DataNCtrl[1:0] with which the PHY layer indicates a type of symbol (e.g. data symbol or control symbol) being communicated by some or all Rx_Symbol bits.
  • the translation circuitry provides a validity signal RxValid to communicate to the MAC layer whether there is currently valid data represented with RxData[19:0] and RxDataK[1:0].
  • RxValid may include or otherwise be based on an RMMI signal RX_PhyDORDY with which the PHY layer indicates that data is available in a corresponding range of signal lines for RX_Symbol.
  • the translation circuitry may communicate to the MAC layer a signal RxElecIdle indicating whether an electrical idle of a PHY receiver is detected—e.g. including indicating whether a beacon signal is detected.
  • RxElecIdle may be generated by the translation circuitry as a function of RMMI signals RX_Burst, which indicates whether a M-PHY receiver is receiving burst data, and RX_Hibern8Exit, which indicates that whether M-PHY receiver is exiting the HIBERN8 power state.
  • RxElecIdle may be generated based on the signals RX_Burst and RX_Hibern8Exit is discussed herein with reference to FIGS. 7A-7C .
  • PIPE signals 410 may further comprise signals RxStatus[2:0] to communicate various PHY receiver status information to the MAC layer.
  • RxStatus[2:0] includes or is otherwise based on RMMI signal RX_SymbolErr, with which the PHY layer indicates any of various errors associated with the decoding of a received symbol.
  • parallel PCIeTM data input bus TxData[19:0] exchanges transmit data from the MAC layer to the translation circuitry according to the PIPE specification.
  • the translation circuitry may provide to a M-PHY transmitter corresponding BURST transmit data TX_Symbol[19:0] according to the RMMI specification.
  • the MAC layer may further provide PIPE signals TxDataK[1:0] indicating whether particular bits of TxData[19:0], at a given time, are control bits or data bits.
  • TxDataK[1:0] the translation circuitry may communicate to the PHY layer a signal TX_ProtDORDY indicating whether data is available in a corresponding bus range of TX_Symbol.
  • the translation circuitry may receive from the MAC layer a PIPE signal TxElecIdle which indicates whether a PHY transmitter is to be placed in an electrical idle state.
  • TxElecIdle may be converted into a corresponding RMMI signal TX_Burst to indicate to the PHY layer whether (or not) a transmit BURST is to be initiated.
  • the translation circuitry is to maintain power state information for the PHY layer.
  • the maintaining of such power state information may include or otherwise be based on the translation circuitry mapping power states described in a PIPE specification with respective power states described in a RMMI specification.
  • a power state described in one PHY interface specification may be variously mapped to different power states described in another PHY interface specification. For example, a first PHY power state of the PIPE specification may map to one power state of the RMMI specification under one system state, but map to another power state of that same RMMI specification under a different system state.
  • PIPE signals 410 may include, for example, signals PowerDown[2:0] for the MAC layer to indicate a PHY power state to the translation circuitry. Based on PowerDown[2:0], the translation circuitry may communicate to the PHY layer a corresponding PHY power state of the RMMI specification. An example of how PowerDown[2:0] may be generated according to one embodiment is discussed herein with reference to FIG. 5 .
  • FIG. 5 illustrates elements of a state diagram 500 for providing communication with a PHY and a protocol stack, where respective operations of the PHY and the protocol stack are according to different respective communication standards.
  • Operation of such a PHY may include translation logic successively implementing states of state diagram 500 to variously associate PHY power states of a PCIeTM specification with PHY power states of a MIPI specification.
  • State diagram 500 may be implemented with state machine logic of the translation circuitry coupled between a protocol stack which is to operate according to a PCIeTM specification and a MIPI PHY controlled by the protocol stack.
  • state machine logic may cause the translation circuitry to exchange signals according to a PIPE interface standard—e.g.
  • Such PIPE signals may include one or more signals to indicate a PHY state, completion of a PHY state transitions and/or other such state information.
  • PIPE signals may include a PhyStatus signal, PowerDown[2:0] signals and/or the like.
  • Such PIPE signals may be exchanged based on activity of the RMMI interface and/or the PIPE interface of the translation circuitry.
  • state diagram 500 includes a reset state 505 which, for example, corresponds to an initial or other baseline state of the PHY and/or the protocol stack. From reset state 505 , the state machine may transition at 502 to a state 510 corresponding to any of for one or more low power PHY states—e.g. including P1 and/or P2 of the PCIeTM 3.0 specification.
  • multiple PCIeTM PHY power states may be associated with the same MIPI PHY power state—e.g. where one or more states of state diagram 500 do not distinguish P1 and P2 from one another, and associate both P1 and P2 with the same MIPI PHY state—e.g. HIBERN8.
  • a transition 512 from state 510 to a state 515 may take place in response the protocol stack indicating with PIPE signal PowerDown[1:0] a transition to a relatively low power PHY state—e.g. one corresponding to PCIeTM power state P2.
  • State 515 may be for the translation circuitry to signal a pulse of the PhyStatus signal of the PIPE interface. Completion of such a pulse may result in a transition 514 back to state 510 .
  • a transition 516 from state 510 to a state 520 may take place in response to PowerDown[1:0] indicating a higher power state POs.
  • Transition 516 may further be in response to an indication that the RMMI control interface M-CTRL is free—e.g. is available for use by the translation logic to read MTX state.
  • State 520 may be for the translation circuitry to signal the MIPI PHY to exit the HIBERN8 power state.
  • the state diagram transitions at 524 to a state 530 for checking the MTX state which has been read.
  • the machine state logic may transition at 526 back to state 525 to perform another read of MTX state. Otherwise, the machine state logic transitions at 532 to a state 535 for signaling a pulse of the PIPE signal PhyStatus. After the PhyStatus pulse is performed, the machine state logic transitions at 534 to a state 540 for operation of the MTX in a MIPI power state which the translation circuitry functionally equates a particular PCIeTM PHY power state—e.g. P0s of the PCIeTM 3.0 specification. This may be the PCIeTM power state which is requested or otherwise indicated by the PIPE signals PowerDown[2:0] which initiates transition 516 .
  • PCIeTM PHY power state e.g. P0s of the PCIeTM 3.0 specification. This may be the PCIeTM power state which is requested or otherwise indicated by the PIPE signals PowerDown[2:0] which initiates transition 516 .
  • a transition 542 from state 540 to a state 545 may be made in response to a signal from the protocol stack indicating a higher power state.
  • transition 542 may be in response to PIPE signals PowerDown[2:0] indicating that the MTX is to transition to a state corresponding to PCIeTM power state P0.
  • state 545 is for the translation circuitry to wait for the M-PHY transmitter to be ready to accept new data.
  • a transition 544 to a state 550 may be performed in response to a TX_DIRDY signal of the RMMI interface indicating readiness of the M-PHY transmitter for new data.
  • State 550 may be for the translation circuitry to signal a pulse of the PhyStatus signal of the PIPE interface. Completion of such a pulse may result in a transition 552 to a state 555 for the translation circuitry to transition the MTX to a high power state—e.g. a MIPI power state which the translation circuitry corresponds to PCIeTM power state P0. This may be the PCIeTM power state which is requested or otherwise indicated by the PIPE signals PowerDown[2:0] which initiates transition 542 .
  • a transition 554 from state 550 back to state 535 may subsequently be performed in response to a signal indicating a lower power state—e.g. in response to PIPE signals PowerDown[2:0] indicating that the PHY is to transition to a MIPI power state which the translation circuitry corresponds to PCIeTM power state POs.
  • Transition 554 may be in further response to PIPE signal TX_SaveState_Status_N indicating that the MTX is entering into a SAVE state.
  • the state machine logic may transition at 546 from state 540 to a state 560 in response to a signal from the protocol stack indicating a lower power state than POs.
  • transition 546 may be in response to PIPE signals PowerDown[2:0] indicating that the PHY is to transition to a state corresponding to one of PCIeTM power states P1, P2.
  • State 560 may include the state logic determining if M-CTRL interface is free, and when it is free, to transition at 562 to a state 565 which causes the translation circuitry to place the M-TX into a MIPI HIBERN8 state.
  • the state machine logic may transition at 564 to a state 570 for reading MTX state information via the M-CTRL interface.
  • the state machine may transition at 572 to a state 575 for checking the MTX state has been read. If the MTX state is determined to not be HIBERN8, then a transition at 574 back to state 570 is performed to reread the MTX state. If the MTX state is determined to be HIBERN8, then a transition 576 back to state 515 is performed.
  • FIG. 6 illustrates elements of a state diagram 600 for operation of protocol stack logic according to an embodiment.
  • the protocol stack logic may perform communications with a PHY, where respective operations of the PHY and the protocol stack are according to different respective communication standards.
  • State diagram 600 may be performed by state machine logic of PCIe protocol stack 150 , for example.
  • state diagram 600 may be implemented with link layer circuitry 360 or other link layer logic, although certain embodiments are not limited in this regard.
  • State diagram 600 includes various states which are each labeled to indicate a respective PCIeTM PHY state and to further indicate, in brackets, a respective MIPI PHY state which is associated with that PCIeTM PHY state.
  • protocol stack logic, translation circuitry and/or PHY layer logic may operate to according to an embodiment to map, correspond, or otherwise associate PCIeTM PHY states and MIPI PHY states with one another as indicated in FIG. 6 .
  • State diagram 600 may include a detect state 610 which represents an initial or other baseline state after a system power-on or other reset event. Detect state 610 may also be entered from one or more other states of state diagram 600 —e.g. including one or more of a hot-reset state 620 , a L2 state 630 , a loopback state 640 and a disabled state 660 . In an embodiment, detect state 610 is may be mapped to or otherwise associated with MIPI PHY power state HIBERN8.
  • State diagram 600 may further include a configuration (CFG) state 650 to be entered from detect state 610 .
  • CFG state 650 the protocol stack may exchange communications with translation circuitry—e.g. via communication path 370 —to discover capabilities of the MIPI M-PHY and/or to configure attributes of the MIPI M-PHY. Such communications to determine M-PHY capabilities and/or configuration may provide for the MIPI MTX and MRX send and receive data at a configured SUB-LINK width, rate series, data rate, etc. Additionally or alternatively, lane-to-lane de-skew may be implemented, scrambling may be enabled/disabled and/or the like.
  • CFG state 650 may be associated with either of the MIPI power states LS-MODE and HS-MODE. For example, CFG state 650 may be correspond to LS-MODE in an instance where CFG state 650 is entered from detect state 610 .
  • the state machine logic may transition to disabled state 660 for disabling one or more configured links—e.g. where it is determined that the one or more links are not to be used.
  • Disabled state 660 may be associated with MIPI power state HIBERN8.
  • the state machine logic may transition to loopback state 640 , which in an embodiment is associated with MIPI power state HS-MODE. Loopback state 640 may be for looping back data between a loopback master and a loopback slave for test and fault isolation purposes prior to returning to detect state 610 .
  • State diagram 600 may further include a L0 state 670 for the PCIeTM link power state L0, which corresponds to the PCIeTM PHY power state P0.
  • L0 is a normal operational state for data and control packets to be transmitted and received.
  • the other power management states L1 690 and L2 630 of state diagram 600 may be entered from L0 state 670 .
  • L0 state 670 may be associated with either of the MIPI power states HS-BURST and STALL. For example, during L0 state 670 , all configured lanes of a transmit sub-link in the MIPI PHY may be permitted to enter a STALL state. When one lane enters STALL, all configured lanes of the sub-link may be required to enter STALL. Additionally or alternatively, during L0 state 670 , all configured lanes of a receive sub-link in the MIPI PHY may be required to support entering STALL state. Each sub-link may be allowed to enter and exit STALL independently.
  • State diagram 600 may further include a recovery state 680 to be entered from L0 state 670 or, in an embodiment, from an L1 state 690 .
  • Recovery state 680 may be associated with MIPI power state HS-BURST, for example.
  • MIPI PHY may exchange training sequences with one or both of a MTX and a MRX.
  • Recovery state 680 may provide for (re)configuration of link bandwidth, bit lock, symbol lock, lane-to-lane de-skew and/or the like.
  • Recovery state 680 may also be used to enter disabled state 660 , hot-reset state 620 , detect state 610 or CFG state 650 , in an embodiment.
  • Hot reset 620 may include operations to implement a hot reset—e.g. according to a PCIeTM specification—for a return to detect state 610 .
  • Hot reset 620 may be associated with MIPI power state HIBERN8, in one embodiment.
  • state diagram 600 includes L1 state 690 for the PCIeTM link power state L1, which corresponds to the PCIeTM PHY power state P1.
  • L1 state 690 may be entered from L0 state 670 , and may be used to enter recovery state 680 .
  • L1 state 690 which is intended as a power savings state, may be associated with MIPI power state HIBERN8, for example.
  • State diagram 600 may further include L2 state 630 for the PCIeTM link power state L2, which corresponds to the PCIeTM PHY power state P2. In PCIe, power can be aggressively conserved in L2—e.g. where most of the MTX and MRX circuitry may be shut off.
  • L2 state 630 may be associated with MIPI power state HIBERN8.
  • L2 state 630 may be entered from L0 state 670 , and may be used to enter detect state 610 .
  • FIG. 7A is a state diagram 700 illustrating operations according to an embodiment for determining signaling to be communicated to a protocol stack.
  • State diagram 700 may be implemented with state machine logic of the translation circuitry coupled between a protocol stack which is to operate according to a PCIeTM specification and a MIPI PHY controlled by the protocol stack.
  • translation circuitry 110 may include state machine logic to implement state diagram 700 —e.g. in addition to translation circuitry 110 implementing state diagram 500 .
  • state diagram 700 includes a state 702 corresponding to a MIPI PHY being in a HIBERN8 state, a state 704 for when the MIPI PHY is not in HIBERN8, but is not exchanging a BURST of data, and a state 712 for when the MIPI PHY is exchanging a BURST of data.
  • a transition 704 from state 702 to state 706 may be in response to a HIBERN8 exit being asserted with the RMMI signal RX_Hibern8Exit.
  • a transition 708 from state 706 back to state 702 may be in response to a HIBERN8 entry being indicated by a deassertion of RX_Hibern8Exit.
  • a transition 710 from state 706 to state 712 may be in response to a data burst being indicated by the RMMI signal RX_Burst during assertion of RX_Hibern8Exit.
  • a transition 714 from state 712 back to state 702 may be in response to a subsequent deasserion of RX_Hibern8Exit.
  • FIG. 7B illustrates elements of a circuit 720 for generating the PIPE signal RxElecIdle based on MIPI PHY state which is indicated with various RMMI signals.
  • Circuit 702 may be include in translation circuitry such as that which is to implement state diagram 700 .
  • Circuit 720 may perform a multiplexing between an input based on the RMMI signal RX_Burst and another input based on the RMMI signal RX_Hibern8Exit. For circuit 720 , these inputs are respective inverted versions of such RMMI signals—i.e. !RX_Burst and !RX_Hibern8Exit—although certain embodiments are not limited in this regard.
  • the PIPE signal RxElecIdle may be determined based on a multiplexing between !RX_Burst and !RX_Hibern8Exit which, for example, is according to whether state diagram 700 is in burst state 712 .
  • FIG. 7C is a timing diagram 730 illustrating the generation of RxElecIdle based on the RMMI signals RX_Burst and RX_Hibern8Exit.
  • RxElecIdle is the logical opposite of RX_Hibern8Exit between times t 0 , t 3 , during which a state machine RX Eidle SM (corresponding to state diagram 700 ) is not in Burst state 712 .
  • RxElecIdle is the logical opposite of RX_Burst, and remains so until a next subsequent deassertion of RX_Hibern8Exit, which in this example occurs after time t 5 .
  • FIG. 8 illustrates elements of a computer system 800 for processing data packets exchanged according to an embodiment.
  • Computer system 800 includes processor 805 and system memory 810 coupled to controller hub 815 .
  • Processor 805 includes any processing element, such as a microprocessor, a host processor, an embedded processor, a co-processor, or other processor.
  • Processor 805 is coupled to controller hub 815 through front-side bus (FSB) 806 .
  • FSB 806 is a serial point-to-point interconnect as described below.
  • link 806 includes a serial, differential interconnect architecture that is compliant with different interconnect standard.
  • System memory 810 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in computer system 800 .
  • System memory 810 is coupled to controller hub 815 through memory interface 816 .
  • Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.
  • DDR double-data rate
  • DRAM dynamic RAM
  • controller hub 815 is a root hub, root complex, or root controller in a PCIeTM interconnection hierarchy.
  • controller hub 815 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub.
  • chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH).
  • MCH memory controller hub
  • ICH interconnect controller hub
  • current systems often include the MCH integrated with processor 805 , while controller 815 is to communicate with I/O devices, in a similar manner as described below.
  • peer-to-peer routing is optionally supported through root complex 815 .
  • controller hub 815 is coupled to switch/bridge 820 through serial link 819 .
  • Input/output modules 817 and 821 which may also be referred to as interfaces/ports 817 and 821 , include/implement a layered protocol stack to provide communication between controller hub 815 and switch 820 .
  • multiple devices are capable of being coupled to switch 820 .
  • Switch/bridge 820 may be further couple to device 825 via serial link 823 and respective input/output modules 822 and 826 .
  • Switch/bridge 820 may route packets/messages from device 825 upstream, i.e. up a hierarchy towards a root complex, to controller hub 815 and downstream, i.e. down a hierarchy away from a root controller, from processor 805 or system memory 810 to device 825 .
  • Switch 820 in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices.
  • Device 825 includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a Network Interface Controller (NIC), an add-in card, an audio processor, a network processor, a hard-drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices.
  • NIC Network Interface Controller
  • an add-in card an audio processor
  • a network processor a hard-drive
  • a storage device a CD/DVD ROM
  • monitor a printer
  • printer printer
  • a mouse a keyboard
  • USB Universal Serial Bus
  • device 825 may include a PCIeTM to PCI/PCI-X bridge to support legacy or other version PCI devices. Endpoint devices in PCIeTM are often classified as legacy, PCIe, or root complex integrated endpoints.
  • Graphics accelerator 830 is also coupled to controller hub 815 through serial link 832 .
  • graphics accelerator 830 is coupled to an MCH, which is coupled to an ICH.
  • Switch 820 and accordingly I/O device 825 , is then coupled to the ICH.
  • I/O modules 831 and 818 are also to implement a layered protocol stack to communicate between graphics accelerator 830 and controller hub 815 . Similar to the MCH discussion above, a graphics controller or the graphics accelerator 830 itself may be integrated in processor 805 .
  • a method comprises, with translation circuitry, sending information describing a state of a physical layer, wherein the information is sent from the translation circuitry via a first communication path to a protocol stack.
  • the method further comprises receiving from the protocol stack first signals based on the information describing the state of the physical layer, wherein the first signals are received via a first interface compatible with a physical interface for peripheral component interconnect express (PIPE) specification, the first interface distinct from the first communication path.
  • the method further comprises sending to the physical layer second signals based on the first signals, the second signals for the physical layer to exchange communications for the protocol stack, wherein the second signals are sent via a second interface compatible with a reference mobile physical module interface (RMMI) specification.
  • PIPE peripheral component interconnect express
  • the method further comprises receiving a request from the protocol stack via the communication path and, in response to request, accessing one or more registers of the PHY to identify capability state or configuration state, wherein the state of a physical layer includes the identified capability state or configuration state.
  • the method further comprises receiving via the second interface a control signal identifying a power state of the physical layer, and with first state machine logic of the translation circuitry, transitioning between a first set of states including a plurality of states each corresponding to a different respective power state of a Peripheral Component Interconnect Express specification, including performing a first state transition based on the received control signal.
  • the first interface includes a PhyStatus signal for indicating completion of a power state transition, the method further comprising, based on the received control signal, pulsing the Phystatus signal.
  • the protocol stack transitions between a second set of states each corresponding to a respective power state according to a Peripheral Component Interconnect Express specification
  • the method further comprises receiving from the protocol stack a first control signal based on a transition of the protocol stack between the second set of states.
  • the method further comprises sending via the second interface a second control signal based on the first control signal, the second control signal to transition the physical layer from a first power state to a second power state, the first power state and the second power state each according to a Mobile Industry Processor Interface (MIPI) specification.
  • MIPI Mobile Industry Processor Interface
  • the translation circuitry corresponds different power states according to the Peripheral Component Interconnect Express specification each with the same power state according to the MIPI specification.
  • the method further comprises transitioning the translation circuitry among a third set of states based on control signals received via the second interface, and based on the transitioning among the third set of states, sending via the first interface a signal indicating an electric idle state of the physical layer.
  • sending the signal indicating the electric idle state based on the transitioning among the third set of states includes, in response to the transitioning among the third set of states, multiplexing between a first RMMI control signal indicating a receipt of a data burst by the physical layer and a second RMMI control signal indicating a hibernate state of the physical layer.
  • the sending the signal indicating the electric idle state based on the transitioning among the third set of states further includes, based on the transitioning among the third set of states, generating the signal indicating the electric idle state.
  • a device comprises translation circuitry including control logic to send information describing a state of a physical layer, wherein the information is sent from the translation circuitry via a first communication path to a protocol stack.
  • the translation circuitry further includes a first interface to couple the translation circuitry to the protocol stack, the first interface compatible with a physical interface for peripheral component interconnect express (PIPE) specification, the first interface further to receive first signals based on the information describing the state of the physical layer, wherein the first signals are received from the protocol stack independent of the first communication path, wherein based on the first signals, the translation circuitry to generate second signals for the physical layer to exchange communications for the protocol stack.
  • the translation circuitry further includes a second interface to couple the translation circuitry to the physical layer, the second interface compatible with a reference mobile physical module interface (RMMI) specification, the second interface further to send the second signals to the physical layer.
  • RMMI reference mobile physical module interface
  • control logic is further to receive a request from the protocol stack via the communication path, and in response to request, to access one or more registers of the PHY including capability state or configuration state, wherein the state of a physical layer includes the capability state or configuration state.
  • second interface is further to receive a control signal identifying a power state of the physical layer, the translation circuitry further comprising first state machine logic to transition between a first set of states including a plurality of states each corresponding to a different respective power state of a Peripheral Component Interconnect Express specification, wherein the first state machine logic to perform a first state transition based on the received control signal.
  • the first interface is to send a PhyStatus signal indicating completion of a power state transition, wherein a pulse of the Phystatus signal is based on the received control signal.
  • the protocol stack transitions between a second set of states each corresponding to a respective power state according to a Peripheral Component Interconnect Express specification, the device further comprising the translation circuitry to receive from the protocol stack a first control signal based on a transition of the protocol stack between the second set of states.
  • the second interface is to send a second control signal based on the first control signal, the second control signal to transition the physical layer from a first power state to a second power state, the first power state and the second power state each according to a Mobile Industry Processor Interface (MIPI) specification.
  • MIPI Mobile Industry Processor Interface
  • the translation circuitry is to correspond different PHY power states according to the Peripheral Component Interconnect Express specification each with the same PHY power state according to the MIPI specification.
  • the translation circuitry further comprises second state machine logic to transition among a third set of states based on control signals received via the second interface, wherein based on a transition of the second state machine logic, the first interface to send a signal indicating an electric idle state of the physical layer.
  • a system comprises a protocol stack, a physical layer circuitry to exchange communications for the protocol stack and translation circuitry coupled between the protocol stack and the physical layer.
  • the translation circuitry includes control logic to send information describing a state of the physical layer, wherein the information is sent from the translation circuitry via a first communication path to the protocol stack.
  • the translation circuitry further includes a first interface coupling the translation circuitry to the protocol stack, the first interface compatible with a physical interface for peripheral component interconnect express (PIPE) specification, the first interface further to receive first signals based on the information describing the state of the physical layer, wherein the first signals are received from the protocol stack independent of the first communication path, wherein based on the first signals, the translation circuitry to generate second signals for the physical layer to exchange communications for the protocol stack.
  • the translation circuitry further includes a second interface coupling the translation circuitry to the physical layer, the second interface compatible with a reference mobile physical module interface (RMMI) specification, the second interface further to send the second signals to the physical layer.
  • RMMI reference mobile physical module interface
  • control logic is further to receive a request from the protocol stack via the communication path, and in response to request, to access one or more registers of the PHY including capability state or configuration state, wherein the state of a physical layer includes the capability state or configuration state.
  • second interface is further to receive a control signal identifying a power state of the physical layer, the translation circuitry further comprising first state machine logic to transition between a first set of states including a plurality of states each corresponding to a different respective power state of a Peripheral Component Interconnect Express specification, wherein the first state machine logic to perform a first state transition based on the received control signal.
  • the first interface is to send a PhyStatus signal indicating completion of a power state transition, wherein a pulse of the Phystatus signal is based on the received control signal.
  • the protocol stack is to transition between a second set of states each corresponding to a respective power state according to a Peripheral Component Interconnect Express specification, the translation circuitry to receive from the protocol stack a first control signal based on a transition of the protocol stack between the second set of states.
  • the second interface is to send a second control signal based on the first control signal, the second control signal to transition the physical layer from a first power state to a second power state, the first power state and the second power state each according to a Mobile Industry Processor Interface (MIPI) specification.
  • MIPI Mobile Industry Processor Interface
  • the translation circuitry is to correspond different PHY power states according to the Peripheral Component Interconnect Express specification each with the same PHY power state according to the MIPI specification.
  • the translation circuitry further comprises second state machine logic to transition among a third set of states based on control signals received via the second interface, wherein based on a transition of the second state machine logic, the first interface to send a signal indicating an electric idle state of the physical layer.
  • This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer.
  • a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.
US14/129,545 2013-04-17 2013-04-17 Device, method and system for operation of a low power PHY with a PCIe protocol stack Active 2033-08-02 US9575552B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2013/037000 WO2014171937A1 (en) 2013-04-17 2013-04-17 Device, method and system for operation of a low power phy with a pcie protocol stack

Publications (2)

Publication Number Publication Date
US20150220140A1 US20150220140A1 (en) 2015-08-06
US9575552B2 true US9575552B2 (en) 2017-02-21

Family

ID=51731717

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/129,545 Active 2033-08-02 US9575552B2 (en) 2013-04-17 2013-04-17 Device, method and system for operation of a low power PHY with a PCIe protocol stack

Country Status (5)

Country Link
US (1) US9575552B2 (de)
EP (1) EP2987087A4 (de)
KR (1) KR101725536B1 (de)
CN (1) CN105051706B (de)
WO (1) WO2014171937A1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180188321A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Device, system and method for providing on-chip test/debug functionality
US20190107882A1 (en) * 2017-10-11 2019-04-11 Qualcomm Incorporated Low power pcie
US10310585B2 (en) * 2016-10-27 2019-06-04 Qualcomm Incorporated Replacement physical layer (PHY) for low-speed peripheral component interconnect (PCI) express (PCIe) systems
US11755525B2 (en) 2021-04-14 2023-09-12 SK Hynix Inc. System including PIPE5 to PIPE4 converter and method thereof

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9652020B2 (en) * 2014-06-18 2017-05-16 Qualcomm Incorporated Systems and methods for providing power savings and interference mitigation on physical transmission media
US9697168B2 (en) * 2015-03-25 2017-07-04 Intel Corporation Apparatus, system and method for sharing physical layer logic across multiple protocols
US9723610B2 (en) * 2015-04-07 2017-08-01 Qualcomm Incorporated Multi-layer timing synchronization framework
WO2017052661A1 (en) * 2015-09-26 2017-03-30 Intel Corporation Multichip package link error detection
US20170286357A1 (en) * 2016-03-30 2017-10-05 Intel Corporation Method, Apparatus And System For Communicating Between Multiple Protocols
US10198394B2 (en) * 2016-05-24 2019-02-05 Intel Corporation Reduced pin count interface
US10127184B2 (en) 2016-09-27 2018-11-13 Intel Corporation Low overheard high throughput solution for point-to-point link
US10444999B2 (en) * 2016-10-13 2019-10-15 Qualcomm Incorporated Universal flash storage (UFS) host design for supporting embedded UFS and UFS card
US9960811B1 (en) 2016-10-27 2018-05-01 Hewlett Packard Enterprise Development Lp DC bias signals isolatable from transmission protocols
US20190324523A1 (en) * 2018-12-21 2019-10-24 Michelle C. Jen Alternate physical layer power mode
US11625084B2 (en) * 2019-08-15 2023-04-11 Intel Corporation Method of optimizing device power and efficiency based on host-controlled hints prior to low-power entry for blocks and components on a PCI express device
CN113489595B (zh) * 2021-06-28 2023-02-28 苏州浪潮智能科技有限公司 一种实现分离式mac和phy电磁兼容的系统、方法
TWI782694B (zh) * 2021-09-06 2022-11-01 智原科技股份有限公司 時序調整電路、時序不對稱消除方法及接收電路
TWI805469B (zh) * 2022-08-12 2023-06-11 創意電子股份有限公司 半導體晶片及序列檢查電路
CN116662231A (zh) * 2023-04-26 2023-08-29 珠海妙存科技有限公司 一种基于m-phy接口的速率匹配方法及其存储介质

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040088590A1 (en) 2002-09-04 2004-05-06 Johathan Lee System and method for optimizing power consumption in a mobile environment
US20090052903A1 (en) 2007-08-24 2009-02-26 Kip Mussatt System and method for expanding PCIe compliant signals over a fiber optic medium with no latency
US20100284451A1 (en) * 2006-08-18 2010-11-11 Nxp, B.V. Mac and phy interface arrangement
US20110231685A1 (en) * 2010-03-18 2011-09-22 Faraday Technology Corp. High speed input/output system and power saving control method thereof
US20120005506A1 (en) 2010-06-30 2012-01-05 Jim Walsh Systems and methods for implementing reduced power states
US20120068735A1 (en) * 2010-09-21 2012-03-22 Harriman David J Incorporating an independent logic block in a system-on-a-chip
WO2012052450A1 (en) 2010-10-18 2012-04-26 St-Ericsson Sa System and method to detect and communicate loss and retention of synchronization in a real-time data transfer scheme
WO2013048395A1 (en) 2011-09-28 2013-04-04 Intel Corporation Low power data recovery using over-clocking
US20140122767A1 (en) * 2012-10-29 2014-05-01 Qualcomm Incorporated Operating m-phy based communications over peripheral component interconnect (pci)-based interfaces, and related cables, connectors, systems and methods

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6385211B1 (en) * 1998-08-19 2002-05-07 Intel Corporation Network controller

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040088590A1 (en) 2002-09-04 2004-05-06 Johathan Lee System and method for optimizing power consumption in a mobile environment
US20100284451A1 (en) * 2006-08-18 2010-11-11 Nxp, B.V. Mac and phy interface arrangement
US20090052903A1 (en) 2007-08-24 2009-02-26 Kip Mussatt System and method for expanding PCIe compliant signals over a fiber optic medium with no latency
US20110231685A1 (en) * 2010-03-18 2011-09-22 Faraday Technology Corp. High speed input/output system and power saving control method thereof
US20120005506A1 (en) 2010-06-30 2012-01-05 Jim Walsh Systems and methods for implementing reduced power states
US20120068735A1 (en) * 2010-09-21 2012-03-22 Harriman David J Incorporating an independent logic block in a system-on-a-chip
WO2012052450A1 (en) 2010-10-18 2012-04-26 St-Ericsson Sa System and method to detect and communicate loss and retention of synchronization in a real-time data transfer scheme
WO2013048395A1 (en) 2011-09-28 2013-04-04 Intel Corporation Low power data recovery using over-clocking
US20140122767A1 (en) * 2012-10-29 2014-05-01 Qualcomm Incorporated Operating m-phy based communications over peripheral component interconnect (pci)-based interfaces, and related cables, connectors, systems and methods

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
"PCT, International Search Report and Written Opinion of the International Searching Authority for International Application No. PCT/US2013/037000", (Jan. 29, 2014), Whole Document.
Cosmic Circuits: "MIPI MPHY-An Introduction", Design & Reuse, Mar. 3, 2011, pp. 1-4. Retrieved from the Internet: URL: http://www.design-reuse.com/articles/25764/mipi-m-phy-ip.htm on Jan. 28, 2015.
European Search Report for European Patent Application No. 13882346.3 Mailed Nov. 28, 2016, 8 pages.
International Preliminary Report on Patentability PCT Application No. PCT/US2013/037000 mailed Oct. 29, 2015, 9 pages.
MIPI, "Test and Debug Interface Framework, Apr. 7, 2006, Approved Version 3.2, Retrieved from http://www.mipi.org/sites/default/files/whitepapers/MIPI-TDWG-whitepaper-v3-2.pdf", (Apr. 7, 2006), 11 pgs.
Office Action for Korean Patent Application No. 2015-7025414, mailed Jul. 8, 2016, 5 pgs.
Rubenstein, Roy , "Hybrids drive interfaces-USB 3.0 and PCIe 3.0 set to play an embedded role in mobile devices, Jan. 22, 2013, Retrieved from http://fplreflib.findlay.co.uk/articles/47459/P29-30.pdf", (Jan. 22, 2013), pp. 29-30.

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10310585B2 (en) * 2016-10-27 2019-06-04 Qualcomm Incorporated Replacement physical layer (PHY) for low-speed peripheral component interconnect (PCI) express (PCIe) systems
US20180188321A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Device, system and method for providing on-chip test/debug functionality
US10705142B2 (en) * 2016-12-29 2020-07-07 Intel Corporation Device, system and method for providing on-chip test/debug functionality
US20190107882A1 (en) * 2017-10-11 2019-04-11 Qualcomm Incorporated Low power pcie
US10963035B2 (en) * 2017-10-11 2021-03-30 Qualcomm Incorporated Low power PCIe
US11755525B2 (en) 2021-04-14 2023-09-12 SK Hynix Inc. System including PIPE5 to PIPE4 converter and method thereof

Also Published As

Publication number Publication date
EP2987087A1 (de) 2016-02-24
KR101725536B1 (ko) 2017-04-11
CN105051706A (zh) 2015-11-11
WO2014171937A1 (en) 2014-10-23
EP2987087A4 (de) 2016-12-28
CN105051706B (zh) 2018-07-24
US20150220140A1 (en) 2015-08-06
KR20150120444A (ko) 2015-10-27

Similar Documents

Publication Publication Date Title
US9575552B2 (en) Device, method and system for operation of a low power PHY with a PCIe protocol stack
CN106209695B (zh) 给加载/存储通信协议提供低功率物理单元
US9390046B2 (en) Controlling a physical link of a first protocol using an extended capability structure of a second protocol
US9830292B2 (en) Architected protocol for changing link operating mode
US9141577B2 (en) Optimized link training and management mechanism
US8549205B1 (en) Providing a consolidated sideband communication channel between devices
EP2619907B1 (de) Einbeziehung eines unabhängigen logikblocks in einem on-chip-system
US11513584B2 (en) Method and apparatus to save power in USB repeaters/re-timers
US20210004347A1 (en) Approximate data bus inversion technique for latency sensitive applications
CN107092335B (zh) 优化的链路训练及管理机制
US20170286357A1 (en) Method, Apparatus And System For Communicating Between Multiple Protocols
US20230315672A1 (en) Interface device and computing system including the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:POR, CHOON GUN;LIM, SU WEI;REEL/FRAME:034400/0221

Effective date: 20140223

AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE THE SPELLING OF INVENTOR 1 ON THE SIGNATURE PAGE: CHUN GUN POR PREVIOUSLY RECORDED ON REEL 034400 FRAME 0221. ASSIGNOR(S) HEREBY CONFIRMS THE THE SPELLING OF INVENTOR 1 ON THE SIGNATURE PAGE: CHOON GUN POR;ASSIGNORS:POR, CHOON GUN;LIM, SU WEI;REEL/FRAME:040912/0959

Effective date: 20161214

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4