US9252257B2 - III-nitride semiconductor device with reduced electric field between gate and drain - Google Patents

III-nitride semiconductor device with reduced electric field between gate and drain Download PDF

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US9252257B2
US9252257B2 US14/332,589 US201414332589A US9252257B2 US 9252257 B2 US9252257 B2 US 9252257B2 US 201414332589 A US201414332589 A US 201414332589A US 9252257 B2 US9252257 B2 US 9252257B2
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nitride
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Michael A. Briere
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Infineon Technologies North America Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H01L29/475—Schottky barrier electrodes on AIII-BV compounds
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Definitions

  • the present application relates to semiconductor devices and methods of fabrication of semiconductor devices.
  • III-Nitride refers to a semiconductor alloy from the InAlGaN system, including, but not limited to, GaN, AlGaN, AIN, InGaN, InAlGaN and the like.
  • a device To reduce the electric field between the gate electrode and the drain electrode, a device according to the present invention includes field plates each disposed between one or more pairs a gate electrode and a drain electrode, each field plate electrically shorted to the source electrode of the device.
  • a III-Nitride power device is provided with a field plate over its heterojunction structure.
  • the field plate may be comprised of a highly conductive III-Nitride body which is shorted to the source electrode of the device.
  • a wide conductive plate is fabricated using any desired method, and then the wide plate is separated into thinner respective interleaved gate electrodes and field plates, for example, through an appropriate etching step, to obtain separated gate electrodes and field plates.
  • FIG. 1 schematically illustrates a top plan view of two adjacently disposed active cells in a device according to the present invention.
  • FIG. 2 schematically illustrates a cross-sectional view along line 2 - 2 viewed in the direction of the arrows.
  • FIG. 3 schematically illustrates a top plan view of a device before the modification thereof using a process according to the present invention.
  • FIG. 4 schematically illustrates a cross-sectional view of a second embodiment of the present invention.
  • FIG. 5 schematically illustrates a cross-sectional view of two adjacent active cells of device according to a further embodiment of the present invention.
  • FIGS. 6 and 7 schematically illustrate selected steps in a process for the fabrication of the device of FIG. 5 according to the present invention.
  • FIG. 8 schematically illustrates a cross-sectional view of two adjacent cells of a device in accordance with the invention according to a further embodiment of the invention.
  • FIG. 9 is like FIG. 8 and shows a still further embodiment of the invention.
  • the device includes drain electrodes 10 , a source electrode 12 , gate electrodes 14 each disposed between source electrode 12 and a respective drain electrode 10 , and field plates 16 each disposed between a gate electrode 14 and a respective drain electrode 10 .
  • All of electrodes 10 , 12 , 14 and field plate 16 may be of any desired conductive material deposited atop heterojunction 18 .
  • source electrode 12 and field plates 16 are electrically shorted to one another as schematically illustrated by FIG. 1 .
  • a device according to the present invention is preferably a III-Nitride power field effect device, such as a high electron mobility transistor (HEMT).
  • a device according to the present invention thus includes the III-Nitride heterojunction 18 formed over a support body 20 .
  • III-Nitride heterojunction 18 includes a first III-Nitride body 22 serving preferably as a channel layer, and a second III-Nitride body 24 serving as a barrier layer.
  • the thickness and composition of first and second III-Nitride bodies 22 , 24 are selected to result in a conductive region at (or near) the heterojunction thereof, commonly referred to as a two-dimensional electron gas (2-DEG).
  • 2-DEG two-dimensional electron gas
  • first III-Nitride body 22 is comprised of GaN while second III-Nitride body 24 is comprised of AlGaN. Further, in the embodiment of FIGS. 1 , 2 and 3 , drain electrodes 10 and source electrode 12 make ohmic contact with second III-Nitride body 24 , while gate electrodes 14 and field plates 16 make a Schottky contact to second III-Nitride body 24 .
  • support body 20 may include a substrate which is compatible with first III-Nitride body 22 (e.g. a GaN substrate) or may include a substrate comprised of silicon, SiC, Sapphire, or the like having a transition body or layer (e.g. an MN body) to allow for the growth thereon of first III-Nitride body 22 .
  • a III-Nitride device is fabricated according to any suitable method to have wide gate electrodes 14 is formed between each drain electrode 10 and source electrode 12 . Thereafter, each wide gate electrode 14 is split or separated into two strips (using any desired and suitable etching technique, for example) to obtain field plates 16 and gate electrodes 14 as illustrated by FIG. 1 .
  • gate electrodes 14 and field plates 16 are deposited over a gate insulation body 26 which is on body 24 and has a composition and thickness suitable to function as a gate dielectric.
  • gate electrode 14 and field plate 16 may be capacitively coupled to body 24 , rather than being Schottky coupled to body 24 .
  • a device includes the III-Nitride heterojunction 18 formed over a support body 20 .
  • Heterojunction 18 includes the first III-Nitride body 22 formed over support body 20 , and second III-Nitride body 24 formed over first III-Nitride body 22 .
  • the thickness and composition of first and second III-Nitride bodies 22 , 24 are selected to form a two-dimensional electron gas at (or near) the heterojunction thereof, as is well known in the art.
  • first III-Nitride body 22 serves as the channel layer and may be composed of GaN
  • second III-Nitride body 24 serves as the barrier layer and may be composed of AlGaN
  • Support body 20 may be a substrate that is compatible with first III-Nitride body 22 , e.g. GaN, or may be a substrate (e.g. silicon, SiC or sapphire) that includes a transition layer (e.g. AlN) to allow for the growth thereon of first III-Nitride body 22 .
  • first power electrode 12 e.g. source electrode
  • second power electrode 10 e.g. drain electrode
  • gate electrode 14 makes a Schottky contact with second III-Nitride body.
  • a gate electrode 14 may be capacitively coupled to second III-Nitride body 24 (e.g. through a gate dielectric) without deviating from the scope and the spirit of the present invention.
  • field plate 16 that is comprised of highly conductive (e.g. N+) III-Nitride material (e.g. GaN or AlGaN) is disposed over second III-Nitride body 24 and between a gate electrode 14 and drain electrode 10 .
  • Field plates 16 are preferably electrically shorted to source electrode 12 , whereby the voltage between gate electrode 14 and drain electrode 10 is reduced to improve the breakdown voltage of the device.
  • the short can be formed in any desired manner.
  • each drain electrode 10 and source electrode 12 resides atop and is ohmically coupled to a respective highly conductive (e.g. N+) III-Nitride (e.g. GaN or AlGaN) pedestal 36 which is formed over second III-Nitride body 24 , whereby ohmic connection between the power electrodes 10 , 12 and second III-Nitride body 24 is improved.
  • a respective highly conductive (e.g. N+) III-Nitride e.g. GaN or AlGaN
  • the III-Nitride heterojunction 18 is formed over a support body 20 according to any suitable method. Thereafter, a highly conductive III-Nitride layer 38 (e.g. a layer of N+ GaN or N+AlGaN) is grown over second III-Nitride body 24 . Next, a layer of conductive material for forming power electrodes 10 , 12 is formed on second III-Nitride body 24 and patterned to obtain electrodes 10 and 12 .
  • a highly conductive III-Nitride layer 38 e.g. a layer of N+ GaN or N+AlGaN
  • a layer of conductive material for forming power electrodes 10 , 12 is formed on second III-Nitride body 24 and patterned to obtain electrodes 10 and 12 .
  • Layer 38 is then patterned to include a plurality of gaps 40 , 41 ( FIG. 7 ) in order to obtain or define field plates 16 and pedestals 36 .
  • gaps 40 and 41 serve to physically isolated field plates 16 and pedestals 36 .
  • gate electrodes 14 are formed in gaps 41 of FIG. 7 on second III-Nitride body 24 , and field plates 16 and source electrode 12 are electrically shorted to obtain a device according to the present invention.
  • the device is an enhancement mode device and field plates 16 may be any conductive material including metallic materials as well as a highly conductive III-Nitride laser or body as described above.
  • An enhancement mode device includes a 2-DEG layer having an interrupted region or a region of reduced carrier density 50 under gate electrode 14 .
  • a recess may be formed in the body 24
  • an implanted region may be formed in either body 24 or 22
  • the surface of body 24 may be treated using CF4 under the gate, or local decomposition as set forth in U.S. application Ser. No.
  • a gate dielectric 26 may be disposed between the gate electrodes 14 and body 24 .
  • dielectric body 26 may be disposed between field plates 16 and body 24 .
  • pedestals 26 may be omitted without deviating from the scope and the spirit of the present invention.
  • electrodes 14 and 16 may be coupled ohmically to body 16 .

Abstract

A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N+ III-Nitride pad layers and the gate may be a Schottky gate or an insulated gate.

Description

This is a continuation of application Ser. No. 12/211,120 filed Sep. 16, 2008.
RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 60/973,295, filed Sep. 18, 2007; and U.S. Provisional Application No. 60/973,367, filed Sep. 18, 2007, the entire disclosure of which is incorporated by reference herein.
FIELD OF THE INVENTION
The present application relates to semiconductor devices and methods of fabrication of semiconductor devices.
DEFINITION
As referred to herein III-Nitride refers to a semiconductor alloy from the InAlGaN system, including, but not limited to, GaN, AlGaN, AIN, InGaN, InAlGaN and the like.
BACKGROUND OF THE INVENTION
It is known that the electric field between the gate electrode and the drain electrode of a III-Nitride power semiconductor device affects the breakdown voltage thereof. Thus, it is desirable to reduce the gate to drain voltage that a gate electrode “sees” during the operation of the device.
SUMMARY OF THE INVENTION
To reduce the electric field between the gate electrode and the drain electrode, a device according to the present invention includes field plates each disposed between one or more pairs a gate electrode and a drain electrode, each field plate electrically shorted to the source electrode of the device.
More specifically, according to one aspect of the present invention, a III-Nitride power device is provided with a field plate over its heterojunction structure. The field plate may be comprised of a highly conductive III-Nitride body which is shorted to the source electrode of the device. As a result, the gate to drain voltage “seen” by the gate electrode is reduced, whereby the capability of the device to withstand breakdown is enhanced.
In a preferred method of fabrication of a device according to the present invention, to obtain as close a spacing between each gate electrode and a respective field plate, a wide conductive plate is fabricated using any desired method, and then the wide plate is separated into thinner respective interleaved gate electrodes and field plates, for example, through an appropriate etching step, to obtain separated gate electrodes and field plates.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 schematically illustrates a top plan view of two adjacently disposed active cells in a device according to the present invention.
FIG. 2 schematically illustrates a cross-sectional view along line 2-2 viewed in the direction of the arrows.
FIG. 3 schematically illustrates a top plan view of a device before the modification thereof using a process according to the present invention.
FIG. 4 schematically illustrates a cross-sectional view of a second embodiment of the present invention.
FIG. 5 schematically illustrates a cross-sectional view of two adjacent active cells of device according to a further embodiment of the present invention.
FIGS. 6 and 7 schematically illustrate selected steps in a process for the fabrication of the device of FIG. 5 according to the present invention.
FIG. 8 schematically illustrates a cross-sectional view of two adjacent cells of a device in accordance with the invention according to a further embodiment of the invention.
FIG. 9 is like FIG. 8 and shows a still further embodiment of the invention.
 DETAILED DESCRIPTION OF THE DRAWINGS
Referring to FIG. 1, two adjacent cells of a much larger device according to one embodiment of the present invention is shown. The device includes drain electrodes 10, a source electrode 12, gate electrodes 14 each disposed between source electrode 12 and a respective drain electrode 10, and field plates 16 each disposed between a gate electrode 14 and a respective drain electrode 10. All of electrodes 10, 12, 14 and field plate 16 may be of any desired conductive material deposited atop heterojunction 18.
According to one aspect of the present invention source electrode 12 and field plates 16 are electrically shorted to one another as schematically illustrated by FIG. 1.
Referring now to FIG. 2, a device according to the present invention is preferably a III-Nitride power field effect device, such as a high electron mobility transistor (HEMT). A device according to the present invention thus includes the III-Nitride heterojunction 18 formed over a support body 20. III-Nitride heterojunction 18 includes a first III-Nitride body 22 serving preferably as a channel layer, and a second III-Nitride body 24 serving as a barrier layer. The thickness and composition of first and second III- Nitride bodies 22, 24 are selected to result in a conductive region at (or near) the heterojunction thereof, commonly referred to as a two-dimensional electron gas (2-DEG). In the embodiment of FIGS. 1, 2 and 3, first III-Nitride body 22 is comprised of GaN while second III-Nitride body 24 is comprised of AlGaN. Further, in the embodiment of FIGS. 1, 2 and 3, drain electrodes 10 and source electrode 12 make ohmic contact with second III-Nitride body 24, while gate electrodes 14 and field plates 16 make a Schottky contact to second III-Nitride body 24. Note that support body 20 may include a substrate which is compatible with first III-Nitride body 22 (e.g. a GaN substrate) or may include a substrate comprised of silicon, SiC, Sapphire, or the like having a transition body or layer (e.g. an MN body) to allow for the growth thereon of first III-Nitride body 22.
Referring now to FIG. 3, in a preferred method for fabricating a device according to the present invention, a III-Nitride device is fabricated according to any suitable method to have wide gate electrodes 14 is formed between each drain electrode 10 and source electrode 12. Thereafter, each wide gate electrode 14 is split or separated into two strips (using any desired and suitable etching technique, for example) to obtain field plates 16 and gate electrodes 14 as illustrated by FIG. 1.
Referring now to FIG. 4, in which like numerals identify like features, in an alternative embodiment, gate electrodes 14 and field plates 16 are deposited over a gate insulation body 26 which is on body 24 and has a composition and thickness suitable to function as a gate dielectric. Thus, after splitting, layer 14′ in FIG. 3, gate electrode 14 and field plate 16 may be capacitively coupled to body 24, rather than being Schottky coupled to body 24.
Referring next to FIG. 5, in which components similar to those of FIGS. 1 to 4 are given the same identifying numeral, a device according to the another embodiment of the present invention includes the III-Nitride heterojunction 18 formed over a support body 20. Heterojunction 18 includes the first III-Nitride body 22 formed over support body 20, and second III-Nitride body 24 formed over first III-Nitride body 22. The thickness and composition of first and second III- Nitride bodies 22, 24 are selected to form a two-dimensional electron gas at (or near) the heterojunction thereof, as is well known in the art.
In FIG. 5, first III-Nitride body 22 serves as the channel layer and may be composed of GaN, and second III-Nitride body 24 serves as the barrier layer and may be composed of AlGaN. Support body 20 may be a substrate that is compatible with first III-Nitride body 22, e.g. GaN, or may be a substrate (e.g. silicon, SiC or sapphire) that includes a transition layer (e.g. AlN) to allow for the growth thereon of first III-Nitride body 22.
The embodiment of FIG. 5 further includes, in each active cell thereof, first power electrode 12 (e.g. source electrode), second power electrode 10 (e.g. drain electrode), and a gate electrode 14 disposed between first power electrode 12 and second power electrode 10. In the preferred embodiment, gate electrode 14 makes a Schottky contact with second III-Nitride body. However, it should be understood that a gate electrode 14 may be capacitively coupled to second III-Nitride body 24 (e.g. through a gate dielectric) without deviating from the scope and the spirit of the present invention.
According to one aspect of the invention as shown in FIG. 5, field plate 16 that is comprised of highly conductive (e.g. N+) III-Nitride material (e.g. GaN or AlGaN) is disposed over second III-Nitride body 24 and between a gate electrode 14 and drain electrode 10. Field plates 16 are preferably electrically shorted to source electrode 12, whereby the voltage between gate electrode 14 and drain electrode 10 is reduced to improve the breakdown voltage of the device. The short can be formed in any desired manner.
In the embodiment of FIG. 5, each drain electrode 10 and source electrode 12 resides atop and is ohmically coupled to a respective highly conductive (e.g. N+) III-Nitride (e.g. GaN or AlGaN) pedestal 36 which is formed over second III-Nitride body 24, whereby ohmic connection between the power electrodes 10, 12 and second III-Nitride body 24 is improved.
Referring now to FIGS. 6 and 7, to fabricate a device according to the embodiment of FIG. 5, the III-Nitride heterojunction 18 is formed over a support body 20 according to any suitable method. Thereafter, a highly conductive III-Nitride layer 38 (e.g. a layer of N+ GaN or N+AlGaN) is grown over second III-Nitride body 24. Next, a layer of conductive material for forming power electrodes 10, 12 is formed on second III-Nitride body 24 and patterned to obtain electrodes 10 and 12.
Layer 38 is then patterned to include a plurality of gaps 40, 41 (FIG. 7) in order to obtain or define field plates 16 and pedestals 36. Note that gaps 40 and 41 serve to physically isolated field plates 16 and pedestals 36. Thereafter, gate electrodes 14 are formed in gaps 41 of FIG. 7 on second III-Nitride body 24, and field plates 16 and source electrode 12 are electrically shorted to obtain a device according to the present invention.
Referring next to FIG. 8 in which numerals identify like features of the preceding Figures, the device is an enhancement mode device and field plates 16 may be any conductive material including metallic materials as well as a highly conductive III-Nitride laser or body as described above. An enhancement mode device according to this embodiment, includes a 2-DEG layer having an interrupted region or a region of reduced carrier density 50 under gate electrode 14. To obtain the interrupted region or the region of reduced carrier density many different methods may be used. For example, a recess may be formed in the body 24, an implanted region may be formed in either body 24 or 22, the surface of body 24 may be treated using CF4 under the gate, or local decomposition as set forth in U.S. application Ser. No. 11/906,842 filed Oct. 4, 2007, entitled III-Nitride Heterjunction Semiconductor Device and Method of Fabrication (IR-3282) (incorporated by reference) may be employed to obtain an interrupted 2-DEG or a 2-DEG of reduced density under gate electrode 14. U.S. application Ser. No. 11/040,657 filed Jan. 21, 2005, entitled Enhancement Mode III-Nitride FET (IR-2663) (incorporated herein in its entirety by reference) sets forth various way to obtain a 2-DEG layer having an interrupted region or a region of reduced carrier density under the gate electrode thereof. Note that in the embodiment of FIG. 8 gate electrode 14 is Schottky coupled to body 16.
It has been found that the combination of a field plate 16 that is shorted to the source electrode in an enhancement mode device (i.e. a device with an interrupted 2-DEG or a 2-DEG with a reduced carrier density under the gate) results in a III-Nitride enhancement mode device that is stable during operation which up to now has eluded those skilled in the art.
Referring next to FIG. 9, in which like numerals identify like features of the prior Figures, in a device according to the third embodiment of the present invention, and, as in FIG. 4, a gate dielectric 26 may be disposed between the gate electrodes 14 and body 24. Furthermore, dielectric body 26 may be disposed between field plates 16 and body 24. Note that in the embodiments of FIGS. 8 and 9, pedestals 26 may be omitted without deviating from the scope and the spirit of the present invention. Thus, electrodes 14 and 16 may be coupled ohmically to body 16.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.

Claims (9)

What is claimed is:
1. A III-Nitride semiconductor device comprising:
a first III-Nitride layer;
a second III-Nitride layer over said first III-Nitride layer;
a 2DEG layer formed by the interface between said first and second III-Nitride layers;
a source contact connected to said first III-Nitride layer;
a drain contact laterally spaced from said source contact and connected to said first III-Nitride layer,
a gate contact coupled to said first III-Nitride layer and disposed laterally between said source and drain contacts;
a conductive field plate disposed between said gate and drain contacts and connected to said source contact to reduce the electric field between said gate and drain contacts when said 2DEG layer is non-conductive, wherein said conductive field plate having a thickness is formed from a first portion of a gate electrode, and wherein said gate contact having said thickness is formed from a second portion of said gate electrode, said first and second portions of said gate electrode having a coplanar top surface, said second portion being physically separated and laterally spaced from said first portion.
2. The III-Nitride semiconductor device of claim 1, wherein said conductive field plate and said gate contact are formed on a top surface of said second III-Nitride layer.
3. The III-Nitride semiconductor device of claim 1, wherein said first III-Nitride layer is GaN and said second III-Nitride layer is AlGaN, and wherein said conductive field plate comprises N type III-Nitride material.
4. The III-Nitride semiconductor device of claim 1, wherein said second III-Nitride layer is supported on a substrate.
5. The III-Nitride semiconductor device of claim 4, wherein said substrate comprises silicon and includes a transition layer below said second III-Nitride layer.
6. The III-Nitride semiconductor device of claim 1, wherein said gate contact is a Schottky contact.
7. The III-Nitride semiconductor device of claim 1, wherein said gate contact is insulated from said first III-Nitride layer.
8. The III-Nitride semiconductor device of claim 1, which further includes a highly conductive III-Nitride pad disposed between said source and drain contacts.
9. The III-Nitride semiconductor device of claim 1, wherein said conductive field plate comprises a layer of highly conductive N+ III-Nitride material.
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